OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [insight/] [sim/] [i960/] [i960-desc.c] - Blame information for rev 1767

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 markom 
/* CPU data for i960.
2 
 
3 
THIS FILE IS MACHINE GENERATED WITH CGEN.
4 
 
5 
Copyright (C) 1996, 1997, 1998, 1999, 2001 Free Software Foundation, Inc.
6 
 
7 
This file is part of the GNU Binutils and/or GDB, the GNU debugger.
8 
 
9 
This program is free software; you can redistribute it and/or modify
10 
it under the terms of the GNU General Public License as published by
11 
the Free Software Foundation; either version 2, or (at your option)
12 
any later version.
13 
 
14 
This program is distributed in the hope that it will be useful,
15 
but WITHOUT ANY WARRANTY; without even the implied warranty of
16 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
17 
GNU General Public License for more details.
18 
 
19 
You should have received a copy of the GNU General Public License along
20 
with this program; if not, write to the Free Software Foundation, Inc.,
21 
59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
22 
 
23 
*/
24 
 
25 
#include "sysdep.h"
26 
#include <ctype.h>
27 
#include <stdio.h>
28 
#include <stdarg.h>
29 
#include "ansidecl.h"
30 
#include "bfd.h"
31 
#include "symcat.h"
32 
#include "i960-desc.h"
33 
#include "i960-opc.h"
34 
#include "opintl.h"
35 
 
36 
/* Attributes.  */
37 
 
38 
static const CGEN_ATTR_ENTRY bool_attr[] =
39 
{
40 
  { "#f", 0 },
41 
  { "#t", 1 },
42 
  { 0, 0 }
43 
};
44 
 
45 
static const CGEN_ATTR_ENTRY MACH_attr[] =
46 
{
47 
  { "base", MACH_BASE },
48 
  { "i960_ka_sa", MACH_I960_KA_SA },
49 
  { "i960_ca", MACH_I960_CA },
50 
  { "max", MACH_MAX },
51 
  { 0, 0 }
52 
};
53 
 
54 
static const CGEN_ATTR_ENTRY ISA_attr[] =
55 
{
56 
  { "i960", ISA_I960 },
57 
  { "max", ISA_MAX },
58 
  { 0, 0 }
59 
};
60 
 
61 
const CGEN_ATTR_TABLE i960_cgen_ifield_attr_table[] =
62 
{
63 
  { "MACH", & MACH_attr[0] },
64 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
65 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
66 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
67 
  { "RESERVED", &bool_attr[0], &bool_attr[0] },
68 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
69 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
70 
  { 0, 0, 0 }
71 
};
72 
 
73 
const CGEN_ATTR_TABLE i960_cgen_hardware_attr_table[] =
74 
{
75 
  { "MACH", & MACH_attr[0] },
76 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
77 
  { "CACHE-ADDR", &bool_attr[0], &bool_attr[0] },
78 
  { "PC", &bool_attr[0], &bool_attr[0] },
79 
  { "PROFILE", &bool_attr[0], &bool_attr[0] },
80 
  { 0, 0, 0 }
81 
};
82 
 
83 
const CGEN_ATTR_TABLE i960_cgen_operand_attr_table[] =
84 
{
85 
  { "MACH", & MACH_attr[0] },
86 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
87 
  { "PCREL-ADDR", &bool_attr[0], &bool_attr[0] },
88 
  { "ABS-ADDR", &bool_attr[0], &bool_attr[0] },
89 
  { "SIGN-OPT", &bool_attr[0], &bool_attr[0] },
90 
  { "SIGNED", &bool_attr[0], &bool_attr[0] },
91 
  { "NEGATIVE", &bool_attr[0], &bool_attr[0] },
92 
  { "RELAX", &bool_attr[0], &bool_attr[0] },
93 
  { "SEM-ONLY", &bool_attr[0], &bool_attr[0] },
94 
  { 0, 0, 0 }
95 
};
96 
 
97 
const CGEN_ATTR_TABLE i960_cgen_insn_attr_table[] =
98 
{
99 
  { "MACH", & MACH_attr[0] },
100 
  { "ALIAS", &bool_attr[0], &bool_attr[0] },
101 
  { "VIRTUAL", &bool_attr[0], &bool_attr[0] },
102 
  { "UNCOND-CTI", &bool_attr[0], &bool_attr[0] },
103 
  { "COND-CTI", &bool_attr[0], &bool_attr[0] },
104 
  { "SKIP-CTI", &bool_attr[0], &bool_attr[0] },
105 
  { "DELAY-SLOT", &bool_attr[0], &bool_attr[0] },
106 
  { "RELAXABLE", &bool_attr[0], &bool_attr[0] },
107 
  { "RELAX", &bool_attr[0], &bool_attr[0] },
108 
  { "NO-DIS", &bool_attr[0], &bool_attr[0] },
109 
  { "PBB", &bool_attr[0], &bool_attr[0] },
110 
  { 0, 0, 0 }
111 
};
112 
 
113 
/* Instruction set variants.  */
114 
 
115 
static const CGEN_ISA i960_cgen_isa_table[] = {
116 
  { "i960", 32, 32, 32, 64,  },
117 
  { 0 }
118 
};
119 
 
120 
/* Machine variants.  */
121 
 
122 
static const CGEN_MACH i960_cgen_mach_table[] = {
123 
  { "i960:ka_sa", "i960:ka_sa", MACH_I960_KA_SA },
124 
  { "i960:ca", "i960:ca", MACH_I960_CA },
125 
  { 0 }
126 
};
127 
 
128 
static CGEN_KEYWORD_ENTRY i960_cgen_opval_h_gr_entries[] =
129 
{
130 
  { "fp", 31 },
131 
  { "sp", 1 },
132 
  { "r0", 0 },
133 
  { "r1", 1 },
134 
  { "r2", 2 },
135 
  { "r3", 3 },
136 
  { "r4", 4 },
137 
  { "r5", 5 },
138 
  { "r6", 6 },
139 
  { "r7", 7 },
140 
  { "r8", 8 },
141 
  { "r9", 9 },
142 
  { "r10", 10 },
143 
  { "r11", 11 },
144 
  { "r12", 12 },
145 
  { "r13", 13 },
146 
  { "r14", 14 },
147 
  { "r15", 15 },
148 
  { "g0", 16 },
149 
  { "g1", 17 },
150 
  { "g2", 18 },
151 
  { "g3", 19 },
152 
  { "g4", 20 },
153 
  { "g5", 21 },
154 
  { "g6", 22 },
155 
  { "g7", 23 },
156 
  { "g8", 24 },
157 
  { "g9", 25 },
158 
  { "g10", 26 },
159 
  { "g11", 27 },
160 
  { "g12", 28 },
161 
  { "g13", 29 },
162 
  { "g14", 30 },
163 
  { "g15", 31 }
164 
};
165 
 
166 
CGEN_KEYWORD i960_cgen_opval_h_gr =
167 
{
168 
  & i960_cgen_opval_h_gr_entries[0],
169 
  34
170 
};
171 
 
172 
static CGEN_KEYWORD_ENTRY i960_cgen_opval_h_cc_entries[] =
173 
{
174 
  { "cc", 0 }
175 
};
176 
 
177 
CGEN_KEYWORD i960_cgen_opval_h_cc =
178 
{
179 
  & i960_cgen_opval_h_cc_entries[0],
180 
  1
181 
};
182 
 
183 
 
184 
 
185 
/* The hardware table.  */
186 
 
187 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
188 
#define A(a) (1 << CGEN_HW_##a)
189 
#else
190 
#define A(a) (1 << CGEN_HW_/**/a)
191 
#endif
192 
 
193 
const CGEN_HW_ENTRY i960_cgen_hw_table[] =
194 
{
195 
  { "h-memory", HW_H_MEMORY, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
196 
  { "h-sint", HW_H_SINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
197 
  { "h-uint", HW_H_UINT, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
198 
  { "h-addr", HW_H_ADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
199 
  { "h-iaddr", HW_H_IADDR, CGEN_ASM_NONE, 0, { 0, { (1<<MACH_BASE) } } },
200 
  { "h-pc", HW_H_PC, CGEN_ASM_NONE, 0, { 0|A(PROFILE)|A(PC), { (1<<MACH_BASE) } } },
201 
  { "h-gr", HW_H_GR, CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_gr, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
202 
  { "h-cc", HW_H_CC, CGEN_ASM_KEYWORD, (PTR) & i960_cgen_opval_h_cc, { 0|A(CACHE_ADDR)|A(PROFILE), { (1<<MACH_BASE) } } },
203 
  { 0 }
204 
};
205 
 
206 
#undef A
207 
 
208 
/* The instruction field table.  */
209 
 
210 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
211 
#define A(a) (1 << CGEN_IFLD_##a)
212 
#else
213 
#define A(a) (1 << CGEN_IFLD_/**/a)
214 
#endif
215 
 
216 
const CGEN_IFLD i960_cgen_ifld_table[] =
217 
{
218 
  { I960_F_NIL, "f-nil", 0, 0, 0, 0, { 0, { (1<<MACH_BASE) } }  },
219 
  { I960_F_OPCODE, "f-opcode", 0, 32, 0, 8, { 0, { (1<<MACH_BASE) } }  },
220 
  { I960_F_SRCDST, "f-srcdst", 0, 32, 8, 5, { 0, { (1<<MACH_BASE) } }  },
221 
  { I960_F_SRC2, "f-src2", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } }  },
222 
  { I960_F_M3, "f-m3", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } }  },
223 
  { I960_F_M2, "f-m2", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } }  },
224 
  { I960_F_M1, "f-m1", 0, 32, 20, 1, { 0, { (1<<MACH_BASE) } }  },
225 
  { I960_F_OPCODE2, "f-opcode2", 0, 32, 21, 4, { 0, { (1<<MACH_BASE) } }  },
226 
  { I960_F_ZERO, "f-zero", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
227 
  { I960_F_SRC1, "f-src1", 0, 32, 27, 5, { 0, { (1<<MACH_BASE) } }  },
228 
  { I960_F_ABASE, "f-abase", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } }  },
229 
  { I960_F_MODEA, "f-modea", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } }  },
230 
  { I960_F_ZEROA, "f-zeroa", 0, 32, 19, 1, { 0, { (1<<MACH_BASE) } }  },
231 
  { I960_F_OFFSET, "f-offset", 0, 32, 20, 12, { 0, { (1<<MACH_BASE) } }  },
232 
  { I960_F_MODEB, "f-modeb", 0, 32, 18, 4, { 0, { (1<<MACH_BASE) } }  },
233 
  { I960_F_SCALE, "f-scale", 0, 32, 22, 3, { 0, { (1<<MACH_BASE) } }  },
234 
  { I960_F_ZEROB, "f-zerob", 0, 32, 25, 2, { 0, { (1<<MACH_BASE) } }  },
235 
  { I960_F_INDEX, "f-index", 0, 32, 27, 5, { 0, { (1<<MACH_BASE) } }  },
236 
  { I960_F_OPTDISP, "f-optdisp", 32, 32, 0, 32, { 0, { (1<<MACH_BASE) } }  },
237 
  { I960_F_BR_SRC1, "f-br-src1", 0, 32, 8, 5, { 0, { (1<<MACH_BASE) } }  },
238 
  { I960_F_BR_SRC2, "f-br-src2", 0, 32, 13, 5, { 0, { (1<<MACH_BASE) } }  },
239 
  { I960_F_BR_M1, "f-br-m1", 0, 32, 18, 1, { 0, { (1<<MACH_BASE) } }  },
240 
  { I960_F_BR_DISP, "f-br-disp", 0, 32, 19, 11, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
241 
  { I960_F_BR_ZERO, "f-br-zero", 0, 32, 30, 2, { 0, { (1<<MACH_BASE) } }  },
242 
  { I960_F_CTRL_DISP, "f-ctrl-disp", 0, 32, 8, 22, { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
243 
  { I960_F_CTRL_ZERO, "f-ctrl-zero", 0, 32, 30, 2, { 0, { (1<<MACH_BASE) } }  },
244 
  { 0 }
245 
};
246 
 
247 
#undef A
248 
 
249 
/* The operand table.  */
250 
 
251 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
252 
#define A(a) (1 << CGEN_OPERAND_##a)
253 
#else
254 
#define A(a) (1 << CGEN_OPERAND_/**/a)
255 
#endif
256 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
257 
#define OPERAND(op) I960_OPERAND_##op
258 
#else
259 
#define OPERAND(op) I960_OPERAND_/**/op
260 
#endif
261 
 
262 
const CGEN_OPERAND i960_cgen_operand_table[] =
263 
{
264 
/* pc: program counter */
265 
  { "pc", I960_OPERAND_PC, HW_H_PC, 0, 0,
266 
    { 0|A(SEM_ONLY), { (1<<MACH_BASE) } }  },
267 
/* src1: source register 1 */
268 
  { "src1", I960_OPERAND_SRC1, HW_H_GR, 27, 5,
269 
    { 0, { (1<<MACH_BASE) } }  },
270 
/* src2: source register 2 */
271 
  { "src2", I960_OPERAND_SRC2, HW_H_GR, 13, 5,
272 
    { 0, { (1<<MACH_BASE) } }  },
273 
/* dst: source/dest register */
274 
  { "dst", I960_OPERAND_DST, HW_H_GR, 8, 5,
275 
    { 0, { (1<<MACH_BASE) } }  },
276 
/* lit1: literal 1 */
277 
  { "lit1", I960_OPERAND_LIT1, HW_H_UINT, 27, 5,
278 
    { 0, { (1<<MACH_BASE) } }  },
279 
/* lit2: literal 2 */
280 
  { "lit2", I960_OPERAND_LIT2, HW_H_UINT, 13, 5,
281 
    { 0, { (1<<MACH_BASE) } }  },
282 
/* st_src: store src */
283 
  { "st_src", I960_OPERAND_ST_SRC, HW_H_GR, 8, 5,
284 
    { 0, { (1<<MACH_BASE) } }  },
285 
/* abase: abase */
286 
  { "abase", I960_OPERAND_ABASE, HW_H_GR, 13, 5,
287 
    { 0, { (1<<MACH_BASE) } }  },
288 
/* offset: offset */
289 
  { "offset", I960_OPERAND_OFFSET, HW_H_UINT, 20, 12,
290 
    { 0, { (1<<MACH_BASE) } }  },
291 
/* scale: scale */
292 
  { "scale", I960_OPERAND_SCALE, HW_H_UINT, 22, 3,
293 
    { 0, { (1<<MACH_BASE) } }  },
294 
/* index: index */
295 
  { "index", I960_OPERAND_INDEX, HW_H_GR, 27, 5,
296 
    { 0, { (1<<MACH_BASE) } }  },
297 
/* optdisp: optional displacement */
298 
  { "optdisp", I960_OPERAND_OPTDISP, HW_H_UINT, 0, 32,
299 
    { 0, { (1<<MACH_BASE) } }  },
300 
/* br_src1: branch src1 */
301 
  { "br_src1", I960_OPERAND_BR_SRC1, HW_H_GR, 8, 5,
302 
    { 0, { (1<<MACH_BASE) } }  },
303 
/* br_src2: branch src2 */
304 
  { "br_src2", I960_OPERAND_BR_SRC2, HW_H_GR, 13, 5,
305 
    { 0, { (1<<MACH_BASE) } }  },
306 
/* br_disp: branch displacement */
307 
  { "br_disp", I960_OPERAND_BR_DISP, HW_H_IADDR, 19, 11,
308 
    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
309 
/* br_lit1: branch literal 1 */
310 
  { "br_lit1", I960_OPERAND_BR_LIT1, HW_H_UINT, 8, 5,
311 
    { 0, { (1<<MACH_BASE) } }  },
312 
/* ctrl_disp: ctrl branch disp */
313 
  { "ctrl_disp", I960_OPERAND_CTRL_DISP, HW_H_IADDR, 8, 22,
314 
    { 0|A(PCREL_ADDR), { (1<<MACH_BASE) } }  },
315 
  { 0 }
316 
};
317 
 
318 
#undef A
319 
 
320 
#define OP(field) CGEN_SYNTAX_MAKE_FIELD (OPERAND (field))
321 
#if defined (__STDC__) || defined (ALMOST_STDC) || defined (HAVE_STRINGIZE)
322 
#define A(a) (1 << CGEN_INSN_##a)
323 
#else
324 
#define A(a) (1 << CGEN_INSN_/**/a)
325 
#endif
326 
 
327 
/* The instruction table.  */
328 
 
329 
static const CGEN_IBASE i960_cgen_insn_table[MAX_INSNS] =
330 
{
331 
  /* Special null first entry.
332 
     A `num' value of zero is thus invalid.
333 
     Also, the special `invalid' insn resides here.  */
334 
  { 0, 0, 0 },
335 
/* mulo $src1, $src2, $dst */
336 
  {
337 
    I960_INSN_MULO, "mulo", "mulo", 32,
338 
    { 0, { (1<<MACH_BASE) } }
339 
  },
340 
/* mulo $lit1, $src2, $dst */
341 
  {
342 
    I960_INSN_MULO1, "mulo1", "mulo", 32,
343 
    { 0, { (1<<MACH_BASE) } }
344 
  },
345 
/* mulo $src1, $lit2, $dst */
346 
  {
347 
    I960_INSN_MULO2, "mulo2", "mulo", 32,
348 
    { 0, { (1<<MACH_BASE) } }
349 
  },
350 
/* mulo $lit1, $lit2, $dst */
351 
  {
352 
    I960_INSN_MULO3, "mulo3", "mulo", 32,
353 
    { 0, { (1<<MACH_BASE) } }
354 
  },
355 
/* remo $src1, $src2, $dst */
356 
  {
357 
    I960_INSN_REMO, "remo", "remo", 32,
358 
    { 0, { (1<<MACH_BASE) } }
359 
  },
360 
/* remo $lit1, $src2, $dst */
361 
  {
362 
    I960_INSN_REMO1, "remo1", "remo", 32,
363 
    { 0, { (1<<MACH_BASE) } }
364 
  },
365 
/* remo $src1, $lit2, $dst */
366 
  {
367 
    I960_INSN_REMO2, "remo2", "remo", 32,
368 
    { 0, { (1<<MACH_BASE) } }
369 
  },
370 
/* remo $lit1, $lit2, $dst */
371 
  {
372 
    I960_INSN_REMO3, "remo3", "remo", 32,
373 
    { 0, { (1<<MACH_BASE) } }
374 
  },
375 
/* divo $src1, $src2, $dst */
376 
  {
377 
    I960_INSN_DIVO, "divo", "divo", 32,
378 
    { 0, { (1<<MACH_BASE) } }
379 
  },
380 
/* divo $lit1, $src2, $dst */
381 
  {
382 
    I960_INSN_DIVO1, "divo1", "divo", 32,
383 
    { 0, { (1<<MACH_BASE) } }
384 
  },
385 
/* divo $src1, $lit2, $dst */
386 
  {
387 
    I960_INSN_DIVO2, "divo2", "divo", 32,
388 
    { 0, { (1<<MACH_BASE) } }
389 
  },
390 
/* divo $lit1, $lit2, $dst */
391 
  {
392 
    I960_INSN_DIVO3, "divo3", "divo", 32,
393 
    { 0, { (1<<MACH_BASE) } }
394 
  },
395 
/* remi $src1, $src2, $dst */
396 
  {
397 
    I960_INSN_REMI, "remi", "remi", 32,
398 
    { 0, { (1<<MACH_BASE) } }
399 
  },
400 
/* remi $lit1, $src2, $dst */
401 
  {
402 
    I960_INSN_REMI1, "remi1", "remi", 32,
403 
    { 0, { (1<<MACH_BASE) } }
404 
  },
405 
/* remi $src1, $lit2, $dst */
406 
  {
407 
    I960_INSN_REMI2, "remi2", "remi", 32,
408 
    { 0, { (1<<MACH_BASE) } }
409 
  },
410 
/* remi $lit1, $lit2, $dst */
411 
  {
412 
    I960_INSN_REMI3, "remi3", "remi", 32,
413 
    { 0, { (1<<MACH_BASE) } }
414 
  },
415 
/* divi $src1, $src2, $dst */
416 
  {
417 
    I960_INSN_DIVI, "divi", "divi", 32,
418 
    { 0, { (1<<MACH_BASE) } }
419 
  },
420 
/* divi $lit1, $src2, $dst */
421 
  {
422 
    I960_INSN_DIVI1, "divi1", "divi", 32,
423 
    { 0, { (1<<MACH_BASE) } }
424 
  },
425 
/* divi $src1, $lit2, $dst */
426 
  {
427 
    I960_INSN_DIVI2, "divi2", "divi", 32,
428 
    { 0, { (1<<MACH_BASE) } }
429 
  },
430 
/* divi $lit1, $lit2, $dst */
431 
  {
432 
    I960_INSN_DIVI3, "divi3", "divi", 32,
433 
    { 0, { (1<<MACH_BASE) } }
434 
  },
435 
/* addo $src1, $src2, $dst */
436 
  {
437 
    I960_INSN_ADDO, "addo", "addo", 32,
438 
    { 0, { (1<<MACH_BASE) } }
439 
  },
440 
/* addo $lit1, $src2, $dst */
441 
  {
442 
    I960_INSN_ADDO1, "addo1", "addo", 32,
443 
    { 0, { (1<<MACH_BASE) } }
444 
  },
445 
/* addo $src1, $lit2, $dst */
446 
  {
447 
    I960_INSN_ADDO2, "addo2", "addo", 32,
448 
    { 0, { (1<<MACH_BASE) } }
449 
  },
450 
/* addo $lit1, $lit2, $dst */
451 
  {
452 
    I960_INSN_ADDO3, "addo3", "addo", 32,
453 
    { 0, { (1<<MACH_BASE) } }
454 
  },
455 
/* subo $src1, $src2, $dst */
456 
  {
457 
    I960_INSN_SUBO, "subo", "subo", 32,
458 
    { 0, { (1<<MACH_BASE) } }
459 
  },
460 
/* subo $lit1, $src2, $dst */
461 
  {
462 
    I960_INSN_SUBO1, "subo1", "subo", 32,
463 
    { 0, { (1<<MACH_BASE) } }
464 
  },
465 
/* subo $src1, $lit2, $dst */
466 
  {
467 
    I960_INSN_SUBO2, "subo2", "subo", 32,
468 
    { 0, { (1<<MACH_BASE) } }
469 
  },
470 
/* subo $lit1, $lit2, $dst */
471 
  {
472 
    I960_INSN_SUBO3, "subo3", "subo", 32,
473 
    { 0, { (1<<MACH_BASE) } }
474 
  },
475 
/* notbit $src1, $src2, $dst */
476 
  {
477 
    I960_INSN_NOTBIT, "notbit", "notbit", 32,
478 
    { 0, { (1<<MACH_BASE) } }
479 
  },
480 
/* notbit $lit1, $src2, $dst */
481 
  {
482 
    I960_INSN_NOTBIT1, "notbit1", "notbit", 32,
483 
    { 0, { (1<<MACH_BASE) } }
484 
  },
485 
/* notbit $src1, $lit2, $dst */
486 
  {
487 
    I960_INSN_NOTBIT2, "notbit2", "notbit", 32,
488 
    { 0, { (1<<MACH_BASE) } }
489 
  },
490 
/* notbit $lit1, $lit2, $dst */
491 
  {
492 
    I960_INSN_NOTBIT3, "notbit3", "notbit", 32,
493 
    { 0, { (1<<MACH_BASE) } }
494 
  },
495 
/* and $src1, $src2, $dst */
496 
  {
497 
    I960_INSN_AND, "and", "and", 32,
498 
    { 0, { (1<<MACH_BASE) } }
499 
  },
500 
/* and $lit1, $src2, $dst */
501 
  {
502 
    I960_INSN_AND1, "and1", "and", 32,
503 
    { 0, { (1<<MACH_BASE) } }
504 
  },
505 
/* and $src1, $lit2, $dst */
506 
  {
507 
    I960_INSN_AND2, "and2", "and", 32,
508 
    { 0, { (1<<MACH_BASE) } }
509 
  },
510 
/* and $lit1, $lit2, $dst */
511 
  {
512 
    I960_INSN_AND3, "and3", "and", 32,
513 
    { 0, { (1<<MACH_BASE) } }
514 
  },
515 
/* andnot $src1, $src2, $dst */
516 
  {
517 
    I960_INSN_ANDNOT, "andnot", "andnot", 32,
518 
    { 0, { (1<<MACH_BASE) } }
519 
  },
520 
/* andnot $lit1, $src2, $dst */
521 
  {
522 
    I960_INSN_ANDNOT1, "andnot1", "andnot", 32,
523 
    { 0, { (1<<MACH_BASE) } }
524 
  },
525 
/* andnot $src1, $lit2, $dst */
526 
  {
527 
    I960_INSN_ANDNOT2, "andnot2", "andnot", 32,
528 
    { 0, { (1<<MACH_BASE) } }
529 
  },
530 
/* andnot $lit1, $lit2, $dst */
531 
  {
532 
    I960_INSN_ANDNOT3, "andnot3", "andnot", 32,
533 
    { 0, { (1<<MACH_BASE) } }
534 
  },
535 
/* setbit $src1, $src2, $dst */
536 
  {
537 
    I960_INSN_SETBIT, "setbit", "setbit", 32,
538 
    { 0, { (1<<MACH_BASE) } }
539 
  },
540 
/* setbit $lit1, $src2, $dst */
541 
  {
542 
    I960_INSN_SETBIT1, "setbit1", "setbit", 32,
543 
    { 0, { (1<<MACH_BASE) } }
544 
  },
545 
/* setbit $src1, $lit2, $dst */
546 
  {
547 
    I960_INSN_SETBIT2, "setbit2", "setbit", 32,
548 
    { 0, { (1<<MACH_BASE) } }
549 
  },
550 
/* setbit $lit1, $lit2, $dst */
551 
  {
552 
    I960_INSN_SETBIT3, "setbit3", "setbit", 32,
553 
    { 0, { (1<<MACH_BASE) } }
554 
  },
555 
/* notand $src1, $src2, $dst */
556 
  {
557 
    I960_INSN_NOTAND, "notand", "notand", 32,
558 
    { 0, { (1<<MACH_BASE) } }
559 
  },
560 
/* notand $lit1, $src2, $dst */
561 
  {
562 
    I960_INSN_NOTAND1, "notand1", "notand", 32,
563 
    { 0, { (1<<MACH_BASE) } }
564 
  },
565 
/* notand $src1, $lit2, $dst */
566 
  {
567 
    I960_INSN_NOTAND2, "notand2", "notand", 32,
568 
    { 0, { (1<<MACH_BASE) } }
569 
  },
570 
/* notand $lit1, $lit2, $dst */
571 
  {
572 
    I960_INSN_NOTAND3, "notand3", "notand", 32,
573 
    { 0, { (1<<MACH_BASE) } }
574 
  },
575 
/* xor $src1, $src2, $dst */
576 
  {
577 
    I960_INSN_XOR, "xor", "xor", 32,
578 
    { 0, { (1<<MACH_BASE) } }
579 
  },
580 
/* xor $lit1, $src2, $dst */
581 
  {
582 
    I960_INSN_XOR1, "xor1", "xor", 32,
583 
    { 0, { (1<<MACH_BASE) } }
584 
  },
585 
/* xor $src1, $lit2, $dst */
586 
  {
587 
    I960_INSN_XOR2, "xor2", "xor", 32,
588 
    { 0, { (1<<MACH_BASE) } }
589 
  },
590 
/* xor $lit1, $lit2, $dst */
591 
  {
592 
    I960_INSN_XOR3, "xor3", "xor", 32,
593 
    { 0, { (1<<MACH_BASE) } }
594 
  },
595 
/* or $src1, $src2, $dst */
596 
  {
597 
    I960_INSN_OR, "or", "or", 32,
598 
    { 0, { (1<<MACH_BASE) } }
599 
  },
600 
/* or $lit1, $src2, $dst */
601 
  {
602 
    I960_INSN_OR1, "or1", "or", 32,
603 
    { 0, { (1<<MACH_BASE) } }
604 
  },
605 
/* or $src1, $lit2, $dst */
606 
  {
607 
    I960_INSN_OR2, "or2", "or", 32,
608 
    { 0, { (1<<MACH_BASE) } }
609 
  },
610 
/* or $lit1, $lit2, $dst */
611 
  {
612 
    I960_INSN_OR3, "or3", "or", 32,
613 
    { 0, { (1<<MACH_BASE) } }
614 
  },
615 
/* nor $src1, $src2, $dst */
616 
  {
617 
    I960_INSN_NOR, "nor", "nor", 32,
618 
    { 0, { (1<<MACH_BASE) } }
619 
  },
620 
/* nor $lit1, $src2, $dst */
621 
  {
622 
    I960_INSN_NOR1, "nor1", "nor", 32,
623 
    { 0, { (1<<MACH_BASE) } }
624 
  },
625 
/* nor $src1, $lit2, $dst */
626 
  {
627 
    I960_INSN_NOR2, "nor2", "nor", 32,
628 
    { 0, { (1<<MACH_BASE) } }
629 
  },
630 
/* nor $lit1, $lit2, $dst */
631 
  {
632 
    I960_INSN_NOR3, "nor3", "nor", 32,
633 
    { 0, { (1<<MACH_BASE) } }
634 
  },
635 
/* xnor $src1, $src2, $dst */
636 
  {
637 
    I960_INSN_XNOR, "xnor", "xnor", 32,
638 
    { 0, { (1<<MACH_BASE) } }
639 
  },
640 
/* xnor $lit1, $src2, $dst */
641 
  {
642 
    I960_INSN_XNOR1, "xnor1", "xnor", 32,
643 
    { 0, { (1<<MACH_BASE) } }
644 
  },
645 
/* xnor $src1, $lit2, $dst */
646 
  {
647 
    I960_INSN_XNOR2, "xnor2", "xnor", 32,
648 
    { 0, { (1<<MACH_BASE) } }
649 
  },
650 
/* xnor $lit1, $lit2, $dst */
651 
  {
652 
    I960_INSN_XNOR3, "xnor3", "xnor", 32,
653 
    { 0, { (1<<MACH_BASE) } }
654 
  },
655 
/* not $src1, $src2, $dst */
656 
  {
657 
    I960_INSN_NOT, "not", "not", 32,
658 
    { 0, { (1<<MACH_BASE) } }
659 
  },
660 
/* not $lit1, $src2, $dst */
661 
  {
662 
    I960_INSN_NOT1, "not1", "not", 32,
663 
    { 0, { (1<<MACH_BASE) } }
664 
  },
665 
/* not $src1, $lit2, $dst */
666 
  {
667 
    I960_INSN_NOT2, "not2", "not", 32,
668 
    { 0, { (1<<MACH_BASE) } }
669 
  },
670 
/* not $lit1, $lit2, $dst */
671 
  {
672 
    I960_INSN_NOT3, "not3", "not", 32,
673 
    { 0, { (1<<MACH_BASE) } }
674 
  },
675 
/* ornot $src1, $src2, $dst */
676 
  {
677 
    I960_INSN_ORNOT, "ornot", "ornot", 32,
678 
    { 0, { (1<<MACH_BASE) } }
679 
  },
680 
/* ornot $lit1, $src2, $dst */
681 
  {
682 
    I960_INSN_ORNOT1, "ornot1", "ornot", 32,
683 
    { 0, { (1<<MACH_BASE) } }
684 
  },
685 
/* ornot $src1, $lit2, $dst */
686 
  {
687 
    I960_INSN_ORNOT2, "ornot2", "ornot", 32,
688 
    { 0, { (1<<MACH_BASE) } }
689 
  },
690 
/* ornot $lit1, $lit2, $dst */
691 
  {
692 
    I960_INSN_ORNOT3, "ornot3", "ornot", 32,
693 
    { 0, { (1<<MACH_BASE) } }
694 
  },
695 
/* clrbit $src1, $src2, $dst */
696 
  {
697 
    I960_INSN_CLRBIT, "clrbit", "clrbit", 32,
698 
    { 0, { (1<<MACH_BASE) } }
699 
  },
700 
/* clrbit $lit1, $src2, $dst */
701 
  {
702 
    I960_INSN_CLRBIT1, "clrbit1", "clrbit", 32,
703 
    { 0, { (1<<MACH_BASE) } }
704 
  },
705 
/* clrbit $src1, $lit2, $dst */
706 
  {
707 
    I960_INSN_CLRBIT2, "clrbit2", "clrbit", 32,
708 
    { 0, { (1<<MACH_BASE) } }
709 
  },
710 
/* clrbit $lit1, $lit2, $dst */
711 
  {
712 
    I960_INSN_CLRBIT3, "clrbit3", "clrbit", 32,
713 
    { 0, { (1<<MACH_BASE) } }
714 
  },
715 
/* shlo $src1, $src2, $dst */
716 
  {
717 
    I960_INSN_SHLO, "shlo", "shlo", 32,
718 
    { 0, { (1<<MACH_BASE) } }
719 
  },
720 
/* shlo $lit1, $src2, $dst */
721 
  {
722 
    I960_INSN_SHLO1, "shlo1", "shlo", 32,
723 
    { 0, { (1<<MACH_BASE) } }
724 
  },
725 
/* shlo $src1, $lit2, $dst */
726 
  {
727 
    I960_INSN_SHLO2, "shlo2", "shlo", 32,
728 
    { 0, { (1<<MACH_BASE) } }
729 
  },
730 
/* shlo $lit1, $lit2, $dst */
731 
  {
732 
    I960_INSN_SHLO3, "shlo3", "shlo", 32,
733 
    { 0, { (1<<MACH_BASE) } }
734 
  },
735 
/* shro $src1, $src2, $dst */
736 
  {
737 
    I960_INSN_SHRO, "shro", "shro", 32,
738 
    { 0, { (1<<MACH_BASE) } }
739 
  },
740 
/* shro $lit1, $src2, $dst */
741 
  {
742 
    I960_INSN_SHRO1, "shro1", "shro", 32,
743 
    { 0, { (1<<MACH_BASE) } }
744 
  },
745 
/* shro $src1, $lit2, $dst */
746 
  {
747 
    I960_INSN_SHRO2, "shro2", "shro", 32,
748 
    { 0, { (1<<MACH_BASE) } }
749 
  },
750 
/* shro $lit1, $lit2, $dst */
751 
  {
752 
    I960_INSN_SHRO3, "shro3", "shro", 32,
753 
    { 0, { (1<<MACH_BASE) } }
754 
  },
755 
/* shli $src1, $src2, $dst */
756 
  {
757 
    I960_INSN_SHLI, "shli", "shli", 32,
758 
    { 0, { (1<<MACH_BASE) } }
759 
  },
760 
/* shli $lit1, $src2, $dst */
761 
  {
762 
    I960_INSN_SHLI1, "shli1", "shli", 32,
763 
    { 0, { (1<<MACH_BASE) } }
764 
  },
765 
/* shli $src1, $lit2, $dst */
766 
  {
767 
    I960_INSN_SHLI2, "shli2", "shli", 32,
768 
    { 0, { (1<<MACH_BASE) } }
769 
  },
770 
/* shli $lit1, $lit2, $dst */
771 
  {
772 
    I960_INSN_SHLI3, "shli3", "shli", 32,
773 
    { 0, { (1<<MACH_BASE) } }
774 
  },
775 
/* shri $src1, $src2, $dst */
776 
  {
777 
    I960_INSN_SHRI, "shri", "shri", 32,
778 
    { 0, { (1<<MACH_BASE) } }
779 
  },
780 
/* shri $lit1, $src2, $dst */
781 
  {
782 
    I960_INSN_SHRI1, "shri1", "shri", 32,
783 
    { 0, { (1<<MACH_BASE) } }
784 
  },
785 
/* shri $src1, $lit2, $dst */
786 
  {
787 
    I960_INSN_SHRI2, "shri2", "shri", 32,
788 
    { 0, { (1<<MACH_BASE) } }
789 
  },
790 
/* shri $lit1, $lit2, $dst */
791 
  {
792 
    I960_INSN_SHRI3, "shri3", "shri", 32,
793 
    { 0, { (1<<MACH_BASE) } }
794 
  },
795 
/* emul $src1, $src2, $dst */
796 
  {
797 
    I960_INSN_EMUL, "emul", "emul", 32,
798 
    { 0, { (1<<MACH_BASE) } }
799 
  },
800 
/* emul $lit1, $src2, $dst */
801 
  {
802 
    I960_INSN_EMUL1, "emul1", "emul", 32,
803 
    { 0, { (1<<MACH_BASE) } }
804 
  },
805 
/* emul $src1, $lit2, $dst */
806 
  {
807 
    I960_INSN_EMUL2, "emul2", "emul", 32,
808 
    { 0, { (1<<MACH_BASE) } }
809 
  },
810 
/* emul $lit1, $lit2, $dst */
811 
  {
812 
    I960_INSN_EMUL3, "emul3", "emul", 32,
813 
    { 0, { (1<<MACH_BASE) } }
814 
  },
815 
/* mov $src1, $dst */
816 
  {
817 
    I960_INSN_MOV, "mov", "mov", 32,
818 
    { 0, { (1<<MACH_BASE) } }
819 
  },
820 
/* mov $lit1, $dst */
821 
  {
822 
    I960_INSN_MOV1, "mov1", "mov", 32,
823 
    { 0, { (1<<MACH_BASE) } }
824 
  },
825 
/* movl $src1, $dst */
826 
  {
827 
    I960_INSN_MOVL, "movl", "movl", 32,
828 
    { 0, { (1<<MACH_BASE) } }
829 
  },
830 
/* movl $lit1, $dst */
831 
  {
832 
    I960_INSN_MOVL1, "movl1", "movl", 32,
833 
    { 0, { (1<<MACH_BASE) } }
834 
  },
835 
/* movt $src1, $dst */
836 
  {
837 
    I960_INSN_MOVT, "movt", "movt", 32,
838 
    { 0, { (1<<MACH_BASE) } }
839 
  },
840 
/* movt $lit1, $dst */
841 
  {
842 
    I960_INSN_MOVT1, "movt1", "movt", 32,
843 
    { 0, { (1<<MACH_BASE) } }
844 
  },
845 
/* movq $src1, $dst */
846 
  {
847 
    I960_INSN_MOVQ, "movq", "movq", 32,
848 
    { 0, { (1<<MACH_BASE) } }
849 
  },
850 
/* movq $lit1, $dst */
851 
  {
852 
    I960_INSN_MOVQ1, "movq1", "movq", 32,
853 
    { 0, { (1<<MACH_BASE) } }
854 
  },
855 
/* modpc $src1, $src2, $dst */
856 
  {
857 
    I960_INSN_MODPC, "modpc", "modpc", 32,
858 
    { 0, { (1<<MACH_BASE) } }
859 
  },
860 
/* modac $src1, $src2, $dst */
861 
  {
862 
    I960_INSN_MODAC, "modac", "modac", 32,
863 
    { 0, { (1<<MACH_BASE) } }
864 
  },
865 
/* lda $offset, $dst */
866 
  {
867 
    I960_INSN_LDA_OFFSET, "lda-offset", "lda", 32,
868 
    { 0, { (1<<MACH_BASE) } }
869 
  },
870 
/* lda $offset($abase), $dst */
871 
  {
872 
    I960_INSN_LDA_INDIRECT_OFFSET, "lda-indirect-offset", "lda", 32,
873 
    { 0, { (1<<MACH_BASE) } }
874 
  },
875 
/* lda ($abase), $dst */
876 
  {
877 
    I960_INSN_LDA_INDIRECT, "lda-indirect", "lda", 32,
878 
    { 0, { (1<<MACH_BASE) } }
879 
  },
880 
/* lda ($abase)[$index*S$scale], $dst */
881 
  {
882 
    I960_INSN_LDA_INDIRECT_INDEX, "lda-indirect-index", "lda", 32,
883 
    { 0, { (1<<MACH_BASE) } }
884 
  },
885 
/* lda $optdisp, $dst */
886 
  {
887 
    I960_INSN_LDA_DISP, "lda-disp", "lda", 64,
888 
    { 0, { (1<<MACH_BASE) } }
889 
  },
890 
/* lda $optdisp($abase), $dst */
891 
  {
892 
    I960_INSN_LDA_INDIRECT_DISP, "lda-indirect-disp", "lda", 64,
893 
    { 0, { (1<<MACH_BASE) } }
894 
  },
895 
/* lda $optdisp[$index*S$scale], $dst */
896 
  {
897 
    I960_INSN_LDA_INDEX_DISP, "lda-index-disp", "lda", 64,
898 
    { 0, { (1<<MACH_BASE) } }
899 
  },
900 
/* lda $optdisp($abase)[$index*S$scale], $dst */
901 
  {
902 
    I960_INSN_LDA_INDIRECT_INDEX_DISP, "lda-indirect-index-disp", "lda", 64,
903 
    { 0, { (1<<MACH_BASE) } }
904 
  },
905 
/* ld $offset, $dst */
906 
  {
907 
    I960_INSN_LD_OFFSET, "ld-offset", "ld", 32,
908 
    { 0, { (1<<MACH_BASE) } }
909 
  },
910 
/* ld $offset($abase), $dst */
911 
  {
912 
    I960_INSN_LD_INDIRECT_OFFSET, "ld-indirect-offset", "ld", 32,
913 
    { 0, { (1<<MACH_BASE) } }
914 
  },
915 
/* ld ($abase), $dst */
916 
  {
917 
    I960_INSN_LD_INDIRECT, "ld-indirect", "ld", 32,
918 
    { 0, { (1<<MACH_BASE) } }
919 
  },
920 
/* ld ($abase)[$index*S$scale], $dst */
921 
  {
922 
    I960_INSN_LD_INDIRECT_INDEX, "ld-indirect-index", "ld", 32,
923 
    { 0, { (1<<MACH_BASE) } }
924 
  },
925 
/* ld $optdisp, $dst */
926 
  {
927 
    I960_INSN_LD_DISP, "ld-disp", "ld", 64,
928 
    { 0, { (1<<MACH_BASE) } }
929 
  },
930 
/* ld $optdisp($abase), $dst */
931 
  {
932 
    I960_INSN_LD_INDIRECT_DISP, "ld-indirect-disp", "ld", 64,
933 
    { 0, { (1<<MACH_BASE) } }
934 
  },
935 
/* ld $optdisp[$index*S$scale], $dst */
936 
  {
937 
    I960_INSN_LD_INDEX_DISP, "ld-index-disp", "ld", 64,
938 
    { 0, { (1<<MACH_BASE) } }
939 
  },
940 
/* ld $optdisp($abase)[$index*S$scale], $dst */
941 
  {
942 
    I960_INSN_LD_INDIRECT_INDEX_DISP, "ld-indirect-index-disp", "ld", 64,
943 
    { 0, { (1<<MACH_BASE) } }
944 
  },
945 
/* ldob $offset, $dst */
946 
  {
947 
    I960_INSN_LDOB_OFFSET, "ldob-offset", "ldob", 32,
948 
    { 0, { (1<<MACH_BASE) } }
949 
  },
950 
/* ldob $offset($abase), $dst */
951 
  {
952 
    I960_INSN_LDOB_INDIRECT_OFFSET, "ldob-indirect-offset", "ldob", 32,
953 
    { 0, { (1<<MACH_BASE) } }
954 
  },
955 
/* ldob ($abase), $dst */
956 
  {
957 
    I960_INSN_LDOB_INDIRECT, "ldob-indirect", "ldob", 32,
958 
    { 0, { (1<<MACH_BASE) } }
959 
  },
960 
/* ldob ($abase)[$index*S$scale], $dst */
961 
  {
962 
    I960_INSN_LDOB_INDIRECT_INDEX, "ldob-indirect-index", "ldob", 32,
963 
    { 0, { (1<<MACH_BASE) } }
964 
  },
965 
/* ldob $optdisp, $dst */
966 
  {
967 
    I960_INSN_LDOB_DISP, "ldob-disp", "ldob", 64,
968 
    { 0, { (1<<MACH_BASE) } }
969 
  },
970 
/* ldob $optdisp($abase), $dst */
971 
  {
972 
    I960_INSN_LDOB_INDIRECT_DISP, "ldob-indirect-disp", "ldob", 64,
973 
    { 0, { (1<<MACH_BASE) } }
974 
  },
975 
/* ldob $optdisp[$index*S$scale], $dst */
976 
  {
977 
    I960_INSN_LDOB_INDEX_DISP, "ldob-index-disp", "ldob", 64,
978 
    { 0, { (1<<MACH_BASE) } }
979 
  },
980 
/* ldob $optdisp($abase)[$index*S$scale], $dst */
981 
  {
982 
    I960_INSN_LDOB_INDIRECT_INDEX_DISP, "ldob-indirect-index-disp", "ldob", 64,
983 
    { 0, { (1<<MACH_BASE) } }
984 
  },
985 
/* ldos $offset, $dst */
986 
  {
987 
    I960_INSN_LDOS_OFFSET, "ldos-offset", "ldos", 32,
988 
    { 0, { (1<<MACH_BASE) } }
989 
  },
990 
/* ldos $offset($abase), $dst */
991 
  {
992 
    I960_INSN_LDOS_INDIRECT_OFFSET, "ldos-indirect-offset", "ldos", 32,
993 
    { 0, { (1<<MACH_BASE) } }
994 
  },
995 
/* ldos ($abase), $dst */
996 
  {
997 
    I960_INSN_LDOS_INDIRECT, "ldos-indirect", "ldos", 32,
998 
    { 0, { (1<<MACH_BASE) } }
999 
  },
1000 
/* ldos ($abase)[$index*S$scale], $dst */
1001 
  {
1002 
    I960_INSN_LDOS_INDIRECT_INDEX, "ldos-indirect-index", "ldos", 32,
1003 
    { 0, { (1<<MACH_BASE) } }
1004 
  },
1005 
/* ldos $optdisp, $dst */
1006 
  {
1007 
    I960_INSN_LDOS_DISP, "ldos-disp", "ldos", 64,
1008 
    { 0, { (1<<MACH_BASE) } }
1009 
  },
1010 
/* ldos $optdisp($abase), $dst */
1011 
  {
1012 
    I960_INSN_LDOS_INDIRECT_DISP, "ldos-indirect-disp", "ldos", 64,
1013 
    { 0, { (1<<MACH_BASE) } }
1014 
  },
1015 
/* ldos $optdisp[$index*S$scale], $dst */
1016 
  {
1017 
    I960_INSN_LDOS_INDEX_DISP, "ldos-index-disp", "ldos", 64,
1018 
    { 0, { (1<<MACH_BASE) } }
1019 
  },
1020 
/* ldos $optdisp($abase)[$index*S$scale], $dst */
1021 
  {
1022 
    I960_INSN_LDOS_INDIRECT_INDEX_DISP, "ldos-indirect-index-disp", "ldos", 64,
1023 
    { 0, { (1<<MACH_BASE) } }
1024 
  },
1025 
/* ldib $offset, $dst */
1026 
  {
1027 
    I960_INSN_LDIB_OFFSET, "ldib-offset", "ldib", 32,
1028 
    { 0, { (1<<MACH_BASE) } }
1029 
  },
1030 
/* ldib $offset($abase), $dst */
1031 
  {
1032 
    I960_INSN_LDIB_INDIRECT_OFFSET, "ldib-indirect-offset", "ldib", 32,
1033 
    { 0, { (1<<MACH_BASE) } }
1034 
  },
1035 
/* ldib ($abase), $dst */
1036 
  {
1037 
    I960_INSN_LDIB_INDIRECT, "ldib-indirect", "ldib", 32,
1038 
    { 0, { (1<<MACH_BASE) } }
1039 
  },
1040 
/* ldib ($abase)[$index*S$scale], $dst */
1041 
  {
1042 
    I960_INSN_LDIB_INDIRECT_INDEX, "ldib-indirect-index", "ldib", 32,
1043 
    { 0, { (1<<MACH_BASE) } }
1044 
  },
1045 
/* ldib $optdisp, $dst */
1046 
  {
1047 
    I960_INSN_LDIB_DISP, "ldib-disp", "ldib", 64,
1048 
    { 0, { (1<<MACH_BASE) } }
1049 
  },
1050 
/* ldib $optdisp($abase), $dst */
1051 
  {
1052 
    I960_INSN_LDIB_INDIRECT_DISP, "ldib-indirect-disp", "ldib", 64,
1053 
    { 0, { (1<<MACH_BASE) } }
1054 
  },
1055 
/* ldib $optdisp[$index*S$scale], $dst */
1056 
  {
1057 
    I960_INSN_LDIB_INDEX_DISP, "ldib-index-disp", "ldib", 64,
1058 
    { 0, { (1<<MACH_BASE) } }
1059 
  },
1060 
/* ldib $optdisp($abase)[$index*S$scale], $dst */
1061 
  {
1062 
    I960_INSN_LDIB_INDIRECT_INDEX_DISP, "ldib-indirect-index-disp", "ldib", 64,
1063 
    { 0, { (1<<MACH_BASE) } }
1064 
  },
1065 
/* ldis $offset, $dst */
1066 
  {
1067 
    I960_INSN_LDIS_OFFSET, "ldis-offset", "ldis", 32,
1068 
    { 0, { (1<<MACH_BASE) } }
1069 
  },
1070 
/* ldis $offset($abase), $dst */
1071 
  {
1072 
    I960_INSN_LDIS_INDIRECT_OFFSET, "ldis-indirect-offset", "ldis", 32,
1073 
    { 0, { (1<<MACH_BASE) } }
1074 
  },
1075 
/* ldis ($abase), $dst */
1076 
  {
1077 
    I960_INSN_LDIS_INDIRECT, "ldis-indirect", "ldis", 32,
1078 
    { 0, { (1<<MACH_BASE) } }
1079 
  },
1080 
/* ldis ($abase)[$index*S$scale], $dst */
1081 
  {
1082 
    I960_INSN_LDIS_INDIRECT_INDEX, "ldis-indirect-index", "ldis", 32,
1083 
    { 0, { (1<<MACH_BASE) } }
1084 
  },
1085 
/* ldis $optdisp, $dst */
1086 
  {
1087 
    I960_INSN_LDIS_DISP, "ldis-disp", "ldis", 64,
1088 
    { 0, { (1<<MACH_BASE) } }
1089 
  },
1090 
/* ldis $optdisp($abase), $dst */
1091 
  {
1092 
    I960_INSN_LDIS_INDIRECT_DISP, "ldis-indirect-disp", "ldis", 64,
1093 
    { 0, { (1<<MACH_BASE) } }
1094 
  },
1095 
/* ldis $optdisp[$index*S$scale], $dst */
1096 
  {
1097 
    I960_INSN_LDIS_INDEX_DISP, "ldis-index-disp", "ldis", 64,
1098 
    { 0, { (1<<MACH_BASE) } }
1099 
  },
1100 
/* ldis $optdisp($abase)[$index*S$scale], $dst */
1101 
  {
1102 
    I960_INSN_LDIS_INDIRECT_INDEX_DISP, "ldis-indirect-index-disp", "ldis", 64,
1103 
    { 0, { (1<<MACH_BASE) } }
1104 
  },
1105 
/* ldl $offset, $dst */
1106 
  {
1107 
    I960_INSN_LDL_OFFSET, "ldl-offset", "ldl", 32,
1108 
    { 0, { (1<<MACH_BASE) } }
1109 
  },
1110 
/* ldl $offset($abase), $dst */
1111 
  {
1112 
    I960_INSN_LDL_INDIRECT_OFFSET, "ldl-indirect-offset", "ldl", 32,
1113 
    { 0, { (1<<MACH_BASE) } }
1114 
  },
1115 
/* ldl ($abase), $dst */
1116 
  {
1117 
    I960_INSN_LDL_INDIRECT, "ldl-indirect", "ldl", 32,
1118 
    { 0, { (1<<MACH_BASE) } }
1119 
  },
1120 
/* ldl ($abase)[$index*S$scale], $dst */
1121 
  {
1122 
    I960_INSN_LDL_INDIRECT_INDEX, "ldl-indirect-index", "ldl", 32,
1123 
    { 0, { (1<<MACH_BASE) } }
1124 
  },
1125 
/* ldl $optdisp, $dst */
1126 
  {
1127 
    I960_INSN_LDL_DISP, "ldl-disp", "ldl", 64,
1128 
    { 0, { (1<<MACH_BASE) } }
1129 
  },
1130 
/* ldl $optdisp($abase), $dst */
1131 
  {
1132 
    I960_INSN_LDL_INDIRECT_DISP, "ldl-indirect-disp", "ldl", 64,
1133 
    { 0, { (1<<MACH_BASE) } }
1134 
  },
1135 
/* ldl $optdisp[$index*S$scale], $dst */
1136 
  {
1137 
    I960_INSN_LDL_INDEX_DISP, "ldl-index-disp", "ldl", 64,
1138 
    { 0, { (1<<MACH_BASE) } }
1139 
  },
1140 
/* ldl $optdisp($abase)[$index*S$scale], $dst */
1141 
  {
1142 
    I960_INSN_LDL_INDIRECT_INDEX_DISP, "ldl-indirect-index-disp", "ldl", 64,
1143 
    { 0, { (1<<MACH_BASE) } }
1144 
  },
1145 
/* ldt $offset, $dst */
1146 
  {
1147 
    I960_INSN_LDT_OFFSET, "ldt-offset", "ldt", 32,
1148 
    { 0, { (1<<MACH_BASE) } }
1149 
  },
1150 
/* ldt $offset($abase), $dst */
1151 
  {
1152 
    I960_INSN_LDT_INDIRECT_OFFSET, "ldt-indirect-offset", "ldt", 32,
1153 
    { 0, { (1<<MACH_BASE) } }
1154 
  },
1155 
/* ldt ($abase), $dst */
1156 
  {
1157 
    I960_INSN_LDT_INDIRECT, "ldt-indirect", "ldt", 32,
1158 
    { 0, { (1<<MACH_BASE) } }
1159 
  },
1160 
/* ldt ($abase)[$index*S$scale], $dst */
1161 
  {
1162 
    I960_INSN_LDT_INDIRECT_INDEX, "ldt-indirect-index", "ldt", 32,
1163 
    { 0, { (1<<MACH_BASE) } }
1164 
  },
1165 
/* ldt $optdisp, $dst */
1166 
  {
1167 
    I960_INSN_LDT_DISP, "ldt-disp", "ldt", 64,
1168 
    { 0, { (1<<MACH_BASE) } }
1169 
  },
1170 
/* ldt $optdisp($abase), $dst */
1171 
  {
1172 
    I960_INSN_LDT_INDIRECT_DISP, "ldt-indirect-disp", "ldt", 64,
1173 
    { 0, { (1<<MACH_BASE) } }
1174 
  },
1175 
/* ldt $optdisp[$index*S$scale], $dst */
1176 
  {
1177 
    I960_INSN_LDT_INDEX_DISP, "ldt-index-disp", "ldt", 64,
1178 
    { 0, { (1<<MACH_BASE) } }
1179 
  },
1180 
/* ldt $optdisp($abase)[$index*S$scale], $dst */
1181 
  {
1182 
    I960_INSN_LDT_INDIRECT_INDEX_DISP, "ldt-indirect-index-disp", "ldt", 64,
1183 
    { 0, { (1<<MACH_BASE) } }
1184 
  },
1185 
/* ldq $offset, $dst */
1186 
  {
1187 
    I960_INSN_LDQ_OFFSET, "ldq-offset", "ldq", 32,
1188 
    { 0, { (1<<MACH_BASE) } }
1189 
  },
1190 
/* ldq $offset($abase), $dst */
1191 
  {
1192 
    I960_INSN_LDQ_INDIRECT_OFFSET, "ldq-indirect-offset", "ldq", 32,
1193 
    { 0, { (1<<MACH_BASE) } }
1194 
  },
1195 
/* ldq ($abase), $dst */
1196 
  {
1197 
    I960_INSN_LDQ_INDIRECT, "ldq-indirect", "ldq", 32,
1198 
    { 0, { (1<<MACH_BASE) } }
1199 
  },
1200 
/* ldq ($abase)[$index*S$scale], $dst */
1201 
  {
1202 
    I960_INSN_LDQ_INDIRECT_INDEX, "ldq-indirect-index", "ldq", 32,
1203 
    { 0, { (1<<MACH_BASE) } }
1204 
  },
1205 
/* ldq $optdisp, $dst */
1206 
  {
1207 
    I960_INSN_LDQ_DISP, "ldq-disp", "ldq", 64,
1208 
    { 0, { (1<<MACH_BASE) } }
1209 
  },
1210 
/* ldq $optdisp($abase), $dst */
1211 
  {
1212 
    I960_INSN_LDQ_INDIRECT_DISP, "ldq-indirect-disp", "ldq", 64,
1213 
    { 0, { (1<<MACH_BASE) } }
1214 
  },
1215 
/* ldq $optdisp[$index*S$scale], $dst */
1216 
  {
1217 
    I960_INSN_LDQ_INDEX_DISP, "ldq-index-disp", "ldq", 64,
1218 
    { 0, { (1<<MACH_BASE) } }
1219 
  },
1220 
/* ldq $optdisp($abase)[$index*S$scale], $dst */
1221 
  {
1222 
    I960_INSN_LDQ_INDIRECT_INDEX_DISP, "ldq-indirect-index-disp", "ldq", 64,
1223 
    { 0, { (1<<MACH_BASE) } }
1224 
  },
1225 
/* st $st_src, $offset */
1226 
  {
1227 
    I960_INSN_ST_OFFSET, "st-offset", "st", 32,
1228 
    { 0, { (1<<MACH_BASE) } }
1229 
  },
1230 
/* st $st_src, $offset($abase) */
1231 
  {
1232 
    I960_INSN_ST_INDIRECT_OFFSET, "st-indirect-offset", "st", 32,
1233 
    { 0, { (1<<MACH_BASE) } }
1234 
  },
1235 
/* st $st_src, ($abase) */
1236 
  {
1237 
    I960_INSN_ST_INDIRECT, "st-indirect", "st", 32,
1238 
    { 0, { (1<<MACH_BASE) } }
1239 
  },
1240 
/* st $st_src, ($abase)[$index*S$scale] */
1241 
  {
1242 
    I960_INSN_ST_INDIRECT_INDEX, "st-indirect-index", "st", 32,
1243 
    { 0, { (1<<MACH_BASE) } }
1244 
  },
1245 
/* st $st_src, $optdisp */
1246 
  {
1247 
    I960_INSN_ST_DISP, "st-disp", "st", 64,
1248 
    { 0, { (1<<MACH_BASE) } }
1249 
  },
1250 
/* st $st_src, $optdisp($abase) */
1251 
  {
1252 
    I960_INSN_ST_INDIRECT_DISP, "st-indirect-disp", "st", 64,
1253 
    { 0, { (1<<MACH_BASE) } }
1254 
  },
1255 
/* st $st_src, $optdisp[$index*S$scale */
1256 
  {
1257 
    I960_INSN_ST_INDEX_DISP, "st-index-disp", "st", 64,
1258 
    { 0, { (1<<MACH_BASE) } }
1259 
  },
1260 
/* st $st_src, $optdisp($abase)[$index*S$scale] */
1261 
  {
1262 
    I960_INSN_ST_INDIRECT_INDEX_DISP, "st-indirect-index-disp", "st", 64,
1263 
    { 0, { (1<<MACH_BASE) } }
1264 
  },
1265 
/* stob $st_src, $offset */
1266 
  {
1267 
    I960_INSN_STOB_OFFSET, "stob-offset", "stob", 32,
1268 
    { 0, { (1<<MACH_BASE) } }
1269 
  },
1270 
/* stob $st_src, $offset($abase) */
1271 
  {
1272 
    I960_INSN_STOB_INDIRECT_OFFSET, "stob-indirect-offset", "stob", 32,
1273 
    { 0, { (1<<MACH_BASE) } }
1274 
  },
1275 
/* stob $st_src, ($abase) */
1276 
  {
1277 
    I960_INSN_STOB_INDIRECT, "stob-indirect", "stob", 32,
1278 
    { 0, { (1<<MACH_BASE) } }
1279 
  },
1280 
/* stob $st_src, ($abase)[$index*S$scale] */
1281 
  {
1282 
    I960_INSN_STOB_INDIRECT_INDEX, "stob-indirect-index", "stob", 32,
1283 
    { 0, { (1<<MACH_BASE) } }
1284 
  },
1285 
/* stob $st_src, $optdisp */
1286 
  {
1287 
    I960_INSN_STOB_DISP, "stob-disp", "stob", 64,
1288 
    { 0, { (1<<MACH_BASE) } }
1289 
  },
1290 
/* stob $st_src, $optdisp($abase) */
1291 
  {
1292 
    I960_INSN_STOB_INDIRECT_DISP, "stob-indirect-disp", "stob", 64,
1293 
    { 0, { (1<<MACH_BASE) } }
1294 
  },
1295 
/* stob $st_src, $optdisp[$index*S$scale */
1296 
  {
1297 
    I960_INSN_STOB_INDEX_DISP, "stob-index-disp", "stob", 64,
1298 
    { 0, { (1<<MACH_BASE) } }
1299 
  },
1300 
/* stob $st_src, $optdisp($abase)[$index*S$scale] */
1301 
  {
1302 
    I960_INSN_STOB_INDIRECT_INDEX_DISP, "stob-indirect-index-disp", "stob", 64,
1303 
    { 0, { (1<<MACH_BASE) } }
1304 
  },
1305 
/* stos $st_src, $offset */
1306 
  {
1307 
    I960_INSN_STOS_OFFSET, "stos-offset", "stos", 32,
1308 
    { 0, { (1<<MACH_BASE) } }
1309 
  },
1310 
/* stos $st_src, $offset($abase) */
1311 
  {
1312 
    I960_INSN_STOS_INDIRECT_OFFSET, "stos-indirect-offset", "stos", 32,
1313 
    { 0, { (1<<MACH_BASE) } }
1314 
  },
1315 
/* stos $st_src, ($abase) */
1316 
  {
1317 
    I960_INSN_STOS_INDIRECT, "stos-indirect", "stos", 32,
1318 
    { 0, { (1<<MACH_BASE) } }
1319 
  },
1320 
/* stos $st_src, ($abase)[$index*S$scale] */
1321 
  {
1322 
    I960_INSN_STOS_INDIRECT_INDEX, "stos-indirect-index", "stos", 32,
1323 
    { 0, { (1<<MACH_BASE) } }
1324 
  },
1325 
/* stos $st_src, $optdisp */
1326 
  {
1327 
    I960_INSN_STOS_DISP, "stos-disp", "stos", 64,
1328 
    { 0, { (1<<MACH_BASE) } }
1329 
  },
1330 
/* stos $st_src, $optdisp($abase) */
1331 
  {
1332 
    I960_INSN_STOS_INDIRECT_DISP, "stos-indirect-disp", "stos", 64,
1333 
    { 0, { (1<<MACH_BASE) } }
1334 
  },
1335 
/* stos $st_src, $optdisp[$index*S$scale */
1336 
  {
1337 
    I960_INSN_STOS_INDEX_DISP, "stos-index-disp", "stos", 64,
1338 
    { 0, { (1<<MACH_BASE) } }
1339 
  },
1340 
/* stos $st_src, $optdisp($abase)[$index*S$scale] */
1341 
  {
1342 
    I960_INSN_STOS_INDIRECT_INDEX_DISP, "stos-indirect-index-disp", "stos", 64,
1343 
    { 0, { (1<<MACH_BASE) } }
1344 
  },
1345 
/* stl $st_src, $offset */
1346 
  {
1347 
    I960_INSN_STL_OFFSET, "stl-offset", "stl", 32,
1348 
    { 0, { (1<<MACH_BASE) } }
1349 
  },
1350 
/* stl $st_src, $offset($abase) */
1351 
  {
1352 
    I960_INSN_STL_INDIRECT_OFFSET, "stl-indirect-offset", "stl", 32,
1353 
    { 0, { (1<<MACH_BASE) } }
1354 
  },
1355 
/* stl $st_src, ($abase) */
1356 
  {
1357 
    I960_INSN_STL_INDIRECT, "stl-indirect", "stl", 32,
1358 
    { 0, { (1<<MACH_BASE) } }
1359 
  },
1360 
/* stl $st_src, ($abase)[$index*S$scale] */
1361 
  {
1362 
    I960_INSN_STL_INDIRECT_INDEX, "stl-indirect-index", "stl", 32,
1363 
    { 0, { (1<<MACH_BASE) } }
1364 
  },
1365 
/* stl $st_src, $optdisp */
1366 
  {
1367 
    I960_INSN_STL_DISP, "stl-disp", "stl", 64,
1368 
    { 0, { (1<<MACH_BASE) } }
1369 
  },
1370 
/* stl $st_src, $optdisp($abase) */
1371 
  {
1372 
    I960_INSN_STL_INDIRECT_DISP, "stl-indirect-disp", "stl", 64,
1373 
    { 0, { (1<<MACH_BASE) } }
1374 
  },
1375 
/* stl $st_src, $optdisp[$index*S$scale */
1376 
  {
1377 
    I960_INSN_STL_INDEX_DISP, "stl-index-disp", "stl", 64,
1378 
    { 0, { (1<<MACH_BASE) } }
1379 
  },
1380 
/* stl $st_src, $optdisp($abase)[$index*S$scale] */
1381 
  {
1382 
    I960_INSN_STL_INDIRECT_INDEX_DISP, "stl-indirect-index-disp", "stl", 64,
1383 
    { 0, { (1<<MACH_BASE) } }
1384 
  },
1385 
/* stt $st_src, $offset */
1386 
  {
1387 
    I960_INSN_STT_OFFSET, "stt-offset", "stt", 32,
1388 
    { 0, { (1<<MACH_BASE) } }
1389 
  },
1390 
/* stt $st_src, $offset($abase) */
1391 
  {
1392 
    I960_INSN_STT_INDIRECT_OFFSET, "stt-indirect-offset", "stt", 32,
1393 
    { 0, { (1<<MACH_BASE) } }
1394 
  },
1395 
/* stt $st_src, ($abase) */
1396 
  {
1397 
    I960_INSN_STT_INDIRECT, "stt-indirect", "stt", 32,
1398 
    { 0, { (1<<MACH_BASE) } }
1399 
  },
1400 
/* stt $st_src, ($abase)[$index*S$scale] */
1401 
  {
1402 
    I960_INSN_STT_INDIRECT_INDEX, "stt-indirect-index", "stt", 32,
1403 
    { 0, { (1<<MACH_BASE) } }
1404 
  },
1405 
/* stt $st_src, $optdisp */
1406 
  {
1407 
    I960_INSN_STT_DISP, "stt-disp", "stt", 64,
1408 
    { 0, { (1<<MACH_BASE) } }
1409 
  },
1410 
/* stt $st_src, $optdisp($abase) */
1411 
  {
1412 
    I960_INSN_STT_INDIRECT_DISP, "stt-indirect-disp", "stt", 64,
1413 
    { 0, { (1<<MACH_BASE) } }
1414 
  },
1415 
/* stt $st_src, $optdisp[$index*S$scale */
1416 
  {
1417 
    I960_INSN_STT_INDEX_DISP, "stt-index-disp", "stt", 64,
1418 
    { 0, { (1<<MACH_BASE) } }
1419 
  },
1420 
/* stt $st_src, $optdisp($abase)[$index*S$scale] */
1421 
  {
1422 
    I960_INSN_STT_INDIRECT_INDEX_DISP, "stt-indirect-index-disp", "stt", 64,
1423 
    { 0, { (1<<MACH_BASE) } }
1424 
  },
1425 
/* stq $st_src, $offset */
1426 
  {
1427 
    I960_INSN_STQ_OFFSET, "stq-offset", "stq", 32,
1428 
    { 0, { (1<<MACH_BASE) } }
1429 
  },
1430 
/* stq $st_src, $offset($abase) */
1431 
  {
1432 
    I960_INSN_STQ_INDIRECT_OFFSET, "stq-indirect-offset", "stq", 32,
1433 
    { 0, { (1<<MACH_BASE) } }
1434 
  },
1435 
/* stq $st_src, ($abase) */
1436 
  {
1437 
    I960_INSN_STQ_INDIRECT, "stq-indirect", "stq", 32,
1438 
    { 0, { (1<<MACH_BASE) } }
1439 
  },
1440 
/* stq $st_src, ($abase)[$index*S$scale] */
1441 
  {
1442 
    I960_INSN_STQ_INDIRECT_INDEX, "stq-indirect-index", "stq", 32,
1443 
    { 0, { (1<<MACH_BASE) } }
1444 
  },
1445 
/* stq $st_src, $optdisp */
1446 
  {
1447 
    I960_INSN_STQ_DISP, "stq-disp", "stq", 64,
1448 
    { 0, { (1<<MACH_BASE) } }
1449 
  },
1450 
/* stq $st_src, $optdisp($abase) */
1451 
  {
1452 
    I960_INSN_STQ_INDIRECT_DISP, "stq-indirect-disp", "stq", 64,
1453 
    { 0, { (1<<MACH_BASE) } }
1454 
  },
1455 
/* stq $st_src, $optdisp[$index*S$scale */
1456 
  {
1457 
    I960_INSN_STQ_INDEX_DISP, "stq-index-disp", "stq", 64,
1458 
    { 0, { (1<<MACH_BASE) } }
1459 
  },
1460 
/* stq $st_src, $optdisp($abase)[$index*S$scale] */
1461 
  {
1462 
    I960_INSN_STQ_INDIRECT_INDEX_DISP, "stq-indirect-index-disp", "stq", 64,
1463 
    { 0, { (1<<MACH_BASE) } }
1464 
  },
1465 
/* cmpobe $br_src1, $br_src2, $br_disp */
1466 
  {
1467 
    I960_INSN_CMPOBE_REG, "cmpobe-reg", "cmpobe", 32,
1468 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1469 
  },
1470 
/* cmpobe $br_lit1, $br_src2, $br_disp */
1471 
  {
1472 
    I960_INSN_CMPOBE_LIT, "cmpobe-lit", "cmpobe", 32,
1473 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1474 
  },
1475 
/* cmpobne $br_src1, $br_src2, $br_disp */
1476 
  {
1477 
    I960_INSN_CMPOBNE_REG, "cmpobne-reg", "cmpobne", 32,
1478 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1479 
  },
1480 
/* cmpobne $br_lit1, $br_src2, $br_disp */
1481 
  {
1482 
    I960_INSN_CMPOBNE_LIT, "cmpobne-lit", "cmpobne", 32,
1483 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1484 
  },
1485 
/* cmpobl $br_src1, $br_src2, $br_disp */
1486 
  {
1487 
    I960_INSN_CMPOBL_REG, "cmpobl-reg", "cmpobl", 32,
1488 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1489 
  },
1490 
/* cmpobl $br_lit1, $br_src2, $br_disp */
1491 
  {
1492 
    I960_INSN_CMPOBL_LIT, "cmpobl-lit", "cmpobl", 32,
1493 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1494 
  },
1495 
/* cmpoble $br_src1, $br_src2, $br_disp */
1496 
  {
1497 
    I960_INSN_CMPOBLE_REG, "cmpoble-reg", "cmpoble", 32,
1498 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1499 
  },
1500 
/* cmpoble $br_lit1, $br_src2, $br_disp */
1501 
  {
1502 
    I960_INSN_CMPOBLE_LIT, "cmpoble-lit", "cmpoble", 32,
1503 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1504 
  },
1505 
/* cmpobg $br_src1, $br_src2, $br_disp */
1506 
  {
1507 
    I960_INSN_CMPOBG_REG, "cmpobg-reg", "cmpobg", 32,
1508 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1509 
  },
1510 
/* cmpobg $br_lit1, $br_src2, $br_disp */
1511 
  {
1512 
    I960_INSN_CMPOBG_LIT, "cmpobg-lit", "cmpobg", 32,
1513 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1514 
  },
1515 
/* cmpobge $br_src1, $br_src2, $br_disp */
1516 
  {
1517 
    I960_INSN_CMPOBGE_REG, "cmpobge-reg", "cmpobge", 32,
1518 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1519 
  },
1520 
/* cmpobge $br_lit1, $br_src2, $br_disp */
1521 
  {
1522 
    I960_INSN_CMPOBGE_LIT, "cmpobge-lit", "cmpobge", 32,
1523 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1524 
  },
1525 
/* cmpibe $br_src1, $br_src2, $br_disp */
1526 
  {
1527 
    I960_INSN_CMPIBE_REG, "cmpibe-reg", "cmpibe", 32,
1528 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1529 
  },
1530 
/* cmpibe $br_lit1, $br_src2, $br_disp */
1531 
  {
1532 
    I960_INSN_CMPIBE_LIT, "cmpibe-lit", "cmpibe", 32,
1533 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1534 
  },
1535 
/* cmpibne $br_src1, $br_src2, $br_disp */
1536 
  {
1537 
    I960_INSN_CMPIBNE_REG, "cmpibne-reg", "cmpibne", 32,
1538 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1539 
  },
1540 
/* cmpibne $br_lit1, $br_src2, $br_disp */
1541 
  {
1542 
    I960_INSN_CMPIBNE_LIT, "cmpibne-lit", "cmpibne", 32,
1543 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1544 
  },
1545 
/* cmpibl $br_src1, $br_src2, $br_disp */
1546 
  {
1547 
    I960_INSN_CMPIBL_REG, "cmpibl-reg", "cmpibl", 32,
1548 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1549 
  },
1550 
/* cmpibl $br_lit1, $br_src2, $br_disp */
1551 
  {
1552 
    I960_INSN_CMPIBL_LIT, "cmpibl-lit", "cmpibl", 32,
1553 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1554 
  },
1555 
/* cmpible $br_src1, $br_src2, $br_disp */
1556 
  {
1557 
    I960_INSN_CMPIBLE_REG, "cmpible-reg", "cmpible", 32,
1558 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1559 
  },
1560 
/* cmpible $br_lit1, $br_src2, $br_disp */
1561 
  {
1562 
    I960_INSN_CMPIBLE_LIT, "cmpible-lit", "cmpible", 32,
1563 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1564 
  },
1565 
/* cmpibg $br_src1, $br_src2, $br_disp */
1566 
  {
1567 
    I960_INSN_CMPIBG_REG, "cmpibg-reg", "cmpibg", 32,
1568 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1569 
  },
1570 
/* cmpibg $br_lit1, $br_src2, $br_disp */
1571 
  {
1572 
    I960_INSN_CMPIBG_LIT, "cmpibg-lit", "cmpibg", 32,
1573 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1574 
  },
1575 
/* cmpibge $br_src1, $br_src2, $br_disp */
1576 
  {
1577 
    I960_INSN_CMPIBGE_REG, "cmpibge-reg", "cmpibge", 32,
1578 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1579 
  },
1580 
/* cmpibge $br_lit1, $br_src2, $br_disp */
1581 
  {
1582 
    I960_INSN_CMPIBGE_LIT, "cmpibge-lit", "cmpibge", 32,
1583 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1584 
  },
1585 
/* bbc $br_src1, $br_src2, $br_disp */
1586 
  {
1587 
    I960_INSN_BBC_REG, "bbc-reg", "bbc", 32,
1588 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1589 
  },
1590 
/* bbc $br_lit1, $br_src2, $br_disp */
1591 
  {
1592 
    I960_INSN_BBC_LIT, "bbc-lit", "bbc", 32,
1593 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1594 
  },
1595 
/* bbs $br_src1, $br_src2, $br_disp */
1596 
  {
1597 
    I960_INSN_BBS_REG, "bbs-reg", "bbs", 32,
1598 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1599 
  },
1600 
/* bbs $br_lit1, $br_src2, $br_disp */
1601 
  {
1602 
    I960_INSN_BBS_LIT, "bbs-lit", "bbs", 32,
1603 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1604 
  },
1605 
/* cmpi $src1, $src2 */
1606 
  {
1607 
    I960_INSN_CMPI, "cmpi", "cmpi", 32,
1608 
    { 0, { (1<<MACH_BASE) } }
1609 
  },
1610 
/* cmpi $lit1, $src2 */
1611 
  {
1612 
    I960_INSN_CMPI1, "cmpi1", "cmpi", 32,
1613 
    { 0, { (1<<MACH_BASE) } }
1614 
  },
1615 
/* cmpi $src1, $lit2 */
1616 
  {
1617 
    I960_INSN_CMPI2, "cmpi2", "cmpi", 32,
1618 
    { 0, { (1<<MACH_BASE) } }
1619 
  },
1620 
/* cmpi $lit1, $lit2 */
1621 
  {
1622 
    I960_INSN_CMPI3, "cmpi3", "cmpi", 32,
1623 
    { 0, { (1<<MACH_BASE) } }
1624 
  },
1625 
/* cmpo $src1, $src2 */
1626 
  {
1627 
    I960_INSN_CMPO, "cmpo", "cmpo", 32,
1628 
    { 0, { (1<<MACH_BASE) } }
1629 
  },
1630 
/* cmpo $lit1, $src2 */
1631 
  {
1632 
    I960_INSN_CMPO1, "cmpo1", "cmpo", 32,
1633 
    { 0, { (1<<MACH_BASE) } }
1634 
  },
1635 
/* cmpo $src1, $lit2 */
1636 
  {
1637 
    I960_INSN_CMPO2, "cmpo2", "cmpo", 32,
1638 
    { 0, { (1<<MACH_BASE) } }
1639 
  },
1640 
/* cmpo $lit1, $lit2 */
1641 
  {
1642 
    I960_INSN_CMPO3, "cmpo3", "cmpo", 32,
1643 
    { 0, { (1<<MACH_BASE) } }
1644 
  },
1645 
/* testno $br_src1 */
1646 
  {
1647 
    I960_INSN_TESTNO_REG, "testno-reg", "testno", 32,
1648 
    { 0, { (1<<MACH_BASE) } }
1649 
  },
1650 
/* testg $br_src1 */
1651 
  {
1652 
    I960_INSN_TESTG_REG, "testg-reg", "testg", 32,
1653 
    { 0, { (1<<MACH_BASE) } }
1654 
  },
1655 
/* teste $br_src1 */
1656 
  {
1657 
    I960_INSN_TESTE_REG, "teste-reg", "teste", 32,
1658 
    { 0, { (1<<MACH_BASE) } }
1659 
  },
1660 
/* testge $br_src1 */
1661 
  {
1662 
    I960_INSN_TESTGE_REG, "testge-reg", "testge", 32,
1663 
    { 0, { (1<<MACH_BASE) } }
1664 
  },
1665 
/* testl $br_src1 */
1666 
  {
1667 
    I960_INSN_TESTL_REG, "testl-reg", "testl", 32,
1668 
    { 0, { (1<<MACH_BASE) } }
1669 
  },
1670 
/* testne $br_src1 */
1671 
  {
1672 
    I960_INSN_TESTNE_REG, "testne-reg", "testne", 32,
1673 
    { 0, { (1<<MACH_BASE) } }
1674 
  },
1675 
/* testle $br_src1 */
1676 
  {
1677 
    I960_INSN_TESTLE_REG, "testle-reg", "testle", 32,
1678 
    { 0, { (1<<MACH_BASE) } }
1679 
  },
1680 
/* testo $br_src1 */
1681 
  {
1682 
    I960_INSN_TESTO_REG, "testo-reg", "testo", 32,
1683 
    { 0, { (1<<MACH_BASE) } }
1684 
  },
1685 
/* bno $ctrl_disp */
1686 
  {
1687 
    I960_INSN_BNO, "bno", "bno", 32,
1688 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1689 
  },
1690 
/* bg $ctrl_disp */
1691 
  {
1692 
    I960_INSN_BG, "bg", "bg", 32,
1693 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1694 
  },
1695 
/* be $ctrl_disp */
1696 
  {
1697 
    I960_INSN_BE, "be", "be", 32,
1698 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1699 
  },
1700 
/* bge $ctrl_disp */
1701 
  {
1702 
    I960_INSN_BGE, "bge", "bge", 32,
1703 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1704 
  },
1705 
/* bl $ctrl_disp */
1706 
  {
1707 
    I960_INSN_BL, "bl", "bl", 32,
1708 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1709 
  },
1710 
/* bne $ctrl_disp */
1711 
  {
1712 
    I960_INSN_BNE, "bne", "bne", 32,
1713 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1714 
  },
1715 
/* ble $ctrl_disp */
1716 
  {
1717 
    I960_INSN_BLE, "ble", "ble", 32,
1718 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1719 
  },
1720 
/* bo $ctrl_disp */
1721 
  {
1722 
    I960_INSN_BO, "bo", "bo", 32,
1723 
    { 0|A(COND_CTI), { (1<<MACH_BASE) } }
1724 
  },
1725 
/* b $ctrl_disp */
1726 
  {
1727 
    I960_INSN_B, "b", "b", 32,
1728 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1729 
  },
1730 
/* bx $offset($abase) */
1731 
  {
1732 
    I960_INSN_BX_INDIRECT_OFFSET, "bx-indirect-offset", "bx", 32,
1733 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1734 
  },
1735 
/* bx ($abase) */
1736 
  {
1737 
    I960_INSN_BX_INDIRECT, "bx-indirect", "bx", 32,
1738 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1739 
  },
1740 
/* bx ($abase)[$index*S$scale] */
1741 
  {
1742 
    I960_INSN_BX_INDIRECT_INDEX, "bx-indirect-index", "bx", 32,
1743 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1744 
  },
1745 
/* bx $optdisp */
1746 
  {
1747 
    I960_INSN_BX_DISP, "bx-disp", "bx", 64,
1748 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1749 
  },
1750 
/* bx $optdisp($abase) */
1751 
  {
1752 
    I960_INSN_BX_INDIRECT_DISP, "bx-indirect-disp", "bx", 64,
1753 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1754 
  },
1755 
/* callx $optdisp */
1756 
  {
1757 
    I960_INSN_CALLX_DISP, "callx-disp", "callx", 64,
1758 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1759 
  },
1760 
/* callx ($abase) */
1761 
  {
1762 
    I960_INSN_CALLX_INDIRECT, "callx-indirect", "callx", 32,
1763 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1764 
  },
1765 
/* callx $offset($abase) */
1766 
  {
1767 
    I960_INSN_CALLX_INDIRECT_OFFSET, "callx-indirect-offset", "callx", 32,
1768 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1769 
  },
1770 
/* ret */
1771 
  {
1772 
    I960_INSN_RET, "ret", "ret", 32,
1773 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1774 
  },
1775 
/* calls $src1 */
1776 
  {
1777 
    I960_INSN_CALLS, "calls", "calls", 32,
1778 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1779 
  },
1780 
/* fmark */
1781 
  {
1782 
    I960_INSN_FMARK, "fmark", "fmark", 32,
1783 
    { 0|A(UNCOND_CTI), { (1<<MACH_BASE) } }
1784 
  },
1785 
/* flushreg */
1786 
  {
1787 
    I960_INSN_FLUSHREG, "flushreg", "flushreg", 32,
1788 
    { 0, { (1<<MACH_BASE) } }
1789 
  },
1790 
};
1791 
 
1792 
#undef A
1793 
#undef MNEM
1794 
#undef OP
1795 
 
1796 
/* Initialize anything needed to be done once, before any cpu_open call.  */
1797 
 
1798 
static void
1799 
init_tables ()
1800 
{
1801 
}
1802 
 
1803 
/* Subroutine of i960_cgen_cpu_open to look up a mach via its bfd name.  */
1804 
 
1805 
static const CGEN_MACH *
1806 
lookup_mach_via_bfd_name (table, name)
1807 
     const CGEN_MACH *table;
1808 
     const char *name;
1809 
{
1810 
  while (table->name)
1811 
    {
1812 
      if (strcmp (name, table->bfd_name) == 0)
1813 
        return table;
1814 
      ++table;
1815 
    }
1816 
  abort ();
1817 
}
1818 
 
1819 
/* Subroutine of i960_cgen_cpu_open to build the hardware table.  */
1820 
 
1821 
static void
1822 
build_hw_table (cd)
1823 
     CGEN_CPU_TABLE *cd;
1824 
{
1825 
  int i;
1826 
  int machs = cd->machs;
1827 
  const CGEN_HW_ENTRY *init = & i960_cgen_hw_table[0];
1828 
  /* MAX_HW is only an upper bound on the number of selected entries.
1829 
     However each entry is indexed by it's enum so there can be holes in
1830 
     the table.  */
1831 
  const CGEN_HW_ENTRY **selected =
1832 
    (const CGEN_HW_ENTRY **) xmalloc (MAX_HW * sizeof (CGEN_HW_ENTRY *));
1833 
 
1834 
  cd->hw_table.init_entries = init;
1835 
  cd->hw_table.entry_size = sizeof (CGEN_HW_ENTRY);
1836 
  memset (selected, 0, MAX_HW * sizeof (CGEN_HW_ENTRY *));
1837 
  /* ??? For now we just use machs to determine which ones we want.  */
1838 
  for (i = 0; init[i].name != NULL; ++i)
1839 
    if (CGEN_HW_ATTR_VALUE (&init[i], CGEN_HW_MACH)
1840 
        & machs)
1841 
      selected[init[i].type] = &init[i];
1842 
  cd->hw_table.entries = selected;
1843 
  cd->hw_table.num_entries = MAX_HW;
1844 
}
1845 
 
1846 
/* Subroutine of i960_cgen_cpu_open to build the hardware table.  */
1847 
 
1848 
static void
1849 
build_ifield_table (cd)
1850 
     CGEN_CPU_TABLE *cd;
1851 
{
1852 
  cd->ifld_table = & i960_cgen_ifld_table[0];
1853 
}
1854 
 
1855 
/* Subroutine of i960_cgen_cpu_open to build the hardware table.  */
1856 
 
1857 
static void
1858 
build_operand_table (cd)
1859 
     CGEN_CPU_TABLE *cd;
1860 
{
1861 
  int i;
1862 
  int machs = cd->machs;
1863 
  const CGEN_OPERAND *init = & i960_cgen_operand_table[0];
1864 
  /* MAX_OPERANDS is only an upper bound on the number of selected entries.
1865 
     However each entry is indexed by it's enum so there can be holes in
1866 
     the table.  */
1867 
  const CGEN_OPERAND **selected =
1868 
    (const CGEN_OPERAND **) xmalloc (MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1869 
 
1870 
  cd->operand_table.init_entries = init;
1871 
  cd->operand_table.entry_size = sizeof (CGEN_OPERAND);
1872 
  memset (selected, 0, MAX_OPERANDS * sizeof (CGEN_OPERAND *));
1873 
  /* ??? For now we just use mach to determine which ones we want.  */
1874 
  for (i = 0; init[i].name != NULL; ++i)
1875 
    if (CGEN_OPERAND_ATTR_VALUE (&init[i], CGEN_OPERAND_MACH)
1876 
        & machs)
1877 
      selected[init[i].type] = &init[i];
1878 
  cd->operand_table.entries = selected;
1879 
  cd->operand_table.num_entries = MAX_OPERANDS;
1880 
}
1881 
 
1882 
/* Subroutine of i960_cgen_cpu_open to build the hardware table.
1883 
   ??? This could leave out insns not supported by the specified mach/isa,
1884 
   but that would cause errors like "foo only supported by bar" to become
1885 
   "unknown insn", so for now we include all insns and require the app to
1886 
   do the checking later.
1887 
   ??? On the other hand, parsing of such insns may require their hardware or
1888 
   operand elements to be in the table [which they mightn't be].  */
1889 
 
1890 
static void
1891 
build_insn_table (cd)
1892 
     CGEN_CPU_TABLE *cd;
1893 
{
1894 
  int i;
1895 
  const CGEN_IBASE *ib = & i960_cgen_insn_table[0];
1896 
  CGEN_INSN *insns = (CGEN_INSN *) xmalloc (MAX_INSNS * sizeof (CGEN_INSN));
1897 
 
1898 
  memset (insns, 0, MAX_INSNS * sizeof (CGEN_INSN));
1899 
  for (i = 0; i < MAX_INSNS; ++i)
1900 
    insns[i].base = &ib[i];
1901 
  cd->insn_table.init_entries = insns;
1902 
  cd->insn_table.entry_size = sizeof (CGEN_IBASE);
1903 
  cd->insn_table.num_init_entries = MAX_INSNS;
1904 
}
1905 
 
1906 
/* Subroutine of i960_cgen_cpu_open to rebuild the tables.  */
1907 
 
1908 
static void
1909 
i960_cgen_rebuild_tables (cd)
1910 
     CGEN_CPU_TABLE *cd;
1911 
{
1912 
  int i,n_isas,n_machs;
1913 
  unsigned int isas = cd->isas;
1914 
  unsigned int machs = cd->machs;
1915 
 
1916 
  cd->int_insn_p = CGEN_INT_INSN_P;
1917 
 
1918 
  /* Data derived from the isa spec.  */
1919 
#define UNSET (CGEN_SIZE_UNKNOWN + 1)
1920 
  cd->default_insn_bitsize = UNSET;
1921 
  cd->base_insn_bitsize = UNSET;
1922 
  cd->min_insn_bitsize = 65535; /* some ridiculously big number */
1923 
  cd->max_insn_bitsize = 0;
1924 
  for (i = 0; i < MAX_ISAS; ++i)
1925 
    if (((1 << i) & isas) != 0)
1926 
      {
1927 
        const CGEN_ISA *isa = & i960_cgen_isa_table[i];
1928 
 
1929 
        /* Default insn sizes of all selected isas must be equal or we set
1930 
           the result to 0, meaning "unknown".  */
1931 
        if (cd->default_insn_bitsize == UNSET)
1932 
          cd->default_insn_bitsize = isa->default_insn_bitsize;
1933 
        else if (isa->default_insn_bitsize == cd->default_insn_bitsize)
1934 
          ; /* this is ok */
1935 
        else
1936 
          cd->default_insn_bitsize = CGEN_SIZE_UNKNOWN;
1937 
 
1938 
        /* Base insn sizes of all selected isas must be equal or we set
1939 
           the result to 0, meaning "unknown".  */
1940 
        if (cd->base_insn_bitsize == UNSET)
1941 
          cd->base_insn_bitsize = isa->base_insn_bitsize;
1942 
        else if (isa->base_insn_bitsize == cd->base_insn_bitsize)
1943 
          ; /* this is ok */
1944 
        else
1945 
          cd->base_insn_bitsize = CGEN_SIZE_UNKNOWN;
1946 
 
1947 
        /* Set min,max insn sizes.  */
1948 
        if (isa->min_insn_bitsize < cd->min_insn_bitsize)
1949 
          cd->min_insn_bitsize = isa->min_insn_bitsize;
1950 
        if (isa->max_insn_bitsize > cd->max_insn_bitsize)
1951 
          cd->max_insn_bitsize = isa->max_insn_bitsize;
1952 
 
1953 
        ++n_isas;
1954 
      }
1955 
 
1956 
  /* Data derived from the mach spec.  */
1957 
  for (i = 0; i < MAX_MACHS; ++i)
1958 
    if (((1 << i) & machs) != 0)
1959 
      {
1960 
        const CGEN_MACH *mach = & i960_cgen_mach_table[i];
1961 
 
1962 
        ++n_machs;
1963 
      }
1964 
 
1965 
  /* Determine which hw elements are used by MACH.  */
1966 
  build_hw_table (cd);
1967 
 
1968 
  /* Build the ifield table.  */
1969 
  build_ifield_table (cd);
1970 
 
1971 
  /* Determine which operands are used by MACH/ISA.  */
1972 
  build_operand_table (cd);
1973 
 
1974 
  /* Build the instruction table.  */
1975 
  build_insn_table (cd);
1976 
}
1977 
 
1978 
/* Initialize a cpu table and return a descriptor.
1979 
   It's much like opening a file, and must be the first function called.
1980 
   The arguments are a set of (type/value) pairs, terminated with
1981 
   CGEN_CPU_OPEN_END.
1982 
 
1983 
   Currently supported values:
1984 
   CGEN_CPU_OPEN_ISAS:    bitmap of values in enum isa_attr
1985 
   CGEN_CPU_OPEN_MACHS:   bitmap of values in enum mach_attr
1986 
   CGEN_CPU_OPEN_BFDMACH: specify 1 mach using bfd name
1987 
   CGEN_CPU_OPEN_ENDIAN:  specify endian choice
1988 
   CGEN_CPU_OPEN_END:     terminates arguments
1989 
 
1990 
   ??? Simultaneous multiple isas might not make sense, but it's not (yet)
1991 
   precluded.
1992 
 
1993 
   ??? We only support ISO C stdargs here, not K&R.
1994 
   Laziness, plus experiment to see if anything requires K&R - eventually
1995 
   K&R will no longer be supported - e.g. GDB is currently trying this.  */
1996 
 
1997 
CGEN_CPU_DESC
1998 
i960_cgen_cpu_open (enum cgen_cpu_open_arg arg_type, ...)
1999 
{
2000 
  CGEN_CPU_TABLE *cd = (CGEN_CPU_TABLE *) xmalloc (sizeof (CGEN_CPU_TABLE));
2001 
  static int init_p;
2002 
  unsigned int isas = 0;  /* 0 = "unspecified" */
2003 
  unsigned int machs = 0; /* 0 = "unspecified" */
2004 
  enum cgen_endian endian = CGEN_ENDIAN_UNKNOWN;
2005 
  va_list ap;
2006 
 
2007 
  if (! init_p)
2008 
    {
2009 
      init_tables ();
2010 
      init_p = 1;
2011 
    }
2012 
 
2013 
  memset (cd, 0, sizeof (*cd));
2014 
 
2015 
  va_start (ap, arg_type);
2016 
  while (arg_type != CGEN_CPU_OPEN_END)
2017 
    {
2018 
      switch (arg_type)
2019 
        {
2020 
        case CGEN_CPU_OPEN_ISAS :
2021 
          isas = va_arg (ap, unsigned int);
2022 
          break;
2023 
        case CGEN_CPU_OPEN_MACHS :
2024 
          machs = va_arg (ap, unsigned int);
2025 
          break;
2026 
        case CGEN_CPU_OPEN_BFDMACH :
2027 
          {
2028 
            const char *name = va_arg (ap, const char *);
2029 
            const CGEN_MACH *mach =
2030 
              lookup_mach_via_bfd_name (i960_cgen_mach_table, name);
2031 
 
2032 
            machs |= mach->num << 1;
2033 
            break;
2034 
          }
2035 
        case CGEN_CPU_OPEN_ENDIAN :
2036 
          endian = va_arg (ap, enum cgen_endian);
2037 
          break;
2038 
        default :
2039 
          fprintf (stderr, "i960_cgen_cpu_open: unsupported argument `%d'\n",
2040 
                   arg_type);
2041 
          abort (); /* ??? return NULL? */
2042 
        }
2043 
      arg_type = va_arg (ap, enum cgen_cpu_open_arg);
2044 
    }
2045 
  va_end (ap);
2046 
 
2047 
  /* mach unspecified means "all" */
2048 
  if (machs == 0)
2049 
    machs = (1 << MAX_MACHS) - 1;
2050 
  /* base mach is always selected */
2051 
  machs |= 1;
2052 
  /* isa unspecified means "all" */
2053 
  if (isas == 0)
2054 
    isas = (1 << MAX_ISAS) - 1;
2055 
  if (endian == CGEN_ENDIAN_UNKNOWN)
2056 
    {
2057 
      /* ??? If target has only one, could have a default.  */
2058 
      fprintf (stderr, "i960_cgen_cpu_open: no endianness specified\n");
2059 
      abort ();
2060 
    }
2061 
 
2062 
  cd->isas = isas;
2063 
  cd->machs = machs;
2064 
  cd->endian = endian;
2065 
  /* FIXME: for the sparc case we can determine insn-endianness statically.
2066 
     The worry here is where both data and insn endian can be independently
2067 
     chosen, in which case this function will need another argument.
2068 
     Actually, will want to allow for more arguments in the future anyway.  */
2069 
  cd->insn_endian = endian;
2070 
 
2071 
  /* Table (re)builder.  */
2072 
  cd->rebuild_tables = i960_cgen_rebuild_tables;
2073 
  i960_cgen_rebuild_tables (cd);
2074 
 
2075 
  return (CGEN_CPU_DESC) cd;
2076 
}
2077 
 
2078 
/* Cover fn to i960_cgen_cpu_open to handle the simple case of 1 isa, 1 mach.
2079 
   MACH_NAME is the bfd name of the mach.  */
2080 
 
2081 
CGEN_CPU_DESC
2082 
i960_cgen_cpu_open_1 (mach_name, endian)
2083 
     const char *mach_name;
2084 
     enum cgen_endian endian;
2085 
{
2086 
  return i960_cgen_cpu_open (CGEN_CPU_OPEN_BFDMACH, mach_name,
2087 
                               CGEN_CPU_OPEN_ENDIAN, endian,
2088 
                               CGEN_CPU_OPEN_END);
2089 
}
2090 
 
2091 
/* Close a cpu table.
2092 
   ??? This can live in a machine independent file, but there's currently
2093 
   no place to put this file (there's no libcgen).  libopcodes is the wrong
2094 
   place as some simulator ports use this but they don't use libopcodes.  */
2095 
 
2096 
void
2097 
i960_cgen_cpu_close (cd)
2098 
     CGEN_CPU_DESC cd;
2099 
{
2100 
  if (cd->insn_table.init_entries)
2101 
    free ((CGEN_INSN *) cd->insn_table.init_entries);
2102 
  if (cd->hw_table.entries)
2103 
    free ((CGEN_HW_ENTRY *) cd->hw_table.entries);
2104 
  free (cd);
2105 
}
2106 
 

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.