OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [insight/] [sim/] [ppc/] [ppc-cache-rules] - Blame information for rev 1774

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 markom
#
2
#   This file is part of the program psim.
3
#
4
#   Copyright (C) 1994-1995, Andrew Cagney 
5
#
6
#   This program is free software; you can redistribute it and/or modify
7
#   it under the terms of the GNU General Public License as published by
8
#   the Free Software Foundation; either version 2 of the License, or
9
#   (at your option) any later version.
10
#
11
#   This program is distributed in the hope that it will be useful,
12
#   but WITHOUT ANY WARRANTY; without even the implied warranty of
13
#   MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
14
#   GNU General Public License for more details.
15
#
16
#   You should have received a copy of the GNU General Public License
17
#   along with this program; if not, write to the Free Software
18
#   Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
19
#
20
cache:RA:RA::
21
cache:RA:rA:signed_word *:(cpu_registers(processor)->gpr + RA)
22
cache:RA:RA_BITMASK:unsigned32:(1 << RA)
23
compute:RA:RA_is_0:int:(RA == 0)
24
cache:RT:RT::
25
cache:RT:rT:signed_word *:(cpu_registers(processor)->gpr + RT)
26
cache:RT:RT_BITMASK:unsigned32:(1 << RT)
27
cache:RS:RS::
28
cache:RS:rS:signed_word *:(cpu_registers(processor)->gpr + RS)
29
cache:RS:RS_BITMASK:unsigned32:(1 << RS)
30
cache:RB:RB::
31
cache:RB:rB:signed_word *:(cpu_registers(processor)->gpr + RB)
32
cache:RB:RB_BITMASK:unsigned32:(1 << RB)
33
scratch:FRA:FRA::
34
cache:FRA:frA:unsigned64 *:(cpu_registers(processor)->fpr + FRA)
35
cache:FRA:FRA_BITMASK:unsigned32:(1 << FRA)
36
scratch:FRB:FRB::
37
cache:FRB:frB:unsigned64 *:(cpu_registers(processor)->fpr + FRB)
38
cache:FRB:FRB_BITMASK:unsigned32:(1 << FRB)
39
scratch:FRC:FRC::
40
cache:FRC:frC:unsigned64 *:(cpu_registers(processor)->fpr + FRC)
41
cache:FRC:FRC_BITMASK:unsigned32:(1 << FRC)
42
scratch:FRS:FRS::
43
cache:FRS:frS:unsigned64 *:(cpu_registers(processor)->fpr + FRS)
44
cache:FRS:FRS_BITMASK:unsigned32:(1 << FRS)
45
scratch:FRT:FRT::
46
cache:FRT:frT:unsigned64 *:(cpu_registers(processor)->fpr + FRT)
47
cache:FRT:FRT_BITMASK:unsigned32:(1 << FRT)
48
cache:SI:EXTS_SI:unsigned_word:((signed_word)(signed16)instruction)
49
scratch:BI:BI::
50
cache:BI:BIT32_BI::BIT32(BI)
51
cache:BF:BF::
52
cache:BF:BF_BITMASK:unsigned32:(1 << BF)
53
scratch:BA:BA::
54
cache:BA:BIT32_BA::BIT32(BA)
55
cache:BA:BA_BITMASK:unsigned32:(1 << BA)
56
scratch:BB:BB::
57
cache:BB:BIT32_BB::BIT32(BB)
58
cache:BB:BB_BITMASK:unsigned32:(1 << BB)
59
cache:BT:BT::
60
cache:BT:BT_BITMASK:unsigned32:(1 << BT)
61
cache:BD:EXTS_BD_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~3)
62
cache:LI:EXTS_LI_0b00:unsigned_word:((((signed_word)(signed32)(instruction << 6)) >> 6) & ~0x3)
63
cache:D:EXTS_D:unsigned_word:((signed_word)(signed16)(instruction))
64
cache:DS:EXTS_DS_0b00:unsigned_word:(((signed_word)(signed16)instruction) & ~0x3)
65
#compute:SPR:SPR_is_256:int:(SPR == 256)

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.