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[/] [or1k/] [trunk/] [insight/] [sim/] [ppc/] [registers.h] - Blame information for rev 1765

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1 578 markom
/*  This file is part of the program psim.
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    Copyright (C) 1994-1997, Andrew Cagney <cagney@highland.com.au>
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    This program is free software; you can redistribute it and/or modify
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    it under the terms of the GNU General Public License as published by
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    the Free Software Foundation; either version 2 of the License, or
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    (at your option) any later version.
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    This program is distributed in the hope that it will be useful,
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    but WITHOUT ANY WARRANTY; without even the implied warranty of
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    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
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    GNU General Public License for more details.
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    You should have received a copy of the GNU General Public License
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    along with this program; if not, write to the Free Software
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    Foundation, Inc., 59 Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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    */
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#ifndef _REGISTERS_H_
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#define _REGISTERS_H_
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/*
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 * The PowerPC registers
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 *
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 */
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/**
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 ** General Purpose Registers
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 **/
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typedef signed_word gpreg;
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38
 
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/**
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 ** Floating Point Registers
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 **/
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typedef unsigned64 fpreg;
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/**
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 ** The condition register
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 **
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 **/
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typedef unsigned32 creg;
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/* The following sub bits are defined for the condition register */
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enum {
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  cr_i_negative = BIT4(0),
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  cr_i_positive = BIT4(1),
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  cr_i_zero = BIT4(2),
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  cr_i_summary_overflow = BIT4(3),
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#if 0
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  /* cr0 - integer status */
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  cr0_i_summary_overflow_bit = 3,
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  cr0_i_negative = BIT32(0),
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  cr0_i_positive = BIT32(1),
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  cr0_i_zero = BIT32(2),
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  cr0_i_summary_overflow = BIT32(3),
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  cr0_i_mask = MASK32(0,3),
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#endif
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  /* cr1 - floating-point status */
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  cr1_i_floating_point_exception_summary_bit = 4,
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  cr1_i_floating_point_enabled_exception_summary_bit = 5,
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  cr1_i_floating_point_invalid_operation_exception_summary_bit = 6,
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  cr1_i_floating_point_overflow_exception_bit = 7,
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  cr1_i_floating_point_exception_summary = BIT32(4),
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  cr1_i_floating_point_enabled_exception_summary = BIT32(5),
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  cr1_i_floating_point_invalid_operation_exception_summary = BIT32(6),
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  cr1_i_floating_point_overflow_exception = BIT32(7),
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  cr1_i_mask = MASK32(4,7),
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};
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/* Condition register 1 contains the result of floating point arithmetic */
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enum {
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  cr_fp_exception = BIT4(0),
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  cr_fp_enabled_exception = BIT4(1),
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  cr_fp_invalid_exception = BIT4(2),
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  cr_fp_overflow_exception = BIT4(3),
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};
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/**
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 ** Floating-Point Status and Control Register
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 **/
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typedef unsigned32 fpscreg;
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enum {
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  fpscr_fx_bit = 0,
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  fpscr_fx = BIT32(0),
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  fpscr_fex_bit = 1,
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  fpscr_fex = BIT32(1),
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  fpscr_vx_bit = 2,
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  fpscr_vx = BIT32(2),
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  fpscr_ox_bit = 3,
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  fpscr_ox = BIT32(3),
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  fpscr_ux = BIT32(4),
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  fpscr_zx = BIT32(5),
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  fpscr_xx = BIT32(6),
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  fpscr_vxsnan = BIT32(7), /* SNAN */
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  fpscr_vxisi = BIT32(8), /* INF - INF */
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  fpscr_vxidi = BIT32(9), /* INF / INF */
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  fpscr_vxzdz = BIT32(10), /* 0 / 0 */
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  fpscr_vximz = BIT32(11), /* INF * 0 */
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  fpscr_vxvc = BIT32(12),
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  fpscr_fr = BIT32(13),
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  fpscr_fi = BIT32(14),
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  fpscr_fprf = MASK32(15, 19),
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  fpscr_c = BIT32(15),
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  fpscr_fpcc_bit = 16, /* well sort of */
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  fpscr_fpcc = MASK32(16, 19),
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  fpscr_fl = BIT32(16),
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  fpscr_fg = BIT32(17),
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  fpscr_fe = BIT32(18),
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  fpscr_fu = BIT32(19),
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  fpscr_rf_quiet_nan = fpscr_c | fpscr_fu,
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  fpscr_rf_neg_infinity = fpscr_fl | fpscr_fu,
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  fpscr_rf_neg_normal_number = fpscr_fl,
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  fpscr_rf_neg_denormalized_number = fpscr_c | fpscr_fl,
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  fpscr_rf_neg_zero = fpscr_c | fpscr_fe,
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  fpscr_rf_pos_zero = fpscr_fe,
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  fpscr_rf_pos_denormalized_number = fpscr_c | fpscr_fg,
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  fpscr_rf_pos_normal_number = fpscr_fg,
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  fpscr_rf_pos_infinity = fpscr_fg | fpscr_fu,
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  fpscr_reserved_20 = BIT32(20),
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  fpscr_vxsoft = BIT32(21),
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  fpscr_vxsqrt = BIT32(22),
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  fpscr_vxcvi = BIT32(23),
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  fpscr_ve = BIT32(24),
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  fpscr_oe = BIT32(25),
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  fpscr_ue = BIT32(26),
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  fpscr_ze = BIT32(27),
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  fpscr_xe = BIT32(28),
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  fpscr_ni = BIT32(29),
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  fpscr_rn = MASK32(30, 31),
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  fpscr_rn_round_to_nearest = 0,
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  fpscr_rn_round_towards_zero = MASK32(31,31),
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  fpscr_rn_round_towards_pos_infinity = MASK32(30,30),
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  fpscr_rn_round_towards_neg_infinity = MASK32(30,31),
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  fpscr_vx_bits = (fpscr_vxsnan | fpscr_vxisi | fpscr_vxidi
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                   | fpscr_vxzdz | fpscr_vximz | fpscr_vxvc
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                   | fpscr_vxsoft | fpscr_vxsqrt | fpscr_vxcvi),
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};
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/**
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 ** XER Register
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 **/
160
 
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typedef unsigned32 xereg;
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enum {
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  xer_summary_overflow = BIT32(0), xer_summary_overflow_bit = 0,
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  xer_carry = BIT32(2), xer_carry_bit = 2,
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  xer_overflow = BIT32(1),
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  xer_reserved_3_24 = MASK32(3,24),
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  xer_byte_count_mask = MASK32(25,31)
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};
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/**
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 ** SPR's
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 **/
175
 
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#include "spreg.h"
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/**
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 ** Segment Registers
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 **/
182
 
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typedef unsigned32 sreg;
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enum {
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  nr_of_srs = 16
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};
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/**
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 ** Machine state register
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 **/
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typedef unsigned_word msreg; /* 32 or 64 bits */
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enum {
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#if (WITH_TARGET_WORD_BITSIZE == 64)
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  msr_64bit_mode = BIT(0),
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#endif
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#if (WITH_TARGET_WORD_BITSIZE == 32)
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  msr_64bit_mode = 0,
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#endif
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  msr_power_management_enable = BIT(45),
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  msr_tempoary_gpr_remapping = BIT(46), /* 603 specific */
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  msr_interrupt_little_endian_mode = BIT(47),
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  msr_external_interrupt_enable = BIT(48),
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  msr_problem_state = BIT(49),
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  msr_floating_point_available = BIT(50),
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  msr_machine_check_enable = BIT(51),
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  msr_floating_point_exception_mode_0 = BIT(52),
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  msr_single_step_trace_enable = BIT(53),
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  msr_branch_trace_enable = BIT(54),
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  msr_floating_point_exception_mode_1 = BIT(55),
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  msr_interrupt_prefix = BIT(57),
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  msr_instruction_relocate = BIT(58),
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  msr_data_relocate = BIT(59),
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  msr_recoverable_interrupt = BIT(62),
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  msr_little_endian_mode = BIT(63)
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};
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enum {
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  srr1_hash_table_or_ibat_miss = BIT(33),
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  srr1_direct_store_error_exception = BIT(35),
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  srr1_protection_violation = BIT(36),
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  srr1_segment_table_miss = BIT(42),
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  srr1_floating_point_enabled = BIT(43),
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  srr1_illegal_instruction = BIT(44),
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  srr1_priviliged_instruction = BIT(45),
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  srr1_trap = BIT(46),
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  srr1_subsequent_instruction = BIT(47)
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};
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/**
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 ** storage interrupt registers
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 **/
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typedef enum {
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  dsisr_direct_store_error_exception = BIT32(0),
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  dsisr_hash_table_or_dbat_miss = BIT32(1),
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  dsisr_protection_violation = BIT32(4),
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  dsisr_earwax_violation = BIT32(5),
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  dsisr_store_operation = BIT32(6),
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  dsisr_segment_table_miss = BIT32(10),
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  dsisr_earwax_disabled = BIT32(11)
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} dsisr_status;
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/**
249
 ** And the registers proper
250
 **/
251
typedef struct _registers {
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253
  gpreg gpr[32];
254
  fpreg fpr[32];
255
  creg cr;
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  fpscreg fpscr;
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258
  /* Machine state register */
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  msreg msr;
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  /* Spr's */
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  spreg spr[nr_of_sprs];
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  /* Segment Registers */
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  sreg sr[nr_of_srs];
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267
} registers;
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/* dump out all the registers */
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INLINE_REGISTERS\
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(void) registers_dump
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(registers *regs);
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/* return information on a register based on name */
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typedef enum {
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  reg_invalid,
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  reg_gpr, reg_fpr, reg_spr, reg_msr,
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  reg_cr, reg_fpscr, reg_pc, reg_sr,
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  reg_insns, reg_stalls, reg_cycles,
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  nr_register_types
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} register_types;
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typedef struct {
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  register_types type;
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  int index;
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  int size;
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} register_descriptions;
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293
INLINE_REGISTERS\
294
(register_descriptions) register_description
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(const char reg[]);
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297
 
298
/* Special purpose registers by their more common names */
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#define SPREG(N)        cpu_registers(processor)->spr[N]
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#define XER             SPREG(spr_xer)
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#define LR              SPREG(spr_lr)
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#define CTR             SPREG(spr_ctr)
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#define SRR0            SPREG(spr_srr0)
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#define SRR1            SPREG(spr_srr1)
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#define DAR             SPREG(spr_dar)
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#define DSISR           SPREG(spr_dsisr)
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309
/* general purpose registers - indexed access */
310
#define GPR(N)          cpu_registers(processor)->gpr[N]
311
 
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/* segment registers */
313
#define SEGREG(N)       cpu_registers(processor)->sr[N]
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/* condition register */
316
#define CR              cpu_registers(processor)->cr
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318
/* machine status register */
319
#define MSR             cpu_registers(processor)->msr
320
 
321
/* floating-point status condition register */
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#define FPSCR           cpu_registers(processor)->fpscr
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#endif /* _REGISTERS_H_ */

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