OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [insight/] [sim/] [testsuite/] [d30v-elf/] [ls-modaddr.S] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 markom
        ; Modular address postincrement/postdecrement test
2
 
3
start:
4
        ;  program PSW for modular address mode
5
        add  r1,r0,0x81000000
6
        nop || nop
7
        mvtsys psw,r1 || nop
8
        nop || nop
9
 
10
test1:
11
        ; set modular address limits: 0x18 bytes
12
        add  r1,r0,0x20000070    ; [start, ...
13
        nop || nop
14
        mvtsys mod_s,r1 || nop
15
        nop || nop
16
        add  r1,r0,0x20000088    ; ..., end)
17
        nop || nop
18
        mvtsys mod_e,r1 || nop
19
 
20
        ; modular autoincrement test
21
        add     r30,r0,0x20000070 ; base address = mod_s
22
        ld2w    r40,@(r30+,r0) || nop ; after:     r30 = ...078
23
        ld2w    r40,@(r30+,r0) || nop ; after:  r30 = ...080
24
        ld2w    r40,@(r30+,r0) || nop ; after:  r30 = ...070
25
 
26
        add     r29,r0,0x20000070 ; expected end address; wrapping around
27
        cmpeq   f1,r30,r29
28
        bra/xf  fail
29
 
30
test2:
31
        ; set modular address limits: 0x18 bytes
32
        add  r1,r0,0x20000088    ; [start, ...
33
        nop || nop
34
        mvtsys mod_s,r1 || nop
35
        nop || nop
36
        add  r1,r0,0x20000070    ; ..., end)
37
        nop || nop
38
        mvtsys mod_e,r1 || nop
39
 
40
        ; modular autodecrement test
41
        add     r30,r0,0x20000088 ; base address = mod_s
42
        ld2w    r40,@(r30-,r0) || nop ; after:  r30 = ...080
43
        ld2w    r40,@(r30-,r0) || nop ; after:  r30 = ...078
44
        ld2w    r40,@(r30-,r0) || nop ; after:  r30 = ...088
45
 
46
        add     r29,r0,0x20000088 ; expected end address; wrapping around
47
        cmpeq   f1,r30,r29
48
        bra/xf  fail
49
 
50
ok:
51
        add     r2,r0,0
52
        .long   0x0e000004, 0x00f00000
53
 
54
fail:
55
        add     r2,r0,47
56
        .long   0x0e000004, 0x00f00000

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.