OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [insight/] [sim/] [testsuite/] [sim/] [fr30/] [and.cgs] - Blame information for rev 578

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 markom
# fr30 testcase for and $Rj,$Ri, and $Rj,@$Ri
2
# mach(): fr30
3
 
4
        .include "testutils.inc"
5
 
6
        START
7
 
8
        .text
9
        .global and
10
and:
11
        ; Test and $Rj,$Ri
12
        mvi_h_gr        0xaaaaaaaa,r7
13
        mvi_h_gr        0x55555555,r8
14
        set_cc          0x0b            ; Set mask opposite of expected
15
        and             r7,r8
16
        test_cc         0 1 1 1
17
        test_h_gr       0,r8
18
 
19
        mvi_h_gr        0xffff0000,r8
20
        set_cc          0x04            ; Set mask opposite of expected
21
        and             r7,r8
22
        test_cc         1 0 0 0
23
        test_h_gr       0xaaaa0000,r8
24
 
25
        mvi_h_gr        0xffff,r8
26
        set_cc          0x0d            ; Set mask opposite of expected
27
        and             r7,r8
28
        test_cc         0 0 0 1
29
        test_h_gr       0xaaaa,r8
30
 
31
        ; Test and $Rj,@$Ri
32
        mvi_h_gr        0xaaaaaaaa,r7
33
        mvi_h_mem       0x55555555,sp
34
        set_cc          0x0b            ; Set mask opposite of expected
35
        and             r7,@sp
36
        test_cc         0 1 1 1
37
        test_h_mem      0,sp
38
 
39
        mvi_h_mem       0xffff0000,sp
40
        set_cc          0x04            ; Set mask opposite of expected
41
        and             r7,@sp
42
        test_cc         1 0 0 0
43
        test_h_mem      0xaaaa0000,sp
44
 
45
        mvr_h_gr        sp,r9
46
        inci_h_gr       4,r9
47
        mvi_h_mem       0xffffffff,sp
48
        mvi_h_mem       0xffff0000,r9
49
        inci_h_gr       1,sp            ; test unaligned access
50
        set_cc          0x05            ; Set mask opposite of expected
51
        and             r7,@sp
52
        test_cc         1 0 0 1
53
        inci_h_gr       -1,sp
54
        test_h_mem      0xaaaaaaaa,sp
55
        test_h_mem      0xffff0000,r9
56
 
57
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.