OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [insight/] [sim/] [testsuite/] [sim/] [fr30/] [stm0.cgs] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 578 markom
# fr30 testcase for stm0 ($reglist_low)
2
# mach(): fr30
3
 
4
        .include "testutils.inc"
5
 
6
        START
7
 
8
        .text
9
        .global stm0
10
stm0:
11
        ; Test stm0 ($reglist_low)
12
        mvr_h_gr        sp,r8           ; save stack pointer temporarily
13
        mvr_h_gr        sp,r9           ; save stack pointer permanently
14
        mvi_h_gr        0,r0
15
        mvi_h_gr        1,r1
16
        mvi_h_gr        2,r2
17
        mvi_h_gr        3,r3
18
        mvi_h_gr        4,r4
19
        mvi_h_gr        5,r5
20
        mvi_h_gr        6,r6
21
        mvi_h_gr        7,r7
22
        set_cc          0x0f            ; Condition codes should not change
23
        stm0            (r0,r2,r4,r6)
24
        test_cc         1 1 1 1
25
        inci_h_gr       -4,r8
26
        test_h_mem      6,r8
27
        inci_h_gr       -4,r8
28
        test_h_mem      4,r8
29
        inci_h_gr       -4,r8
30
        test_h_mem      2,r8
31
        inci_h_gr       -4,r8
32
        test_h_mem      0,r8
33
 
34
        mvr_h_gr        r9,sp           ; restore stack pointer
35
        mvr_h_gr        r9,r8           ; save stack pointer temporarily
36
        mvi_h_gr        0,r0
37
        mvi_h_gr        1,r1
38
        mvi_h_gr        2,r2
39
        mvi_h_gr        3,r3
40
        mvi_h_gr        4,r4
41
        mvi_h_gr        5,r5
42
        mvi_h_gr        6,r6
43
        mvi_h_gr        7,r7
44
        set_cc          0x0f            ; Condition codes should not change
45
        stm0            (r1,r3,r5,r7)
46
        test_cc         1 1 1 1
47
        inci_h_gr       -4,r8
48
        test_h_mem      7,r8
49
        inci_h_gr       -4,r8
50
        test_h_mem      5,r8
51
        inci_h_gr       -4,r8
52
        test_h_mem      3,r8
53
        inci_h_gr       -4,r8
54
        test_h_mem      1,r8
55
 
56
        mvr_h_gr        r9,sp           ; restore stack pointer
57
        mvr_h_gr        r9,r8           ; save stack pointer temporarily
58
        mvi_h_gr        0,r0
59
        mvi_h_gr        1,r1
60
        mvi_h_gr        2,r2
61
        mvi_h_gr        3,r3
62
        mvi_h_gr        4,r4
63
        mvi_h_gr        5,r5
64
        mvi_h_gr        6,r6
65
        mvi_h_gr        7,r7
66
        set_cc          0x0f            ; Condition codes should not change
67
        stm0            (r1,r5,r7,r3)   ; Order specified should not matter
68
        test_cc         1 1 1 1
69
        inci_h_gr       -4,r8
70
        test_h_mem      7,r8
71
        inci_h_gr       -4,r8
72
        test_h_mem      5,r8
73
        inci_h_gr       -4,r8
74
        test_h_mem      3,r8
75
        inci_h_gr       -4,r8
76
        test_h_mem      1,r8
77
 
78
        mvr_h_gr        r9,sp           ; restore stack pointer
79
        mvr_h_gr        r9,r8           ; save stack pointer temporarily
80
        mvi_h_gr        9,r0
81
        mvi_h_gr        9,r1
82
        mvi_h_gr        9,r2
83
        mvi_h_gr        9,r3
84
        mvi_h_gr        9,r4
85
        mvi_h_gr        9,r5
86
        mvi_h_gr        9,r6
87
        mvi_h_gr        9,r7
88
        set_cc          0x0f            ; Condition codes should not change
89
        stm0            ()              ; should do nothing
90
        test_cc         1 1 1 1
91
        testr_h_gr      r9,sp
92
        inci_h_gr       -4,r8
93
        test_h_mem      7,r8
94
        inci_h_gr       -4,r8
95
        test_h_mem      5,r8
96
        inci_h_gr       -4,r8
97
        test_h_mem      3,r8
98
        inci_h_gr       -4,r8
99
        test_h_mem      1,r8
100
 
101
        pass

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.