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[/] [or1k/] [trunk/] [insight/] [sim/] [tic80/] [tic80.ic] - Blame information for rev 1772

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cache:Dest:Dest:
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cache:Dest:rDest:signed_word *:(&(CPU)->reg[Dest])
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cache:Source1:vSource1:signed_word:(GPR (Source1) + 0)
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cache:Source:vSource:signed_word:(GPR (Source) + 0)
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cache:Base:Base:
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cache:SignedImmediate:vSource1:signed_word:SEXT (SignedImmediate, 14)
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cache:BITNUM:bitnum:int:(~BITNUM) & 0x1f
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cache:SignedOffset:vSignedOffset:signed_word:SEXT (SignedOffset, 14)
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cache:INDCR:UCRN:unsigned32:(GPR (INDCR) + 0)
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#cache:INDCR:UCRN:unsigned32:(INDCR == 0 ? 0 : (CPU)->reg[INDCR])

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