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[/] [or1k/] [trunk/] [jtag/] [jp2.c] - Blame information for rev 1277

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1 1246 markom 
/* jp2-linux.c -- JTAG protocol via parallel port for linux
2 
   Copyright(C) 2001 Marko Mlinar, markom@opencores.org
3 
   Code for TCP/IP copied from gdb, by Chris Ziomkowski
4 
 
5 
This file is part of OpenRISC 1000 Architectural Simulator.
6 
 
7 
This program is free software; you can redistribute it and/or modify
8 
it under the terms of the GNU General Public License as published by
9 
the Free Software Foundation; either version 2 of the License, or
10 
(at your option) any later version.
11 
 
12 
This program is distributed in the hope that it will be useful,
13 
but WITHOUT ANY WARRANTY; without even the implied warranty of
14 
MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
15 
GNU General Public License for more details.
16 
 
17 
You should have received a copy of the GNU General Public License
18 
along with this program; if not, write to the Free Software
19 
Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. */
20 
 
21 
/* Establishes jtag proxy server and communicates with parallel
22 
 port directly.  Requires root access. */
23 
 
24 1274 markom 
#include <assert.h>
25 1246 markom 
#include <stdio.h>
26 
#include <ctype.h>
27 
#include <string.h>
28 
#include <stdlib.h>
29 
#include <unistd.h>
30 
#include <stdarg.h>
31 1259 markom 
#include <sys/stat.h>
32 
#include <sys/types.h>
33 1246 markom 
 
34 
/* Dirty way to include inb and outb from, but they say it is
35 
   a standard one.  */
36 
#include <asm/io.h>
37 
#include <asm/system.h>
38 
#include "mc.h"
39 
#include "gdb.h"
40 
#include "jp2.h"
41 
 
42 1259 markom 
#define TC_RESET           0
43 
#define TC_BRIGHT          1
44 
#define TC_DIM             2
45 
#define TC_UNDERLINE       3
46 
#define TC_BLINK           4
47 
#define TC_REVERSE         7
48 
#define TC_HIDDEN          8
49 
 
50 
#define TC_BLACK           0
51 
#define TC_RED             1
52 
#define TC_GREEN           2
53 
#define TC_YELLOW          3
54 
#define TC_BLUE            4
55 
#define TC_MAGENTA         5
56 
#define TC_CYAN            6
57 
#define TC_WHITE           7
58 
 
59 1274 markom 
#define SDRAM_BASE       0x00000000
60 
#define SDRAM_SIZE       0x04000000
61 
#define SRAM_BASE        0x40000000
62 
#define SRAM_SIZE        0x04000000 // This is not ok
63 
 
64 
 
65 
 
66 1246 markom 
static int base = 0x378; /* FIXME: We should detect the address. */
67 
int err = 0;
68 
int set_pc = 0;
69 
int set_step = 0;
70 
int waiting = 0;
71 
 
72 
/* Scan chain info. */
73 
static int chain_addr_size[] = { 0,  32, 0,  0,  5,  32, 32};
74 
static int chain_data_size[] = { 0,  32, 0,  32, 32, 32, 32};
75 
static int chain_is_valid[]  = { 0,  1,  0,  1,  1,  1,   1};
76 
static int chain_has_crc[]   = { 0,  1,  0,  1,  1,  1,   1};
77 
static int chain_has_rw[]    = { 0,  1,  0,  0,  1,  1,   1};
78 
 
79 
/* Currently selected scan chain - just to prevent unnecessary
80 
   transfers. */
81 
static int current_chain = -1;
82 
 
83 
/* The chain that should be currently selected. */
84 
static int dbg_chain = -1;
85 
 
86 
/* Crc of current read or written data.  */
87 
static int crc_r, crc_w = 0;
88 
 
89 
/* Address of previous read */
90 
static unsigned long prev_regno = 0;
91 
 
92 
/* Generates new crc, sending in new bit input_bit */
93 
static unsigned long crc_calc(unsigned long crc, int input_bit) {
94 
  unsigned long d = (input_bit&1) ? 0xfffffff : 0x0000000;
95 
  unsigned long crc_32 = ((crc >> 31)&1) ? 0xfffffff : 0x0000000;
96 
  crc <<= 1;
97 
  return crc ^ (d ^ crc_32) & DBG_CRC_POLY;
98 
}
99 
 
100 
/* Send a byte to parallel port. */
101 
inline static void jp2_out(unsigned int value) {
102 
#ifdef RTL_SIM
103 
  time_t time;
104 
  struct stat s;
105 
  char buf[1000];
106 
  FILE *fout;
107 
  unsigned num_read;
108 
  int r;
109 
  fout = fopen(GDB_IN, "wt+");
110 
  fprintf(fout, "F\n");
111 
  fclose(fout);
112 
  fout = fopen(GDB_OUT, "wt+");
113 
  fprintf(fout, "%02X\n", value);
114 
  fclose(fout);
115 
error:
116 
  fout = fopen(GDB_OUT, "rt");
117 
  r = fscanf(fout,"%x", &num_read);
118 
  fclose(fout);
119 
  if(r == 0 || num_read !=(0x10 | value)) goto error;
120 
#else
121 
  outb(value, LPT_WRITE);
122 
#endif /* RTL_SIM */
123 1259 markom 
  if (!(value & TCLK_BIT)) {
124 
    if (value & TMS_BIT) debug("%c[%d;%dm", 0x1b, TC_BRIGHT, TC_WHITE + 30);
125 
    debug("%x",(value & TDI_BIT) != 0);
126 
    debug("%c[%d;%dm", 0x1b, TC_RESET, TC_WHITE + 30);
127 
  }
128 1246 markom 
  flush_debug();
129 
}
130 
 
131 
/* Receive a byte from parallel port.  */
132 
inline static unsigned char jp2_in() {
133 
  int data;
134 
#ifndef RTL_SIM
135 
  data = inb(LPT_READ);
136 
#ifdef TDO_INV
137 
  data =(data & TDO_BIT) != TDO_BIT;
138 
#else
139 
  data =(data & TDO_BIT) == TDO_BIT;
140 
#endif
141 
#else
142 
  FILE *fin = 0;
143 
  char ch;
144 
  time_t time;
145 
  struct stat s;
146 
  while(1) {
147 
    fin = fopen(GDB_IN, "rt");
148 
    if(fin == 0) continue;
149 
    ch = fgetc(fin);
150 
    if(ch != '0' && ch != '1') {
151 
      fclose(fin);
152 
      continue;
153 
    } else break;
154 
  }
155 
  fclose(fin);
156 
  data = ch == '1';
157 
#endif /* !RTL_SIM */
158 1259 markom 
  debug("%c[%d;%dm", 0x1b, TC_BRIGHT, TC_GREEN + 30);
159 
  debug("%01X", data);
160 
  debug("%c[%d;%dm", 0x1b, TC_RESET, TC_WHITE + 30);
161 1246 markom 
  flush_debug();
162 
  return data;
163 
}
164 
 
165 
/* Writes TCLK=0, TRST=1, TMS=bit1, TDI=bit0
166 
   and    TCLK=1, TRST=1, TMS=bit1, TDI=bit0 */
167 
static inline void jp2_write_JTAG(unsigned char packet) {
168 
  unsigned char data = TRST_BIT;
169 
  if(packet & 1) data |= TDI_BIT;
170 
  if(packet & 2) data |= TMS_BIT;
171 
 
172 
  jp2_out(data);
173 
  JTAG_WAIT();
174 
  crc_w = crc_calc(crc_w, packet&1);
175 
 
176 
  /* rise clock */
177 
  jp2_out(data | TCLK_BIT);
178 
  JTAG_WAIT();
179 
}
180 
 
181 
/* Reads TDI.  */
182 
static inline int jp2_read_JTAG() {
183 
  int data;
184 
  data = jp2_in();
185 
  crc_r = crc_calc(crc_r, data);
186 
  return data;
187 
}
188 
 
189 
/* Writes bitstream.  LS bit first if len < 0, MS bit first if len > 0.  */
190 
static inline void jp2_write_stream(ULONGEST stream, int len, int set_last_bit) {
191 
  int i;
192 
  if (len < 0) {
193 
    len = -len;
194 1259 markom 
    debug("writeL%d(", len);
195 1246 markom 
    for(i = 0; i < len - 1; i++)
196 
      jp2_write_JTAG((stream >> i) & 1);
197 
 
198 
    if(set_last_bit) jp2_write_JTAG((stream >>(len - 1))& 1 | TMS);
199 
    else jp2_write_JTAG((stream >>(len - 1))& 1);
200 
  } else {
201 1259 markom 
    debug("write%d(", len);
202 1246 markom 
    for(i = 0; i < len - 1; i++)
203 
      jp2_write_JTAG((stream >> (len - 1 - i)) & 1);
204 
 
205 
    if(set_last_bit) jp2_write_JTAG((stream >> 0) & 1 | TMS);
206 
    else jp2_write_JTAG((stream >> 0)& 1);
207 
  }
208 
  debug(")\n");
209 
}
210 
 
211 
/* Gets bitstream.  LS bit first if len < 0, MS bit first if len > 0.  */
212 
inline static ULONGEST jp2_read_stream(unsigned long stream, int len, int set_last_bit) {
213 
  int i;
214 
  ULONGEST data = 0;
215 
  if (len < 0) {
216 1259 markom 
    debug("readL(");
217 1246 markom 
    for(i = 0; i < len - 1; i++) {
218 
      jp2_write_JTAG((stream >> i) & 1);   /* LSB first */
219 
      data |= jp2_read_JTAG() << i; /* LSB first */
220 
    }
221 
 
222 
    if (set_last_bit) jp2_write_JTAG((stream >> (len - 1)) & 1 | TMS);
223 
    else jp2_write_JTAG((stream >> (len - 1)) & 1);
224 
    data |= jp2_read_JTAG() << (len - 1);
225 
  } else {
226 1259 markom 
    debug("read(");
227 1246 markom 
    for(i = 0; i < len - 1; i++) {
228 
      jp2_write_JTAG((stream >> (len - 1 - i)) & 1);   /* MSB first */
229 
      data |= jp2_read_JTAG() << (len - 1 - i); /* MSB first */
230 
    }
231 
 
232 
    if (set_last_bit) jp2_write_JTAG((stream >> 0) & 1 | TMS);
233 
    else jp2_write_JTAG((stream >> 0) & 1);
234 
    data |= jp2_read_JTAG() << 0;
235 
  }
236 
  debug(")\n");
237 
  return data;
238 
}
239 
 
240 
/* Sets scan chain.  */
241 
void jtag_set_ir(int ir) {
242 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
243 
  jp2_write_JTAG(TMS); /* SELECT_IR SCAN */
244 
 
245 
  jp2_write_JTAG(0); /* CAPTURE_IR */
246 
  jp2_write_JTAG(0); /* SHIFT_IR */
247 
 
248 
  /* write data, EXIT1_IR */
249 
  jp2_write_stream(ir, -JI_SIZE, 1);
250 
 
251 
  jp2_write_JTAG(TMS); /* UPDATE_IR */
252 
  jp2_write_JTAG(0); /* IDLE */
253 
  current_chain = -1;
254 
}
255 
 
256 
/* Resets JTAG
257 
   Writes TRST=0
258 
   and    TRST=1 */
259 
static void jp2_reset_JTAG() {
260 
  int i;
261 
  debug2("\nreset(");
262 
  jp2_out(0);
263 
  JTAG_RETRY_WAIT();
264 
  /* In case we don't have TRST reset it manually */
265 
  for(i = 0; i < 8; i++) jp2_write_JTAG(TMS);
266 
  jp2_out(TRST_BIT);
267 
  JTAG_RETRY_WAIT();
268 
  jp2_write_JTAG(0);
269 
  debug2(")\n");
270 
}
271 
 
272 
/* Resets JTAG, and sets DEBUG scan chain */
273 
static int dbg_reset() {
274 
  int err;
275 1274 markom 
  unsigned long id;
276 1246 markom 
  jp2_reset_JTAG();
277 1274 markom 
 
278 
  /* read ID */
279 
  jtag_set_ir(JI_IDCODE);
280 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
281 
  jp2_write_JTAG(0); /* CAPTURE_DR */
282 
  jp2_write_JTAG(0); /* SHIFT_DR */
283 
  /* read ID, EXIT1_DR */
284 
  crc_w = 0xffffffff;
285 
  id = jp2_read_stream(0, 32, 1);
286 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
287 
  jp2_write_JTAG(0); /* IDLE */
288 
  printf("JTAG ID = %08x\n", id);
289 
 
290 1246 markom 
  /* select debug scan chain and stay in it forever */
291 
  jtag_set_ir(JI_DEBUG);
292 
  current_chain = -1;
293 
  return DBG_ERR_OK;
294 
}
295 1274 markom 
 
296 1259 markom 
/* counts retries and returns zero if we should abort */
297 1246 markom 
/* TODO: dinamically adjust timings for jp2 */
298 
static int retry_no = 0;
299 
int retry_do() {
300 
  int i, err;
301 1259 markom 
  printf("RETRY\n");
302 1274 markom 
  //exit(2);
303 1246 markom 
  if (retry_no >= NUM_SOFT_RETRIES) {
304 
    if ((err = dbg_reset())) return err;
305 
  } else { /* quick reset */
306 
    for(i = 0; i < 8; i++) jp2_write_JTAG(TMS);
307 
    jp2_write_JTAG(0); /* go into IDLE state */
308 
  }
309 
  if (retry_no >= NUM_SOFT_RETRIES + NUM_HARD_RETRIES) {
310 
    retry_no = 0;
311 1259 markom 
    return 0;
312 1246 markom 
  }
313 
  retry_no++;
314 1259 markom 
  return 1;
315 1246 markom 
}
316 
 
317 
/* resets retry counter */
318 
void retry_ok() {
319 
  retry_no = 0;
320 
}
321 
 
322 
/* Sets scan chain.  */
323 
int dbg_set_chain(int chain) {
324 
  int status, crc_generated, crc_read;
325 
  dbg_chain = chain;
326 
 
327 
try_again:
328 
  if (current_chain == chain) return DBG_ERR_OK;
329 
  current_chain = -1;
330 
  debug("\n");
331 
  debug2("set_chain %i\n", chain);
332 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
333 
  jp2_write_JTAG(0); /* CAPTURE_DR */
334 
  jp2_write_JTAG(0); /* SHIFT_DR */
335 
 
336 
  /* write data, EXIT1_DR */
337 1259 markom 
  crc_w = 0xffffffff;
338 1274 markom 
  jp2_write_stream((chain & 0xf | (1<<DC_SIZE)), DC_SIZE + 1, 0);
339 1246 markom 
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
340 1259 markom 
  crc_r = 0xffffffff;
341 1246 markom 
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
342 
  crc_generated = crc_r;
343 
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
344 
 
345 1274 markom 
  //printf("%x %x %x\n", status, crc_read, crc_generated);
346 
  /* CRCs must match, otherwise retry */
347 
  if (crc_read != crc_generated) {
348 1246 markom 
    if (retry_do()) goto try_again;
349 
    else return DBG_ERR_CRC;
350 
  }
351 1274 markom 
  /* we should read expected status value, otherwise retry */
352 
  if (status != 0) {
353 
    if (retry_do()) goto try_again;
354 
    else return status;
355 
  }
356 1246 markom 
 
357 
  /* reset retry counter */
358 
  retry_ok();
359 
 
360 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
361 
  jp2_write_JTAG(0); /* IDLE */
362 
  current_chain = chain;
363 
  return DBG_ERR_OK;
364 
}
365 
 
366 
/* sends out a command with 32bit address and 16bit length, if len >= 0 */
367 1274 markom 
int dbg_command(int type, unsigned long adr, int len) {
368 1246 markom 
  int status, crc_generated, crc_read;
369 
 
370 
try_again:
371 
  dbg_set_chain(dbg_chain);
372 
  debug("\n");
373 1274 markom 
  debug2("comm %i\n", type);
374 1246 markom 
 
375 
  /***** WRITEx *****/
376 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
377 
  jp2_write_JTAG(0); /* CAPTURE_DR */
378 
  jp2_write_JTAG(0); /* SHIFT_DR */
379 
 
380 
  /* write data, EXIT1_DR */
381 1259 markom 
  crc_w = 0xffffffff;
382 1274 markom 
  jp2_write_stream((DI_WRITE_CMD & 0xf | (0<<DC_SIZE)), DC_SIZE + 1, 0);
383 
  jp2_write_stream(type, 4, 0);
384 1246 markom 
  jp2_write_stream(adr, 32, 0);
385 1274 markom 
  assert(len > 0);
386 
  jp2_write_stream(len - 1, 16, 0);
387 1246 markom 
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
388 1259 markom 
  crc_r = 0xffffffff;
389 1246 markom 
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
390 
  crc_generated = crc_r;
391 
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
392 
 
393 1274 markom 
  /* CRCs must match, otherwise retry */
394 
  if (crc_read != crc_generated) {
395 1246 markom 
    if (retry_do()) goto try_again;
396 
    else return DBG_ERR_CRC;
397 
  }
398 1274 markom 
  /* we should read expected status value, otherwise retry */
399 
  if (status != 0) {
400 
    if (retry_do()) goto try_again;
401 
    else return status;
402 
  }
403 1246 markom 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
404 
  jp2_write_JTAG(0); /* IDLE */
405 
 
406 
  /* reset retry counter */
407 
  retry_ok();
408 
  return DBG_ERR_OK;
409 
}
410 
 
411 1274 markom 
/* writes a ctrl reg */
412 
int dbg_ctrl(int reset, int stall) {
413 1246 markom 
  int status, crc_generated, crc_read;
414 
 
415 
try_again:
416 
  dbg_set_chain(dbg_chain);
417 
  debug("\n");
418 1274 markom 
  debug2("ctrl\n");
419 1246 markom 
 
420 1274 markom 
  /***** WRITEx *****/
421 1246 markom 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
422 
  jp2_write_JTAG(0); /* CAPTURE_DR */
423 
  jp2_write_JTAG(0); /* SHIFT_DR */
424 
 
425 
  /* write data, EXIT1_DR */
426 1259 markom 
  crc_w = 0xffffffff;
427 1274 markom 
  jp2_write_stream((DI_WRITE_CTRL & 0xf | (0<<DC_SIZE)), DC_SIZE + 1, 0);
428 
  jp2_write_stream(reset, 1, 0);
429 
  jp2_write_stream(stall, 1, 0);
430 
  jp2_write_stream(0, 50, 0);
431 1246 markom 
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
432 1259 markom 
  crc_r = 0xffffffff;
433 1246 markom 
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
434 
  crc_generated = crc_r;
435 
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
436 
 
437 1274 markom 
  /* CRCs must match, otherwise retry */
438 
  //printf("%x %x %x\n", status, crc_read, crc_generated);
439 
  if (crc_read != crc_generated) {
440 1246 markom 
    if (retry_do()) goto try_again;
441 
    else return DBG_ERR_CRC;
442 
  }
443 1274 markom 
  /* we should read expected status value, otherwise retry */
444 
  if (status != 0) {
445 
    if (retry_do()) goto try_again;
446 
    else return status;
447 
  }
448 1246 markom 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
449 
  jp2_write_JTAG(0); /* IDLE */
450 
 
451 
  /* reset retry counter */
452 
  retry_ok();
453 
  return DBG_ERR_OK;
454 
}
455 
 
456 1274 markom 
/* reads control register */
457 
int dbg_ctrl_read(int *reset, int *stall) {
458 1246 markom 
  int status, crc_generated, crc_read;
459 
 
460 
try_again:
461 
  dbg_set_chain(dbg_chain);
462 
  debug("\n");
463 1274 markom 
  debug2("ctrl_read\n");
464 1246 markom 
 
465 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
466 
  jp2_write_JTAG(0); /* CAPTURE_DR */
467 
  jp2_write_JTAG(0); /* SHIFT_DR */
468 
 
469 
  /* write data, EXIT1_DR */
470 1259 markom 
  crc_w = 0xffffffff;
471 1274 markom 
  jp2_write_stream(DI_READ_CTRL | (0<<DC_SIZE), DC_SIZE + 1, 0);
472 1246 markom 
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
473 1259 markom 
  crc_r = 0xffffffff;
474 1274 markom 
  *reset = jp2_read_stream(0, 1, 0);
475 
  *stall = jp2_read_stream(0, 1, 0);
476 
  jp2_read_stream(0, 50, 0);
477 1246 markom 
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
478 
  crc_generated = crc_r;
479 
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
480 1274 markom 
 
481 
  /* CRCs must match, otherwise retry */
482 
  //printf("%x %x %x\n", status, crc_read, crc_generated);
483 
  if (crc_read != crc_generated) {
484 
    if (retry_do()) goto try_again;
485 
    else return DBG_ERR_CRC;
486 
  }
487 
  /* we should read expected status value, otherwise retry */
488 
  if (status != 0) {
489 
    if (retry_do()) goto try_again;
490 
    else return status;
491 
  }
492 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
493 
  jp2_write_JTAG(0); /* IDLE */
494 1246 markom 
 
495 1274 markom 
  /* reset retry counter */
496 
  retry_ok();
497 
  return DBG_ERR_OK;
498 
}
499 
/* issues a burst read/write */
500 
int dbg_go(unsigned char *data, unsigned short len, int read) {
501 
  int status, crc_generated, crc_read;
502 
  int i;
503 
 
504 
try_again:
505 
  dbg_set_chain(dbg_chain);
506 
  debug("\n");
507 
  debug2("go len = %d\n", len);
508 
 
509 
  jp2_write_JTAG(TMS); /* SELECT_DR SCAN */
510 
  jp2_write_JTAG(0); /* CAPTURE_DR */
511 
  jp2_write_JTAG(0); /* SHIFT_DR */
512 
 
513 
  /* write data, EXIT1_DR */
514 
  crc_w = 0xffffffff;
515 
  jp2_write_stream(DI_GO | (0<<DC_SIZE), DC_SIZE + 1, 0);
516 
  if (!read) {
517 
    /* reverse byte ordering, since we must send in big endian */
518 
    for (i = 0; i < len; i++)
519 
      jp2_write_stream(data[i], 8, 0);
520 1246 markom 
  }
521 1274 markom 
  jp2_write_stream(crc_w, DBG_CRC_SIZE, 0);
522 
  crc_r = 0xffffffff;
523 
  if (read) {
524 
    /* reverse byte ordering, since we must send in big endian */
525 
    for (i = 0; i < len; i++)
526 
      data[i] = jp2_read_stream(data[i], 8, 0);
527 
  }
528 
  status = jp2_read_stream(0, DC_STATUS_SIZE, 0);
529 
  crc_generated = crc_r;
530 
  crc_read = jp2_read_stream(0, DBG_CRC_SIZE, 1);
531 
 
532 
  /* CRCs must match, otherwise retry */
533 
  //printf("%x %x %x\n", status, crc_read, crc_generated);
534 
  if (crc_read != crc_generated) {
535 1246 markom 
    if (retry_do()) goto try_again;
536 
    else return DBG_ERR_CRC;
537 
  }
538 1274 markom 
  /* we should read expected status value, otherwise retry */
539 
  if (status != 0) {
540 
    if (retry_do()) goto try_again;
541 
    else return status;
542 
  }
543 1246 markom 
  jp2_write_JTAG(TMS); /* UPDATE_DR */
544 1274 markom 
  jp2_write_JTAG(0); /* IDLE */
545 1246 markom 
 
546 
  /* reset retry counter */
547 
  retry_ok();
548 
  return DBG_ERR_OK;
549 
}
550 
 
551 1274 markom 
/* read a word from wishbone */
552 
int dbg_wb_read32(unsigned long adr, unsigned long *data) {
553 1246 markom 
  int err;
554 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
555 1274 markom 
  if ((err = dbg_command(0x6, adr, 4))) return err;
556 
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
557 
  *data = ntohl(*data);
558 
  return err;
559 1246 markom 
}
560 
 
561 1274 markom 
/* write a word to wishbone */
562 
int dbg_wb_write32(unsigned long adr, unsigned long data) {
563 1246 markom 
  int err;
564 1274 markom 
  data = ntohl(data);
565 1246 markom 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
566 1274 markom 
  if ((err = dbg_command(0x2, adr, 4))) return err;
567 
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
568 1246 markom 
  return DBG_ERR_OK;
569 
}
570 
 
571 1274 markom 
/* write a word to wishbone */
572 
int dbg_wb_write16(unsigned long adr, unsigned short data) {
573 1246 markom 
  int err;
574 1274 markom 
  data = ntohs(data);
575 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
576 
  if ((err = dbg_command(0x1, adr, 2))) return err;
577 
  if ((err = dbg_go((unsigned char*)&data, 2, 0))) return err;
578 1246 markom 
  return DBG_ERR_OK;
579 
}
580 
 
581 1274 markom 
/* write a word to wishbone */
582 
int dbg_wb_write8(unsigned long adr, unsigned long data) {
583 1246 markom 
  int err;
584 1274 markom 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
585 
  if ((err = dbg_command(0x0, adr, 1))) return err;
586 
  if ((err = dbg_go((unsigned char*)&data, 1, 0))) return err;
587 1246 markom 
  return DBG_ERR_OK;
588 
}
589 
 
590 1274 markom 
/* read a block from wishbone */
591 
int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len) {
592 
  int i, err;
593 
  //printf("%08x %08x\n", adr, len);
594 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
595 
  if ((err = dbg_command(0x6, adr, len))) return err;
596 
  if ((err = dbg_go((unsigned char*)data, len, 1))) return err;
597 
  for (i = 0; i < len / 4; i ++) data[i] = ntohl(data[i]);
598 
  //printf("%08x\n", err);
599 
  return DBG_ERR_OK;
600 1246 markom 
}
601 
 
602 1274 markom 
/* read a block from wishbone */
603 
int dbg_wb_read_block16(unsigned long adr, unsigned short *data, int len) {
604 
  int i, err;
605 
  //printf("%08x %08x\n", adr, len);
606 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
607 
  if ((err = dbg_command(0x5, adr, len))) return err;
608 
  if ((err = dbg_go((unsigned char*)data, len, 1))) return err;
609 
  for (i = 0; i < len / 2; i ++) data[i] = ntohs(data[i]);
610 
  //printf("%08x\n", err);
611 
  return DBG_ERR_OK;
612 1246 markom 
}
613 
 
614 
/* read a block from wishbone */
615 1274 markom 
int dbg_wb_read_block8(unsigned long adr, unsigned char *data, int len) {
616 1259 markom 
  int i, err;
617 
  //printf("%08x %08x\n", adr, len);
618 1274 markom 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
619 
  if ((err = dbg_command(0x4, adr, len))) return err;
620 
  if ((err = dbg_go((unsigned char*)data, len, 1))) return err;
621 1259 markom 
  //printf("%08x\n", err);
622 1274 markom 
  return DBG_ERR_OK;
623 1246 markom 
}
624 
 
625 
/* write a block to wishbone */
626 
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len) {
627 1274 markom 
  int i, err;
628 1259 markom 
  for (i = 0; i < len / 4; i ++) data[i] = ntohl(data[i]);
629 1274 markom 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
630 
  if ((err = dbg_command(0x2, adr, len))) return err;
631 
  if ((err = dbg_go((unsigned char*)data, len, 0))) return err;
632 
  return DBG_ERR_OK;
633 1246 markom 
}
634 
 
635 1274 markom 
/* write a block to wishbone */
636 
int dbg_wb_write_block16(unsigned long adr, unsigned short *data, int len) {
637 
  int i, err;
638 
  for (i = 0; i < len / 2; i ++) data[i] = ntohs(data[i]);
639 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
640 
  if ((err = dbg_command(0x1, adr, len))) return err;
641 
  if ((err = dbg_go((unsigned char*)data, len, 0))) return err;
642 
  return DBG_ERR_OK;
643 
}
644 
 
645 
/* write a block to wishbone */
646 
int dbg_wb_write_block8(unsigned long adr, unsigned char *data, int len) {
647 
  int i, err;
648 
  if ((err = dbg_set_chain(DC_WISHBONE))) return err;
649 
  if ((err = dbg_command(0x0, adr, len))) return err;
650 
  if ((err = dbg_go((unsigned char*)data, len, 0))) return err;
651 
  return DBG_ERR_OK;
652 
}
653 
 
654 1246 markom 
/* read a register from cpu */
655 1274 markom 
int dbg_cpu0_read(unsigned long adr, unsigned long *data) {
656 
  int err;
657 
  if ((err = dbg_set_chain(DC_CPU0))) return err;
658 
  if ((err = dbg_command(0x6, adr, 4))) return err;
659 
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
660 1259 markom 
  *data = ntohl(*data);
661 1274 markom 
  return DBG_ERR_OK;
662 1246 markom 
}
663 
 
664 1274 markom 
/* write a cpu register */
665 
int dbg_cpu0_write(unsigned long adr, unsigned long data) {
666 
  int err;
667 
  data = ntohl(data);
668 
  if ((err = dbg_set_chain(DC_CPU0))) return err;
669 
  if ((err = dbg_command(0x2, adr, 4))) return err;
670 
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
671 
  return DBG_ERR_OK;
672 1246 markom 
}
673 
 
674 1274 markom 
/* read a register from cpu */
675 
int dbg_cpu1_read(unsigned long adr, unsigned long *data) {
676 
  int err;
677 
  if ((err = dbg_set_chain(DC_CPU1))) return err;
678 
  if ((err = dbg_command(0x6, adr, 4))) return err;
679 
  if ((err = dbg_go((unsigned char*)data, 4, 1))) return err;
680 
  *data = ntohl(*data);
681 
  return DBG_ERR_OK;
682 
}
683 
 
684 1246 markom 
/* write a cpu register */
685 1274 markom 
int dbg_cpu1_write(unsigned long adr, unsigned long data) {
686 
  int err;
687 1259 markom 
  data = ntohl(data);
688 1274 markom 
  if ((err = dbg_set_chain(DC_CPU1))) return err;
689 
  if ((err = dbg_command(0x2, adr, 4))) return err;
690 
  if ((err = dbg_go((unsigned char*)&data, 4, 0))) return err;
691 
  return DBG_ERR_OK;
692 1246 markom 
}
693 
 
694 
/* write a cpu module register */
695 1274 markom 
int dbg_cpu1_write_reg(unsigned long adr, unsigned char data) {
696 
  int err;
697 
  if ((err = dbg_set_chain(DC_CPU1))) return err;
698 
  if ((err = dbg_ctrl(data & 2, data &1))) return err;
699 
  return DBG_ERR_OK;
700 1246 markom 
}
701 
 
702 1274 markom 
/* read a register from cpu module */
703 
int dbg_cpu1_read_ctrl(unsigned long adr, unsigned char *data) {
704 
  int err;
705 
  int r, s;
706 
  if ((err = dbg_set_chain(DC_CPU1))) return err;
707 
  if ((err = dbg_ctrl_read(&r, &s))) return err;
708 
  *data = (r << 1) | s;
709 
  return DBG_ERR_OK;
710 
}
711 
 
712 
/* write a cpu module register */
713 
int dbg_cpu0_write_ctrl(unsigned long adr, unsigned char data) {
714 
  int err;
715 
  if ((err = dbg_set_chain(DC_CPU0))) return err;
716 
  if ((err = dbg_ctrl(data & 2, data &1))) return err;
717 
  return DBG_ERR_OK;
718 
}
719 
 
720 
/* read a register from cpu module */
721 
int dbg_cpu0_read_ctrl(unsigned long adr, unsigned char *data) {
722 
  int err;
723 
  int r, s;
724 
  if ((err = dbg_set_chain(DC_CPU0))) return err;
725 
  if ((err = dbg_ctrl_read(&r, &s))) return err;
726 
  *data = (r << 1) | s;
727 
  return DBG_ERR_OK;
728 
}
729 
 
730 1259 markom 
void check(char *fn, int l, int i) {
731 
  if (i != DBG_ERR_OK) {
732 
    fprintf(stderr, "%s:%d: Jtag error %d occured; exiting.\n", fn, l, i);
733 
    exit(1);
734 
  }
735 
}
736 
 
737 1274 markom 
 
738 
void test_sdram (void) {
739 
  unsigned long insn;
740 
  unsigned long i;
741 
  unsigned long data4_out[0x08];
742 
  unsigned long data4_in[0x08];
743 
  unsigned short data2_out[0x10];
744 
  unsigned short data2_in[0x10];
745 
  unsigned char data1_out[0x20];
746 
  unsigned char data1_in[0x20];
747 
 
748 
  printf("Start SDRAM WR\n");
749 
  for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
750 
    //printf("0x%x: 0x%x\n", SDRAM_BASE+i, i);
751 
    CHECK(dbg_wb_write32(SDRAM_BASE+i, i));
752 
  }
753 
 
754 
  printf("Start SDRAM RD\n");
755 
  for (i=0x10; i<(SDRAM_SIZE+SDRAM_BASE); i=i<<1) {
756 
    CHECK(dbg_wb_read32(SDRAM_BASE+i, &insn));
757 
    //printf("0x%x: 0x%x\n", SDRAM_BASE+i, insn);
758 
    if (i != insn) {
759 
      printf("SDRAM not OK");
760 
      exit (1);
761 
    }
762 
  }
763 
 
764 
  printf("32-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
765 
  for (i=0; i<(0x20/4); i++) {
766 
    data4_out[i] = data4_in[i] = ((4*i+3)<<24) | ((4*i+2)<<16) | ((4*i+1)<<8) | (4*i);
767 
    //printf("data_out = %0x\n", data4_out[i]);
768 
  }
769 
 
770 
  //printf("Press a key for write\n"); getchar();
771 
  CHECK(dbg_wb_write_block32(SDRAM_BASE, &data4_out[0], 0x20));
772 
 
773 
  // 32-bit block read is used for checking
774 
  printf("32-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
775 
  CHECK(dbg_wb_read_block32(SDRAM_BASE, &data4_out[0], 0x20));
776 
  for (i=0; i<(0x20/4); i++) {
777 
    //printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
778 
    if (data4_in[i] != data4_out[i]) {
779 
      printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data4_in[i], data4_out[i]);
780 
      exit(1);
781 
    }
782 
  }
783 
 
784 
  printf("16-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
785 
  for (i=0; i<(0x20/2); i++) {
786 
    data2_out[i] = data2_in[i] = ((4*i+1)<<8) | (4*i);
787 
    //printf("data_out = %0x\n", data_out[i]);
788 
  }
789 
  CHECK(dbg_wb_write_block16(SDRAM_BASE, &data2_out[0], 0x20));
790 
 
791 
  // 16-bit block read is used for checking
792 
  printf("16-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
793 
  CHECK(dbg_wb_read_block16(SDRAM_BASE, &data2_out[0], 0x20));
794 
  for (i=0; i<(0x20/2); i++) {
795 
    //printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
796 
    if (data2_in[i] != data2_out[i]) {
797 
      printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data2_in[i], data2_out[i]);
798 
      exit(1);
799 
    }
800 
  }
801 
 
802 
  printf("8-bit block write from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
803 
  for (i=0; i<(0x20/1); i++) {
804 
    data1_out[i] = data1_in[i] = (4*i);
805 
    //printf("data_out = %0x\n", data_out[i]);
806 
  }
807 
  CHECK(dbg_wb_write_block8(SDRAM_BASE, &data1_out[0], 0x20));
808 
 
809 
  // 32-bit block read is used for checking
810 
  printf("8-bit block read from %x to %x\n", SDRAM_BASE, SDRAM_BASE + 0x20);
811 
  CHECK(dbg_wb_read_block8(SDRAM_BASE, &data1_out[0], 0x20));
812 
  for (i=0; i<(0x20/1); i++) {
813 
    //printf("0x%x: 0x%x\n", SDRAM_BASE+(i*4), data_out[i]);
814 
    if (data1_in[i] != data1_out[i]) {
815 
      printf("SDRAM data differs. Expected: 0x%0x, read: 0x%0x\n", data1_in[i], data1_out[i]);
816 
      exit(1);
817 
    }
818 
  }
819 
}
820 
 
821 
 
822 1246 markom 
void dbg_test() {
823 
  int i;
824 
  unsigned long npc, ppc, r1, insn, result;
825 1259 markom 
  unsigned char stalled;
826 
#if 1
827 
#define MC_BASE_ADDR     0x93000000
828 
#define FLASH_BASE_ADDR  0xf0000000
829 
#define FLASH_BAR_VAL    FLASH_BASE_ADDR
830 
#define FLASH_AMR_VAL    0xf0000000
831 
#define FLASH_WTR_VAL    0x00011009
832 
#define FLASH_RTR_VAL    0x01002009
833 
#define SDRAM_BASE_ADDR  0x00000000
834 
#define SDRAM_BAR_VAL    SDRAM_BASE_ADDR
835 1274 markom 
//#define SDRAM_SIZE       0x04000000  defined at the start of this program
836 1259 markom 
#define SDRAM_AMR_VAL    (~(SDRAM_SIZE -1))
837 
#define SDRAM_RATR_VAL   0x00000006
838 
#define SDRAM_RCDR_VAL   0x00000002
839 
#define SDRAM_RCTR_VAL   0x00000006
840 
#define SDRAM_REFCTR_VAL 0x00000006
841 
#define SDRAM_PTR_VAL    0x00000001
842 
#define SDRAM_RRDR_VAL   0x00000000
843 
#define SDRAM_RIR_VAL    0x000000C0
844 1246 markom 
 
845 1259 markom 
#define MC_BAR_0         0x00
846 
#define MC_AMR_0         0x04
847 
#define MC_WTR_0         0x30
848 
#define MC_RTR_0         0x34
849 
#define MC_OSR           0xe8
850 1274 markom 
#define MC_BAR_1         0x08
851 1259 markom 
#define MC_BAR_4         0x80
852 1274 markom 
#define MC_AMR_1         0x0c
853 1259 markom 
#define MC_AMR_4         0x84
854 1274 markom 
#define MC_CCR_1         0x24
855 1259 markom 
#define MC_CCR_4         0xa0
856 
#define MC_RATR          0xb0
857 
#define MC_RCDR          0xc8
858 
#define MC_RCTR          0xb4
859 
#define MC_REFCTR        0xc4
860 
#define MC_PTR           0xbc
861 
#define MC_RRDR          0xb8
862 
#define MC_RIR           0xcc
863 
#define MC_ORR           0xe4
864 
 
865 1274 markom 
  //usleep(1000000);
866 1246 markom 
 
867 1274 markom 
  printf("Stall 8051\n");
868 
  CHECK(dbg_cpu1_write_reg(0, 0x01)); // stall 8051
869 
 
870 
  printf("Stall or1k\n");
871 
  CHECK(dbg_cpu0_write_ctrl(0, 0x01));      // stall or1k
872 
 
873 
  CHECK(dbg_cpu1_read_ctrl(0, &stalled));
874 
  if (!(stalled & 0x1)) {
875 
    printf("8051 should be stalled\n");   // check stall 8051
876 
    exit(1);
877 
  }
878 
 
879 
  CHECK(dbg_cpu0_read_ctrl(0, &stalled));
880 
  if (!(stalled & 0x1)) {
881 
    printf("or1k should be stalled\n");   // check stall or1k
882 
    exit(1);
883 
  }
884 
 
885 
  printf("Initialize Memory Controller\n");
886 1259 markom 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_0, FLASH_BAR_VAL & 0xffff0000));
887 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_0, FLASH_AMR_VAL & 0xffff0000));
888 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_WTR_0, FLASH_WTR_VAL));
889 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RTR_0, FLASH_RTR_VAL));
890 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x40000000));
891 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_4, SDRAM_BAR_VAL & 0xffff0000));
892 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_4, SDRAM_AMR_VAL & 0xffff0000));
893 1274 markom 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0x00bf0005));
894 1259 markom 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RATR, SDRAM_RATR_VAL));
895 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RCDR, SDRAM_RCDR_VAL));
896 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RCTR, SDRAM_RCTR_VAL));
897 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_REFCTR, SDRAM_REFCTR_VAL));
898 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_PTR, SDRAM_PTR_VAL));
899 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RRDR, SDRAM_RRDR_VAL));
900 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_RIR, SDRAM_RIR_VAL));
901 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x5e000000));
902 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x5e000000));
903 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x6e000000));
904 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
905 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
906 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
907 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
908 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
909 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
910 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
911 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x6e000000));
912 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_OSR, 0x7e000033));
913 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_ORR, 0x7e000033));
914 1274 markom 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_4, 0xc0bf0005));
915 1259 markom 
 
916 
  CHECK(dbg_wb_read32(MC_BASE_ADDR+MC_CCR_4, &insn));
917 1274 markom 
  printf("expected %x, read %x\n", 0xc0bf0005, insn);
918 
 
919 
  // SRAM initialized to 0x40000000
920 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_BAR_1, SRAM_BASE & 0xffff0000));
921 1277 markom 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_AMR_1, ~(SRAM_SIZE - 1) & 0xffff0000));
922 1274 markom 
  CHECK(dbg_wb_write32(MC_BASE_ADDR + MC_CCR_1, 0xc020001f));
923 1259 markom 
#endif
924 1246 markom 
 
925 1259 markom 
#if 1
926 
#define CPU_OP_ADR  0
927 
#define CPU_SEL_ADR 1
928 1246 markom 
 
929 1259 markom 
  /* unstall the or1200 in highland_sys */
930 1274 markom 
  printf("Unstall or1k\n");
931 1259 markom 
  CHECK(dbg_wb_write32(0xb8070000, 2));
932 1246 markom 
 
933 1274 markom 
  CHECK(dbg_cpu1_read_ctrl(0, &stalled));
934 
  if (!(stalled & 0x1)) {
935 
    printf("8051 should be stalled\n");   // check stall 8051
936 
    exit(1);
937 
  }
938 
 
939 
  printf("Stall or1k\n");
940 
  CHECK(dbg_cpu0_write_ctrl(0, 0x01));         // stall or1k
941 
 
942 
  printf("SDRAM test: \n");
943 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0x12345678));
944 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x00, &insn));
945 1259 markom 
  printf("expected %x, read %x\n", 0x12345678, insn);
946 
  if (insn != 0x12345678) exit(1);
947 1274 markom 
 
948 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0000, 0x11112222));
949 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
950 
  printf("expected %x, read %x\n", 0x11112222, insn);
951 
  if (insn != 0x11112222) exit(1);
952 1246 markom 
 
953 1274 markom 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0004, 0x33334444));
954 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0008, 0x55556666));
955 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x000c, 0x77778888));
956 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0010, 0x9999aaaa));
957 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0014, 0xbbbbcccc));
958 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0018, 0xddddeeee));
959 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x001c, 0xffff0000));
960 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0020, 0xdeadbeef));
961 
 
962 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0000, &insn));
963 1259 markom 
  printf("expected %x, read %x\n", 0x11112222, insn);
964 1274 markom 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0004, &insn));
965 
  printf("expected %x, read %x\n", 0x33334444, insn);
966 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0008, &insn));
967 
  printf("expected %x, read %x\n", 0x55556666, insn);
968 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x000c, &insn));
969 
  printf("expected %x, read %x\n", 0x77778888, insn);
970 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0010, &insn));
971 
  printf("expected %x, read %x\n", 0x9999aaaa, insn);
972 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0014, &insn));
973 
  printf("expected %x, read %x\n", 0xbbbbcccc, insn);
974 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0018, &insn));
975 
  printf("expected %x, read %x\n", 0xddddeeee, insn);
976 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x001c, &insn));
977 
  printf("expected %x, read %x\n", 0xffff0000, insn);
978 
  CHECK(dbg_wb_read32(SDRAM_BASE+0x0020, &insn));
979 
  printf("expected %x, read %x\n", 0xdeadbeef, insn);
980 
 
981 
  if (insn != 0xdeadbeef) {
982 
    printf("SDRAM test failed !!!\n");
983 
    exit(1);
984 
  }
985 
    else
986 
    printf("SDRAM test passed\n");
987 
 
988 
  printf("SRAM test: \n");
989 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0000, 0x11112222));
990 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0004, 0x33334444));
991 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0008, 0x55556666));
992 
  CHECK(dbg_wb_write32(SRAM_BASE+0x000c, 0x77778888));
993 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0010, 0x9999aaaa));
994 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0014, 0xbbbbcccc));
995 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0018, 0xddddeeee));
996 
  CHECK(dbg_wb_write32(SRAM_BASE+0x001c, 0xffff0000));
997 
  CHECK(dbg_wb_write32(SRAM_BASE+0x0020, 0xdedababa));
998 1259 markom 
 
999 1274 markom 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0000, &insn));
1000 
  printf("expected %x, read %x\n", 0x11112222, insn);
1001 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0004, &insn));
1002 1259 markom 
  printf("expected %x, read %x\n", 0x33334444, insn);
1003 1274 markom 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0008, &insn));
1004 1259 markom 
  printf("expected %x, read %x\n", 0x55556666, insn);
1005 1274 markom 
  CHECK(dbg_wb_read32(SRAM_BASE+0x000c, &insn));
1006 1259 markom 
  printf("expected %x, read %x\n", 0x77778888, insn);
1007 1274 markom 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0010, &insn));
1008 1259 markom 
  printf("expected %x, read %x\n", 0x9999aaaa, insn);
1009 1274 markom 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0014, &insn));
1010 1259 markom 
  printf("expected %x, read %x\n", 0xbbbbcccc, insn);
1011 1274 markom 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0018, &insn));
1012 1259 markom 
  printf("expected %x, read %x\n", 0xddddeeee, insn);
1013 1274 markom 
  CHECK(dbg_wb_read32(SRAM_BASE+0x001c, &insn));
1014 1259 markom 
  printf("expected %x, read %x\n", 0xffff0000, insn);
1015 1274 markom 
  CHECK(dbg_wb_read32(SRAM_BASE+0x0020, &insn));
1016 
  printf("expected %x, read %x\n", 0xdedababa, insn);
1017 
 
1018 
  if (insn != 0xdedababa) {
1019 
    printf("SRAN test failed!!!\n");
1020 
    exit(1);
1021 
  }
1022 
    else
1023 
    printf("SRAM test passed\n");
1024 1246 markom 
 
1025 1274 markom 
  #if 1
1026 
    test_sdram();
1027 
  #endif
1028 1246 markom 
 
1029 1274 markom 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x00, 0xe0000005));   /* l.xor   r0,r0,r0   */
1030 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x04, 0x9c200000));   /* l.addi  r1,r0,0x0  */
1031 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x08, 0x18400000));   /* l.movhi r2,0x4000  */
1032 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x0c, 0xa8420030));   /* l.ori   r2,r2,0x30 */
1033 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x10, 0x9c210001));   /* l.addi  r1,r1,1    */
1034 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x14, 0x9c210001));   /* l.addi  r1,r1,1    */
1035 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x18, 0xd4020800));   /* l.sw    0(r2),r1   */
1036 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x1c, 0x9c210001));   /* l.addi  r1,r1,1    */
1037 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x20, 0x84620000));   /* l.lwz   r3,0(r2)   */
1038 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x24, 0x03fffffb));   /* l.j     loop2      */
1039 
  CHECK(dbg_wb_write32(SDRAM_BASE+0x28, 0xe0211800));   /* l.add   r1,r1,r3   */
1040 1259 markom 
 
1041 1274 markom 
  CHECK(dbg_cpu0_write((0 << 11) + 17, 0x01));  /* Enable exceptions */
1042 
  CHECK(dbg_cpu0_write((6 << 11) + 20, 0x2000));  /* Trap causes stall */
1043 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE));  /* Set PC */
1044 
  CHECK(dbg_cpu0_write((6 << 11) + 16, 1 << 22));  /* Set step bit */
1045 1259 markom 
  for(i = 0; i < 11; i++) {
1046 1274 markom 
    CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* 11x Unstall */
1047 
    do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1048 1259 markom 
  }
1049 
 
1050 1274 markom 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1051 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1052 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1053 1246 markom 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1054 1259 markom 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 5);
1055 1246 markom 
  result = npc + ppc + r1;
1056 
 
1057 1274 markom 
  CHECK(dbg_cpu0_write((6 << 11) + 16, 0));  /* Reset step bit */
1058 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x28, &insn));  /* Set trap insn in delay slot */
1059 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, 0x21000001));
1060 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1061 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1062 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1063 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1064 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1065 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x28, insn));  /* Set back original insn */
1066 1246 markom 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1067 1259 markom 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 8);
1068 1246 markom 
  result = npc + ppc + r1 + result;
1069 
 
1070 1274 markom 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x24, &insn));  /* Set trap insn in place of branch insn */
1071 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, 0x21000001));
1072 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x10));  /* Set PC */
1073 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1074 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1075 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1076 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1077 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1078 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x24, insn));  /* Set back original insn */
1079 1246 markom 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1080 1259 markom 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000028, 0x00000024, 11);
1081 1246 markom 
  result = npc + ppc + r1 + result;
1082 
 
1083 1274 markom 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn));  /* Set trap insn before branch insn */
1084 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
1085 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x24));  /* Set PC */
1086 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1087 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1088 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1089 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1090 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1091 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn));  /* Set back original insn */
1092 1246 markom 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1093 1259 markom 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000024, 0x00000020, 24);
1094 1246 markom 
  result = npc + ppc + r1 + result;
1095 
 
1096 1274 markom 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x1c, &insn));  /* Set trap insn behind lsu insn */
1097 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, 0x21000001));
1098 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x20));  /* Set PC */
1099 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1100 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1101 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1102 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1103 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1104 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x1c, insn));  /* Set back original insn */
1105 1246 markom 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1106 1259 markom 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000020, 0x0000001c, 49);
1107 1246 markom 
  result = npc + ppc + r1 + result;
1108 
 
1109 1274 markom 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x20, &insn));  /* Set trap insn very near previous one */
1110 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, 0x21000001));
1111 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x1c));  /* Set PC */
1112 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1113 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1114 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1115 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1116 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1117 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x20, insn));  /* Set back original insn */
1118 1246 markom 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1119 1259 markom 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000024, 0x00000020, 50);
1120 1246 markom 
  result = npc + ppc + r1 + result;
1121 
 
1122 1274 markom 
  CHECK(dbg_wb_read32(SDRAM_BASE + 0x10, &insn));  /* Set trap insn to the start */
1123 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, 0x21000001));
1124 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x20)  /* Set PC */);
1125 
  CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1126 
  do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1127 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1128 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1129 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1130 
  CHECK(dbg_wb_write32(SDRAM_BASE + 0x10, insn));  /* Set back original insn */
1131 1246 markom 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1132 1259 markom 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000014, 0x00000010, 99);
1133 1246 markom 
  result = npc + ppc + r1 + result;
1134 
 
1135 1274 markom 
  CHECK(dbg_cpu0_write((6 << 11) + 16, 1 << 22));  /* Set step bit */
1136 1259 markom 
  for(i = 0; i < 5; i++) {
1137 1274 markom 
    CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1138 
    do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1139 1259 markom 
  }
1140 1274 markom 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1141 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1142 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1143 1246 markom 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1144 1259 markom 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000028, 0x00000024, 101);
1145 1246 markom 
  result = npc + ppc + r1 + result;
1146 
 
1147 1274 markom 
  CHECK(dbg_cpu0_write((0 << 11) + 16, SDRAM_BASE + 0x24));  /* Set PC */
1148 1259 markom 
  for(i = 0; i < 2; i++) {
1149 1274 markom 
    CHECK(dbg_cpu0_write_ctrl(CPU_OP_ADR, 0x00));  /* Unstall */
1150 
    do CHECK(dbg_cpu0_read_ctrl(CPU_OP_ADR, &stalled)); while (!(stalled & 1));
1151 1259 markom 
  }
1152 1274 markom 
  CHECK(dbg_cpu0_read((0 << 11) + 16, &npc));  /* Read NPC */
1153 
  CHECK(dbg_cpu0_read((0 << 11) + 18, &ppc));  /* Read PPC */
1154 
  CHECK(dbg_cpu0_read(0x401, &r1));  /* Read R1 */
1155 1246 markom 
  printf("Read      npc = %.8lx ppc = %.8lx r1 = %.8lx\n", npc, ppc, r1);
1156 1259 markom 
  printf("Expected  npc = %.8lx ppc = %.8lx r1 = %.8lx\n", 0x00000010, 0x00000028, 201);
1157 1246 markom 
  result = npc + ppc + r1 + result;
1158 1274 markom 
  printf("result = %.8lx\n", result ^ 0xdeaddae1);
1159 1246 markom 
 
1160 1274 markom 
 
1161 
  { // 8051 TEST
1162 
    unsigned long npc[3], tmp;
1163 
 
1164 
    // WRITE ACC
1165 
    CHECK(dbg_cpu1_write(0x20e0, 0xa6));
1166 
 
1167 
    // READ ACC
1168 
    CHECK(dbg_cpu1_read(0x20e0, &tmp));   // select SFR space
1169 
    printf("Read  8051   ACC = %0x (expected a6)\n", tmp);
1170 
    result = result + tmp;
1171 
 
1172 
    // set exception to single step to jump over a loop
1173 
    CHECK(dbg_cpu1_write(0x3010, 0xa0)); // set single step and global enable in EER
1174 
    CHECK(dbg_cpu1_write(0x3011, 0x40)); // set evec = 24'h000040
1175 
    CHECK(dbg_cpu1_write(0x3012, 0x00)); // (already reset value)
1176 
    CHECK(dbg_cpu1_write(0x3013, 0x00)); // (already reset value)
1177 
 
1178 
    // set HW breakpoint at PC == 0x41
1179 
    CHECK(dbg_cpu1_write(0x3020, 0x41)); // DVR0 = 24'h000041
1180 
    CHECK(dbg_cpu1_write(0x3023, 0x39)); // DCR0 = valid, == PC
1181 
    CHECK(dbg_cpu1_write(0x3001, 0x04)); // DSR = watchpoint
1182 
 
1183 
    // flush 8051 instruction cache
1184 
    CHECK(dbg_cpu1_write(0x209f, 0x00));
1185 
 
1186 
    // Put some instructions in ram (8-bit mode on wishbone)
1187 
    CHECK(dbg_wb_write8 (0x40, 0x04));  // inc a
1188 
    CHECK(dbg_wb_write8 (0x41, 0x03));  // rr a;
1189 
    CHECK(dbg_wb_write8 (0x42, 0x14));  // dec a;
1190 
    CHECK(dbg_wb_write8 (0x43, 0xf5));  // mov 0e5h, a;
1191 
    CHECK(dbg_wb_write8 (0x44, 0xe5));
1192 
 
1193 
    // unstall just 8051
1194 
    CHECK(dbg_cpu1_write_reg(0, 0));
1195 
 
1196 
    // read PC
1197 
    CHECK(dbg_cpu1_read(0, &npc[0]));
1198 
    CHECK(dbg_cpu1_read(1, &npc[1]));
1199 
    CHECK(dbg_cpu1_read(2, &npc[2]));
1200 
    printf("Read  8051   npc = %02x%02x%02x (expected 41)\n", npc[2], npc[1], npc[0]);
1201 
    result = result + (npc[2] << 16) + (npc[1] << 8) + npc[0];
1202 
 
1203 
    // READ ACC
1204 
    CHECK(dbg_cpu1_read(0x20e0, &tmp));   // select SFR space
1205 
    printf("Read  8051   ACC = %0x (expected a7)\n", tmp);
1206 
    result = result + tmp;
1207 
 
1208 
    // set sigle step to stop execution
1209 
    CHECK(dbg_cpu1_write(0x3001, 0x20)); // set single step and global enable in DSR
1210 
 
1211 
    // clear DRR
1212 
    CHECK(dbg_cpu1_write(0x3000, 0x00)); // set single step and global enable in DRR
1213 
 
1214 
    // unstall just 8051
1215 
    CHECK(dbg_cpu1_write_reg(0, 0));
1216 
 
1217 
    // read PC
1218 
    CHECK(dbg_cpu1_read(0, &npc[0]));
1219 
    CHECK(dbg_cpu1_read(1, &npc[1]));
1220 
    CHECK(dbg_cpu1_read(2, &npc[2]));
1221 
    printf("Read  8051   npc = %02x%02x%02x (expected 42)\n", npc[2], npc[1], npc[0]);
1222 
    result = result + (npc[2] << 16) + (npc[1] << 8) + npc[0];
1223 
 
1224 
    // READ ACC
1225 
    CHECK(dbg_cpu1_read(0x20e0, &tmp));   // select SFR space
1226 
    printf("Read  8051   ACC = %0x (expected d3)\n", tmp);
1227 
    result = result + tmp;
1228 
 
1229 
    printf("report (%x)\n", result ^ 0x6c1 ^ 0xdeaddead);
1230 
  }
1231 1246 markom 
#endif
1232 
}
1233 
 
1234 
int main(int argc,  char *argv[]) {
1235 
  char *redirstr;
1236 
  int trace_fd = 0;
1237 
  char *s;
1238 
  int err = DBG_ERR_OK;
1239 
 
1240 
  srand(getpid());
1241 
  if(argc != 2) {
1242 
    printf("JTAG protocol via parallel port for linux.\n");
1243 
    printf("Copyright(C) 2001 Marko Mlinar, markom@opencores.org\n\n");
1244 
    printf("Usage: %s JTAG port_number\n", argv[0]);
1245 
    return -1;
1246 
  }
1247 
 
1248 
#ifndef RTL_SIM
1249 
  if(ioperm(LPT_BASE, 3, 1)) {
1250 
    fprintf(stderr, "Couldn't get the port at %x\n", LPT_BASE);
1251 
    perror("Root privileges are required.\n");
1252 
    return -1;
1253 
  }
1254 
  printf("Using parallel port at %x\n", LPT_BASE);
1255 
#else
1256 
  {
1257 
    FILE *fin = fopen(GDB_IN, "wt+");
1258 
    if(fin == 0) {
1259 
      fprintf(stderr, "Can not open %s\n", GDB_IN);
1260 
      exit(1);
1261 
    }
1262 
    fclose(fin);
1263 
 
1264 
  }
1265 
#endif
1266 
#ifndef RTL_SIM
1267 
  /* Get rid of root privileges.  */
1268 
  setreuid(getuid(), getuid());
1269 
#endif
1270 
 
1271 
  /* Initialize a new connection to the or1k board, and make sure we are
1272 
     really connected.  */
1273 
  current_chain = -1;
1274 
  if ((err = dbg_reset())) goto error;
1275 
 
1276 
  /* Test the connection.  */
1277 
  dbg_test();
1278 
 
1279 
  /* We have a connection.  Establish server.  */
1280 
  argv++; argc--;
1281 
  printf("Dropping root privileges.\n");
1282 
  serverPort = strtol(*(argv),&s,10);
1283 
  if(*s) return -1;
1284 
  argv++; argc--;
1285 
 
1286 
  if(server_fd = GetServerSocket("or1ksim","tcp", serverPort)) {
1287 
    printf("JTAG Proxy server started on port %d\n", serverPort);
1288 
    printf("Press CTRL+c to exit.\n");
1289 
  } else {
1290 
    fprintf(stderr,"Cannot start JTAG Proxy server on port %d\n", serverPort);
1291 
    exit(-1);
1292 
  }
1293 
 
1294 
  /* Do endless loop of checking and handle GDB requests.  Ctrl-c exits.  */
1295 
  HandleServerSocket(true);
1296 
  return 0;
1297 
error:
1298 
  fprintf(stderr,"Connection with jtag via parallel port failed (err = %d).\n", err);
1299 
  exit(-1);
1300 
}
1301 
 

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