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[/] [or1k/] [trunk/] [jtag/] [jp2.h] - Blame information for rev 1246

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#ifndef _JP2_H_
#define _JP2_H_
 
#define Boolean int
#define false 0
#define true 1
 
#define GDB_IN "../sim/rtl_sim/run/gdb_in.dat"
#define GDB_OUT "../sim/rtl_sim/run/gdb_out.dat"
 
#ifdef DEBUG
#define debug printf
#else
#define debug
#endif
 
#ifdef DEBUG2
#define debug2 printf
#else
#define debug2
#endif
 
#if (DEBUG) || (DEBUG2)
#define flush_debug() fflush(stdout)
#else
#define flush_debug()
#endif
 
#define LPT_BASE (base)
#define LPT_READ (LPT_BASE+1)
#define LPT_WRITE LPT_BASE
#if RTL_SIM
#define TCLK_BIT (0x01) /* D0, pin #2 */
#define TRST_BIT (0x02) /* D1, pin #3 */
#define TDI_BIT  (0x04) /* D2, pin #4 */
#define TMS_BIT  (0x08) /* D0, pin #5 */
#define TDO_BIT  (0x20) /* PE, pin #12 */
#define TMS      (0x02)
#define TDI      (0x01)
#else
#ifdef XILINX_PARALLEL_CABLE_III
#define TCLK_BIT (0x02) /* D1 pin 3 */
#define TRST_BIT (0x10) /* Not used */
#define TDI_BIT  (0x01) /* D0 pin 2 */
#define TMS_BIT  (0x04) /* D2 pin 4 */
#define TDO_BIT  (0x10) /* S6 pin 13*/
#define TMS      (0x02)
#define TDI      (0x01)
#else
#ifdef XESS_PARALLEL_CABLE
#define TCLK_BIT (0x04) /* D2 pin 4 */
#define TRST_BIT (0x08) /* D3 pin 5 */
#define TDI_BIT  (0x10) /* D4 pin 6 */
#define TMS_BIT  (0x20) /* D5 pin 7 */
#define TDO_BIT  (0x20) /* S5 pin 12*/
#define TMS      (0x02)
#define TDI      (0x01)
#endif
#endif
#endif
 
#ifdef RTL_SIM
# define JTAG_WAIT() usleep(1000)
# define JTAG_RETRY_WAIT() usleep (1000)
#else
# define JTAG_WAIT() {      \
  int i;        \
  volatile int j;   \
  for(i = 0; i < 1000; i++) \
    j = i;      \
  }
# define JTAG_RETRY_WAIT() usleep (1000)
#endif
 
/* Selects crc trailer size in bits. Currently supported: 8 */
#define CRC_SIZE (8)
 
/* Scan chain size in bits.  */
#define SC_SIZE (4)
 
#ifndef ULONGEST
#define ULONGEST unsigned long
#endif
 
extern unsigned int serverPort;
extern unsigned int server_fd;
extern void HandleServerSocket(Boolean block);
 
extern int err;
extern void JTAGRequest(void);
extern void GDBRequest(void);
 
/* read a word from wishbone */
int dbg_wb_read32(unsigned long adr, unsigned long *data);
 
/* write a word to wishbone */
int dbg_wb_write32(unsigned long adr, unsigned long data);
 
/* read a block from wishbone */
int dbg_wb_read_block_32(unsigned long adr, unsigned long *data, int len);
 
/* write a block to wishbone */
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len);
 
/* read a register from cpu */
int dbg_cpu_read32(unsigned long adr, unsigned long *data);
 
/* read a register from cpu module */
int dbg_cpu_read_reg(unsigned long adr, unsigned long *data);
 
/* write a cpu register */
int dbg_cpu_write32(unsigned long adr, unsigned long data);
 
/* write a cpu module register */
int dbg_cpu_write_reg(unsigned long adr, unsigned long data);
 
 
#define DC_SIZE           3
#define DC_STATUS_SIZE    4
 
#define DC_CPU            0
#define DC_WISHBONE       1
 
#define DI_WB_STATUS      0
#define DI_WB_WRITE8      1
#define DI_WB_WRITE16     2
#define DI_WB_WRITE32     3
#define DI_WB_GO          4
#define DI_WB_READ8       5
#define DI_WB_READ16      6
#define DI_WB_READ32      7
 
#define DI_CPU_WRITE8     1
#define DI_CPU_WRITE32    2
#define DI_CPU_WRITE_REG  3
#define DI_CPU_GO         4
#define DI_CPU_READ8      5
#define DI_CPU_READ32     6
#define DI_CPU_READ_REG   7
 
#define DBG_CRC_SIZE      32
#define DBG_CRC_POLY      0x04c11db7
 
#define DBG_ERR_OK        0
#define DBG_ERR_CRC       1
#define DBG_ERR_INV_CHAIN 2
#define DBG_ERR_BUSERR    3
 
#define NUM_SOFT_RETRIES  3
#define NUM_HARD_RETRIES  3
#define NUM_ACCESS_RETRIES 10
 
#endif /* _JP2_H_ */
 

Line No.	Rev	Author	Line
1	1246	markom	`#ifndef _JP2_H_`
2			`#define _JP2_H_`
3
4			`#define Boolean int`
5			`#define false 0`
6			`#define true 1`
7
8			`#define GDB_IN "../sim/rtl_sim/run/gdb_in.dat"`
9			`#define GDB_OUT "../sim/rtl_sim/run/gdb_out.dat"`
10
11			`#ifdef DEBUG`
12			`#define debug printf`
13			`#else`
14			`#define debug`
15			`#endif`
16
17			`#ifdef DEBUG2`
18			`#define debug2 printf`
19			`#else`
20			`#define debug2`
21			`#endif`
22
23			`#if (DEBUG) \|\| (DEBUG2)`
24			`#define flush_debug() fflush(stdout)`
25			`#else`
26			`#define flush_debug()`
27			`#endif`
28
29			`#define LPT_BASE (base)`
30			`#define LPT_READ (LPT_BASE+1)`
31			`#define LPT_WRITE LPT_BASE`
32			`#if RTL_SIM`
33			`#define TCLK_BIT (0x01) /* D0, pin #2 */`
34			`#define TRST_BIT (0x02) /* D1, pin #3 */`
35			`#define TDI_BIT (0x04) /* D2, pin #4 */`
36			`#define TMS_BIT (0x08) /* D0, pin #5 */`
37			`#define TDO_BIT (0x20) /* PE, pin #12 */`
38			`#define TMS (0x02)`
39			`#define TDI (0x01)`
40			`#else`
41			`#ifdef XILINX_PARALLEL_CABLE_III`
42			`#define TCLK_BIT (0x02) /* D1 pin 3 */`
43			`#define TRST_BIT (0x10) /* Not used */`
44			`#define TDI_BIT (0x01) /* D0 pin 2 */`
45			`#define TMS_BIT (0x04) /* D2 pin 4 */`
46			`#define TDO_BIT (0x10) /* S6 pin 13*/`
47			`#define TMS (0x02)`
48			`#define TDI (0x01)`
49			`#else`
50			`#ifdef XESS_PARALLEL_CABLE`
51			`#define TCLK_BIT (0x04) /* D2 pin 4 */`
52			`#define TRST_BIT (0x08) /* D3 pin 5 */`
53			`#define TDI_BIT (0x10) /* D4 pin 6 */`
54			`#define TMS_BIT (0x20) /* D5 pin 7 */`
55			`#define TDO_BIT (0x20) /* S5 pin 12*/`
56			`#define TMS (0x02)`
57			`#define TDI (0x01)`
58			`#endif`
59			`#endif`
60			`#endif`
61
62			`#ifdef RTL_SIM`
63			`# define JTAG_WAIT() usleep(1000)`
64			`# define JTAG_RETRY_WAIT() usleep (1000)`
65			`#else`
66			`# define JTAG_WAIT() { \`
67			`int i; \`
68			`volatile int j; \`
69			`for(i = 0; i < 1000; i++) \`
70			`j = i; \`
71			`}`
72			`# define JTAG_RETRY_WAIT() usleep (1000)`
73			`#endif`
74
75			`/* Selects crc trailer size in bits. Currently supported: 8 */`
76			`#define CRC_SIZE (8)`
77
78			`/* Scan chain size in bits. */`
79			`#define SC_SIZE (4)`
80
81			`#ifndef ULONGEST`
82			`#define ULONGEST unsigned long`
83			`#endif`
84
85			`extern unsigned int serverPort;`
86			`extern unsigned int server_fd;`
87			`extern void HandleServerSocket(Boolean block);`
88
89			`extern int err;`
90			`extern void JTAGRequest(void);`
91			`extern void GDBRequest(void);`
92
93			`/* read a word from wishbone */`
94			`int dbg_wb_read32(unsigned long adr, unsigned long *data);`
95
96			`/* write a word to wishbone */`
97			`int dbg_wb_write32(unsigned long adr, unsigned long data);`
98
99			`/* read a block from wishbone */`
100			`int dbg_wb_read_block_32(unsigned long adr, unsigned long *data, int len);`
101
102			`/* write a block to wishbone */`
103			`int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len);`
104
105			`/* read a register from cpu */`
106			`int dbg_cpu_read32(unsigned long adr, unsigned long *data);`
107
108			`/* read a register from cpu module */`
109			`int dbg_cpu_read_reg(unsigned long adr, unsigned long *data);`
110
111			`/* write a cpu register */`
112			`int dbg_cpu_write32(unsigned long adr, unsigned long data);`
113
114			`/* write a cpu module register */`
115			`int dbg_cpu_write_reg(unsigned long adr, unsigned long data);`
116
117
118			`#define DC_SIZE 3`
119			`#define DC_STATUS_SIZE 4`
120
121			`#define DC_CPU 0`
122			`#define DC_WISHBONE 1`
123
124			`#define DI_WB_STATUS 0`
125			`#define DI_WB_WRITE8 1`
126			`#define DI_WB_WRITE16 2`
127			`#define DI_WB_WRITE32 3`
128			`#define DI_WB_GO 4`
129			`#define DI_WB_READ8 5`
130			`#define DI_WB_READ16 6`
131			`#define DI_WB_READ32 7`
132
133			`#define DI_CPU_WRITE8 1`
134			`#define DI_CPU_WRITE32 2`
135			`#define DI_CPU_WRITE_REG 3`
136			`#define DI_CPU_GO 4`
137			`#define DI_CPU_READ8 5`
138			`#define DI_CPU_READ32 6`
139			`#define DI_CPU_READ_REG 7`
140
141			`#define DBG_CRC_SIZE 32`
142			`#define DBG_CRC_POLY 0x04c11db7`
143
144			`#define DBG_ERR_OK 0`
145			`#define DBG_ERR_CRC 1`
146			`#define DBG_ERR_INV_CHAIN 2`
147			`#define DBG_ERR_BUSERR 3`
148
149			`#define NUM_SOFT_RETRIES 3`
150			`#define NUM_HARD_RETRIES 3`
151			`#define NUM_ACCESS_RETRIES 10`
152
153			`#endif /* _JP2_H_ */`
154

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[/] [or1k/] [trunk/] [jtag/] [jp2.h] - Blame information for rev 1246