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#ifndef _JP2_H_

#define _JP2_H_

//#define DEBUG 1

//#define DEBUG2 1

#define Boolean int

#define false 0

#define true 1

#define GDB_IN "../sim/rtl_sim/run/gdb_in.dat"

#define GDB_OUT "../sim/rtl_sim/run/gdb_out.dat"

#ifdef DEBUG

#define debug printf

#else

#define debug

#endif

#ifdef DEBUG2

#define debug2 printf

#else

#define debug2

#endif

#if (DEBUG) || (DEBUG2)

#define flush_debug() fflush(stdout)

#else

#define flush_debug()

#endif

#define LPT_BASE (base)

#define LPT_READ (LPT_BASE+1)

#define LPT_WRITE LPT_BASE

#if RTL_SIM

#define TCLK_BIT (0x01) /* D0, pin #2 */

#define TRST_BIT (0x02) /* D1, pin #3 */

#define TDI_BIT  (0x04) /* D2, pin #4 */

#define TMS_BIT  (0x08) /* D0, pin #5 */

#define TDO_BIT  (0x20) /* PE, pin #12 */

#define TMS      (0x02)

#define TDI      (0x01)

#else

#ifdef XILINX_PARALLEL_CABLE_III

#define TCLK_BIT (0x02) /* D1 pin 3 */

#define TRST_BIT (0x10) /* Not used */

#define TDI_BIT  (0x01) /* D0 pin 2 */

#define TMS_BIT  (0x04) /* D2 pin 4 */

#define TDO_BIT  (0x10) /* S6 pin 13*/

#define TMS      (0x02)

#define TDI      (0x01)

#else

#ifdef XESS_PARALLEL_CABLE

#define TCLK_BIT (0x04) /* D2 pin 4 */

#define TRST_BIT (0x08) /* D3 pin 5 */

#define TDI_BIT  (0x10) /* D4 pin 6 */

#define TMS_BIT  (0x20) /* D5 pin 7 */

#define TDO_BIT  (0x20) /* S5 pin 12*/

#define TMS      (0x02)

#define TDI      (0x01)

#endif

#endif

#endif

#ifdef RTL_SIM

# define JTAG_WAIT() usleep(1000)

# define JTAG_RETRY_WAIT() usleep (1000)

#else

# define JTAG_WAIT() {      \

  int i;        \

  volatile int j;   \

  for(i = 0; i < 1000; i++) \

    j = i;      \

  }

# define JTAG_RETRY_WAIT() usleep (1000)

#endif

/* Selects crc trailer size in bits. Currently supported: 8 */

#define CRC_SIZE (8)

/* Scan chain size in bits.  */

#define SC_SIZE (4)

#ifndef ULONGEST

#define ULONGEST unsigned long

#endif

extern unsigned int serverPort;

extern unsigned int server_fd;

extern void HandleServerSocket(Boolean block);

extern int err;

extern void JTAGRequest(void);

extern void GDBRequest(void);

/* read a word from wishbone */

int dbg_wb_read32(unsigned long adr, unsigned long *data);

/* write a word to wishbone */

int dbg_wb_write32(unsigned long adr, unsigned long data);

/* read a block from wishbone */

int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len);

/* write a block to wishbone */

int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len);

/* read a register from cpu */

int dbg_cpu_read32(unsigned long adr, unsigned long *data);

/* read a register from cpu module */

int dbg_cpu_read_reg(unsigned long adr, unsigned char *data);

/* write a cpu register */

int dbg_cpu_write32(unsigned long adr, unsigned long data);

/* write a cpu module register */

int dbg_cpu_write_reg(unsigned long adr, unsigned char data);

#define DC_SIZE           3

#define DC_STATUS_SIZE    4

/* reverse bit ordering! */

#define DC_CPU            0

#define DC_WISHBONE       4

#define DI_WB_STATUS      0

#define DI_WB_WRITE8      1

#define DI_WB_WRITE16     2

#define DI_WB_WRITE32     3

#define DI_WB_GO          4

#define DI_WB_READ8       5

#define DI_WB_READ16      6

#define DI_WB_READ32      7

#define DI_CPU_WRITE8     1

#define DI_CPU_WRITE32    2

#define DI_CPU_WRITE_REG  3

#define DI_CPU_GO         4

#define DI_CPU_READ8      5

#define DI_CPU_READ32     6

#define DI_CPU_READ_REG   7

#define DBG_CRC_SIZE      32

#define DBG_CRC_POLY      0x04c11db7

#define DBG_ERR_OK        0

#define DBG_ERR_CRC       1

#define DBG_ERR_INV_CHAIN 2

#define DBG_ERR_BUSERR    3

#define NUM_SOFT_RETRIES  3

#define NUM_HARD_RETRIES  3

#define NUM_ACCESS_RETRIES 10

#define CHECK(x) check(__FILE__, __LINE__, (x))

#endif /* _JP2_H_ */