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[/] [or1k/] [trunk/] [jtag/] [jp2.h] - Blame information for rev 1274

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#ifndef _JP2_H_
#define _JP2_H_
 
//#define DEBUG 1
//#define DEBUG2 1
 
#define Boolean int
#define false 0
#define true 1
 
#define GDB_IN "../sim/rtl_sim/run/gdb_in.dat"
#define GDB_OUT "../sim/rtl_sim/run/gdb_out.dat"
 
#ifdef DEBUG
#define debug printf
#else
#define debug
#endif
 
#ifdef DEBUG2
#define debug2 printf
#else
#define debug2
#endif
 
#if (DEBUG) || (DEBUG2)
#define flush_debug() fflush(stdout)
#else
#define flush_debug()
#endif
 
#define LPT_BASE (base)
#define LPT_READ (LPT_BASE+1)
#define LPT_WRITE LPT_BASE
#if RTL_SIM
#define TCLK_BIT (0x01) /* D0, pin #2 */
#define TRST_BIT (0x02) /* D1, pin #3 */
#define TDI_BIT  (0x04) /* D2, pin #4 */
#define TMS_BIT  (0x08) /* D0, pin #5 */
#define TDO_BIT  (0x20) /* PE, pin #12 */
#define TMS      (0x02)
#define TDI      (0x01)
#else
#ifdef XILINX_PARALLEL_CABLE_III
#define TCLK_BIT (0x02) /* D1 pin 3 */
#define TRST_BIT (0x10) /* Not used */
#define TDI_BIT  (0x01) /* D0 pin 2 */
#define TMS_BIT  (0x04) /* D2 pin 4 */
#define TDO_BIT  (0x10) /* S6 pin 13*/
#define TMS      (0x02)
#define TDI      (0x01)
#else
#ifdef XESS_PARALLEL_CABLE
#define TCLK_BIT (0x04) /* D2 pin 4 */
#define TRST_BIT (0x08) /* D3 pin 5 */
#define TDI_BIT  (0x10) /* D4 pin 6 */
#define TMS_BIT  (0x20) /* D5 pin 7 */
#define TDO_BIT  (0x20) /* S5 pin 12*/
#define TMS      (0x02)
#define TDI      (0x01)
#endif
#endif
#endif
 
#ifdef RTL_SIM
# define JTAG_WAIT() usleep(1000)
# define JTAG_RETRY_WAIT() usleep (1000)
#else
# define JTAG_WAIT() {      \
  int i;        \
  volatile int j;   \
  for(i = 0; i < 1000; i++) \
    j = i;      \
  }
# define JTAG_RETRY_WAIT() usleep (1000)
#endif
 
/* Selects crc trailer size in bits. Currently supported: 8 */
#define CRC_SIZE (8)
 
/* Scan chain size in bits.  */
#define SC_SIZE (4)
 
#ifndef ULONGEST
#define ULONGEST unsigned long
#endif
 
extern unsigned int serverPort;
extern unsigned int server_fd;
extern void HandleServerSocket(Boolean block);
 
extern int err;
extern void JTAGRequest(void);
extern void GDBRequest(void);
 
/* read a word from wishbone */
int dbg_wb_read32(unsigned long adr, unsigned long *data);
 
/* write a word to wishbone */
int dbg_wb_write32(unsigned long adr, unsigned long data);
 
/* read a block from wishbone */
int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len);
 
/* write a block to wishbone */
int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len);
 
/* read a register from cpu */
int dbg_cpu0_read(unsigned long adr, unsigned long *data);
 
/* read a register from cpu module */
int dbg_cpu0_read_ctrl(unsigned long adr, unsigned char *data);
 
/* write a cpu register */
int dbg_cpu0_write(unsigned long adr, unsigned long data);
 
/* write a cpu module register */
int dbg_cpu0_write_ctrl(unsigned long adr, unsigned char data);
 
 
#define DC_SIZE           4
#define DC_STATUS_SIZE    4
 
#define DC_WISHBONE       0
#define DC_CPU0           1
#define DC_CPU1           2
 
#define DI_GO          0
#define DI_READ_CMD    1
#define DI_WRITE_CMD   2
#define DI_READ_CTRL   3
#define DI_WRITE_CTRL  4
 
#define DBG_CRC_SIZE      32
#define DBG_CRC_POLY      0x04c11db7
 
#define DBG_ERR_OK        0
#define DBG_ERR_CRC       8
 
#define NUM_SOFT_RETRIES  3
#define NUM_HARD_RETRIES  3
#define NUM_ACCESS_RETRIES 10
 
#define CHECK(x) check(__FILE__, __LINE__, (x))
#endif /* _JP2_H_ */
 

Line No.	Rev	Author	Line
1	1246	markom	`#ifndef _JP2_H_`
2			`#define _JP2_H_`
3
4	1259	markom	`//#define DEBUG 1`
5			`//#define DEBUG2 1`
6
7	1246	markom	`#define Boolean int`
8			`#define false 0`
9			`#define true 1`
10
11			`#define GDB_IN "../sim/rtl_sim/run/gdb_in.dat"`
12			`#define GDB_OUT "../sim/rtl_sim/run/gdb_out.dat"`
13
14			`#ifdef DEBUG`
15			`#define debug printf`
16			`#else`
17			`#define debug`
18			`#endif`
19
20			`#ifdef DEBUG2`
21			`#define debug2 printf`
22			`#else`
23			`#define debug2`
24			`#endif`
25
26			`#if (DEBUG) \|\| (DEBUG2)`
27			`#define flush_debug() fflush(stdout)`
28			`#else`
29			`#define flush_debug()`
30			`#endif`
31
32			`#define LPT_BASE (base)`
33			`#define LPT_READ (LPT_BASE+1)`
34			`#define LPT_WRITE LPT_BASE`
35			`#if RTL_SIM`
36			`#define TCLK_BIT (0x01) /* D0, pin #2 */`
37			`#define TRST_BIT (0x02) /* D1, pin #3 */`
38			`#define TDI_BIT (0x04) /* D2, pin #4 */`
39			`#define TMS_BIT (0x08) /* D0, pin #5 */`
40			`#define TDO_BIT (0x20) /* PE, pin #12 */`
41			`#define TMS (0x02)`
42			`#define TDI (0x01)`
43			`#else`
44			`#ifdef XILINX_PARALLEL_CABLE_III`
45			`#define TCLK_BIT (0x02) /* D1 pin 3 */`
46			`#define TRST_BIT (0x10) /* Not used */`
47			`#define TDI_BIT (0x01) /* D0 pin 2 */`
48			`#define TMS_BIT (0x04) /* D2 pin 4 */`
49			`#define TDO_BIT (0x10) /* S6 pin 13*/`
50			`#define TMS (0x02)`
51			`#define TDI (0x01)`
52			`#else`
53			`#ifdef XESS_PARALLEL_CABLE`
54			`#define TCLK_BIT (0x04) /* D2 pin 4 */`
55			`#define TRST_BIT (0x08) /* D3 pin 5 */`
56			`#define TDI_BIT (0x10) /* D4 pin 6 */`
57			`#define TMS_BIT (0x20) /* D5 pin 7 */`
58			`#define TDO_BIT (0x20) /* S5 pin 12*/`
59			`#define TMS (0x02)`
60			`#define TDI (0x01)`
61			`#endif`
62			`#endif`
63			`#endif`
64
65			`#ifdef RTL_SIM`
66			`# define JTAG_WAIT() usleep(1000)`
67			`# define JTAG_RETRY_WAIT() usleep (1000)`
68			`#else`
69			`# define JTAG_WAIT() { \`
70			`int i; \`
71			`volatile int j; \`
72			`for(i = 0; i < 1000; i++) \`
73			`j = i; \`
74			`}`
75			`# define JTAG_RETRY_WAIT() usleep (1000)`
76			`#endif`
77
78			`/* Selects crc trailer size in bits. Currently supported: 8 */`
79			`#define CRC_SIZE (8)`
80
81			`/* Scan chain size in bits. */`
82			`#define SC_SIZE (4)`
83
84			`#ifndef ULONGEST`
85			`#define ULONGEST unsigned long`
86			`#endif`
87
88			`extern unsigned int serverPort;`
89			`extern unsigned int server_fd;`
90			`extern void HandleServerSocket(Boolean block);`
91
92			`extern int err;`
93			`extern void JTAGRequest(void);`
94			`extern void GDBRequest(void);`
95
96			`/* read a word from wishbone */`
97			`int dbg_wb_read32(unsigned long adr, unsigned long *data);`
98
99			`/* write a word to wishbone */`
100			`int dbg_wb_write32(unsigned long adr, unsigned long data);`
101
102			`/* read a block from wishbone */`
103	1259	markom	`int dbg_wb_read_block32(unsigned long adr, unsigned long *data, int len);`
104	1246	markom
105			`/* write a block to wishbone */`
106			`int dbg_wb_write_block32(unsigned long adr, unsigned long *data, int len);`
107
108			`/* read a register from cpu */`
109	1274	markom	`int dbg_cpu0_read(unsigned long adr, unsigned long *data);`
110	1246	markom
111			`/* read a register from cpu module */`
112	1274	markom	`int dbg_cpu0_read_ctrl(unsigned long adr, unsigned char *data);`
113	1246	markom
114			`/* write a cpu register */`
115	1274	markom	`int dbg_cpu0_write(unsigned long adr, unsigned long data);`
116	1246	markom
117			`/* write a cpu module register */`
118	1274	markom	`int dbg_cpu0_write_ctrl(unsigned long adr, unsigned char data);`
119	1246	markom
120
121	1274	markom	`#define DC_SIZE 4`
122	1246	markom	`#define DC_STATUS_SIZE 4`
123
124	1274	markom	`#define DC_WISHBONE 0`
125			`#define DC_CPU0 1`
126			`#define DC_CPU1 2`
127	1246	markom
128	1274	markom	`#define DI_GO 0`
129			`#define DI_READ_CMD 1`
130			`#define DI_WRITE_CMD 2`
131			`#define DI_READ_CTRL 3`
132			`#define DI_WRITE_CTRL 4`
133	1246	markom
134			`#define DBG_CRC_SIZE 32`
135			`#define DBG_CRC_POLY 0x04c11db7`
136
137			`#define DBG_ERR_OK 0`
138	1274	markom	`#define DBG_ERR_CRC 8`
139	1246	markom
140			`#define NUM_SOFT_RETRIES 3`
141			`#define NUM_HARD_RETRIES 3`
142			`#define NUM_ACCESS_RETRIES 10`
143
144	1259	markom	`#define CHECK(x) check(__FILE__, __LINE__, (x))`
145	1246	markom	`#endif /* _JP2_H_ */`
146

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[/] [or1k/] [trunk/] [jtag/] [jp2.h] - Blame information for rev 1274