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1275 |
phoenix |
/*
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* linux/arch/arm/mm/proc-arm2,3.S
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*
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* Copyright (C) 1997-1999 Russell King
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*
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* This program is free software; you can redistribute it and/or modify
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* it under the terms of the GNU General Public License version 2 as
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* published by the Free Software Foundation.
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*
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* MMU functions for ARM2,3
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*
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* These are the low level assembler for performing cache
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* and memory functions on ARM2, ARM250 and ARM3 processors.
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*/
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#include
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#include
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#include
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#include
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/*
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* MEMC workhorse code. It's both a horse which things it's a pig.
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*/
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/*
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* Function: cpu_memc_update_entry(pgd_t *pgd, unsigned long phys_pte, unsigned long addr)
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* Params : pgd Page tables/MEMC mapping
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* : phys_pte physical address, or PTE
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* : addr virtual address
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*/
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ENTRY(cpu_memc_update_entry)
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tst r1, #PAGE_PRESENT @ is the page present
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orreq r1, r1, #PAGE_OLD | PAGE_CLEAN
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moveq r2, #0x01f00000
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mov r3, r1, lsr #13 @ convert to physical page nr
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and r3, r3, #0x3fc
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adr ip, memc_phys_table_32
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ldr r3, [ip, r3]
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tst r1, #PAGE_OLD | PAGE_NOT_USER
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biceq r3, r3, #0x200
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tsteq r1, #PAGE_READONLY | PAGE_CLEAN
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biceq r3, r3, #0x300
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mov r2, r2, lsr #15 @ virtual -> nr
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orr r3, r3, r2, lsl #15
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and r2, r2, #0x300
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orr r3, r3, r2, lsl #2
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and r2, r3, #255
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sub r0, r0, #256 * 4
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str r3, [r0, r2, lsl #2]
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strb r3, [r3]
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movs pc, lr
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/*
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* Params : r0 = preserved
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* : r1 = memc table base (preserved)
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* : r2 = page table entry
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* : r3 = preserved
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* : r4 = unused
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* : r5 = memc physical address translation table
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* : ip = virtual address (preserved)
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*/
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update_pte:
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mov r4, r2, lsr #13
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and r4, r4, #0x3fc
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ldr r4, [r5, r4] @ covert to MEMC page
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tst r2, #PAGE_OLD | PAGE_NOT_USER @ check for MEMC read
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biceq r4, r4, #0x200
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tsteq r2, #PAGE_READONLY | PAGE_CLEAN @ check for MEMC write
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biceq r4, r4, #0x300
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orr r4, r4, ip
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and r2, ip, #0x01800000
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orr r4, r4, r2, lsr #13
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and r2, r4, #255
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str r4, [r1, r2, lsl #2]
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movs pc, lr
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/*
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* Params : r0 = preserved
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* : r1 = memc table base (preserved)
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* : r2 = page table base
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* : r3 = preserved
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* : r4 = unused
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* : r5 = memc physical address translation table
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* : ip = virtual address (updated)
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*/
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update_pte_table:
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stmfd sp!, {r0, lr}
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bic r0, r2, #3
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1: ldr r2, [r0], #4 @ get entry
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tst r2, #PAGE_PRESENT @ page present
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blne update_pte @ process pte
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add ip, ip, #32768 @ increment virt addr
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ldr r2, [r0], #4 @ get entry
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tst r2, #PAGE_PRESENT @ page present
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blne update_pte @ process pte
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add ip, ip, #32768 @ increment virt addr
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ldr r2, [r0], #4 @ get entry
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tst r2, #PAGE_PRESENT @ page present
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blne update_pte @ process pte
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add ip, ip, #32768 @ increment virt addr
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ldr r2, [r0], #4 @ get entry
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tst r2, #PAGE_PRESENT @ page present
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blne update_pte @ process pte
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add ip, ip, #32768 @ increment virt addr
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tst ip, #32768 * 31 @ finished?
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bne 1b
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ldmfd sp!, {r0, pc}^
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/*
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* Function: cpu_memc_update_all(pgd_t *pgd)
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* Params : pgd Page tables/MEMC mapping
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* Notes : this is optimised for 32k pages
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*/
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ENTRY(cpu_memc_update_all)
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stmfd sp!, {r4, r5, lr}
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bl clear_tables
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sub r1, r0, #256 * 4 @ start of MEMC tables
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adr r5, memc_phys_table_32 @ Convert to logical page number
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mov ip, #0 @ virtual address
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1: ldmia r0!, {r2, r3}
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tst r2, #PAGE_PRESENT
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addeq ip, ip, #1048576
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blne update_pte_table
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mov r2, r3
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tst r2, #PAGE_PRESENT
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addeq ip, ip, #1048576
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blne update_pte_table
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teq ip, #32 * 1048576
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bne 1b
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ldmfd sp!, {r4, r5, pc}^
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/*
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* Build the table to map from physical page number to memc page number
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*/
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.type memc_phys_table_32, #object
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memc_phys_table_32:
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.irp b7, 0x00, 0x80
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.irp b6, 0x00, 0x02
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.irp b5, 0x00, 0x04
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.irp b4, 0x00, 0x01
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.irp b3, 0x00, 0x40
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.irp b2, 0x00, 0x20
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.irp b1, 0x00, 0x10
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.irp b0, 0x00, 0x08
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.long 0x03800300 + \b7 + \b6 + \b5 + \b4 + \b3 + \b2 + \b1 + \b0
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.endr
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.endr
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.endr
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.endr
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.endr
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.endr
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.endr
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.endr
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.size memc_phys_table_32, . - memc_phys_table_32
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/*
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* helper for cpu_memc_update_all, this clears out all
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* mappings, setting them close to the top of memory,
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* and inaccessible (0x01f00000).
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* Params : r0 = page table pointer
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*/
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clear_tables: ldr r1, _arm3_set_pgd - 4
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ldr r2, [r1]
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sub r1, r0, #256 * 4 @ start of MEMC tables
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add r2, r1, r2, lsl #2 @ end of tables
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mov r3, #0x03f00000 @ Default mapping (null mapping)
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orr r3, r3, #0x00000f00
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orr r4, r3, #1
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orr r5, r3, #2
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orr ip, r3, #3
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1: stmia r1!, {r3, r4, r5, ip}
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add r3, r3, #4
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add r4, r4, #4
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add r5, r5, #4
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add ip, ip, #4
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stmia r1!, {r3, r4, r5, ip}
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add r3, r3, #4
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add r4, r4, #4
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add r5, r5, #4
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add ip, ip, #4
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teq r1, r2
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bne 1b
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mov pc, lr
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/*
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* Function: *_set_pgd(pgd_t *pgd)
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* Params : pgd New page tables/MEMC mapping
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* Purpose : update MEMC hardware with new mapping
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*/
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.word SYMBOL_NAME(page_nr)
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_arm3_set_pgd: mcr p15, 0, r1, c1, c0, 0 @ flush cache
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_arm2_set_pgd: stmfd sp!, {lr}
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ldr r1, _arm3_set_pgd - 4
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ldr r2, [r1]
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sub r0, r0, #256 * 4 @ start of MEMC tables
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add r1, r0, r2, lsl #2 @ end of tables
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1: ldmia r0!, {r2, r3, ip, lr}
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strb r2, [r2]
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strb r3, [r3]
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strb ip, [ip]
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strb lr, [lr]
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ldmia r0!, {r2, r3, ip, lr}
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strb r2, [r2]
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strb r3, [r3]
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strb ip, [ip]
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strb lr, [lr]
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teq r0, r1
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bne 1b
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ldmfd sp!, {pc}^
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/*
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* Function: *_proc_init (void)
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* Purpose : Initialise the cache control registers
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*/
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_arm3_proc_init:
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mov r0, #0x001f0000
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orr r0, r0, #0x0000ff00
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orr r0, r0, #0x000000ff
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| 221 |
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mcr p15, 0, r0, c3, c0 @ ARM3 Cacheable
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| 222 |
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mcr p15, 0, r0, c4, c0 @ ARM3 Updateable
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mov r0, #0
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| 224 |
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mcr p15, 0, r0, c5, c0 @ ARM3 Disruptive
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| 225 |
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mcr p15, 0, r0, c1, c0 @ ARM3 Flush
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| 226 |
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mov r0, #3
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| 227 |
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mcr p15, 0, r0, c2, c0 @ ARM3 Control
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| 228 |
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_arm2_proc_init:
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| 229 |
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movs pc, lr
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| 230 |
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| 231 |
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/*
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| 232 |
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* Function: *_proc_fin (void)
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| 233 |
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* Purpose : Finalise processor (disable caches)
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| 234 |
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*/
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| 235 |
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_arm3_proc_fin: mov r0, #2
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mcr p15, 0, r0, c2, c0
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| 237 |
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_arm2_proc_fin: orrs pc, lr, #I_BIT|F_BIT
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| 238 |
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| 239 |
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/*
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| 240 |
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* Function: *_xchg_1 (int new, volatile void *ptr)
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| 241 |
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* Params : new New value to store at...
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| 242 |
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* : ptr pointer to byte-wide location
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| 243 |
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* Purpose : Performs an exchange operation
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| 244 |
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* Returns : Original byte data at 'ptr'
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| 245 |
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*/
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| 246 |
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_arm2_xchg_1: mov r2, pc
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| 247 |
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orr r2, r2, #I_BIT
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| 248 |
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teqp r2, #0
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| 249 |
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ldrb r2, [r1]
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| 250 |
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strb r0, [r1]
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| 251 |
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mov r0, r2
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| 252 |
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movs pc, lr
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| 253 |
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| 254 |
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_arm3_xchg_1: swpb r0, r0, [r1]
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| 255 |
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movs pc, lr
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| 256 |
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| 257 |
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/*
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| 258 |
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* Function: *_xchg_4 (int new, volatile void *ptr)
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| 259 |
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* Params : new New value to store at...
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| 260 |
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* : ptr pointer to word-wide location
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| 261 |
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* Purpose : Performs an exchange operation
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| 262 |
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* Returns : Original word data at 'ptr'
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| 263 |
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*/
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| 264 |
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_arm2_xchg_4: mov r2, pc
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| 265 |
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orr r2, r2, #I_BIT
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| 266 |
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teqp r2, #0
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| 267 |
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ldr r2, [r1]
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| 268 |
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str r0, [r1]
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| 269 |
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mov r0, r2
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| 270 |
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movs pc, lr
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| 271 |
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| 272 |
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_arm3_xchg_4: swp r0, r0, [r1]
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| 273 |
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movs pc, lr
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| 274 |
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| 275 |
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_arm2_3_check_bugs:
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| 276 |
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bics pc, lr, #0x04000000 @ Clear FIQ disable bit
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| 277 |
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| 278 |
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_arm2_name: .asciz "ARM 2"
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| 279 |
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_arm250_name: .asciz "ARM 250"
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| 280 |
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_arm3_name: .asciz "ARM 3"
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| 281 |
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| 282 |
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.section ".text.init", #alloc, #execinstr
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| 283 |
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/*
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| 284 |
|
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* Purpose : Function pointers used to access above functions - all calls
|
| 285 |
|
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* come through these
|
| 286 |
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*/
|
| 287 |
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.globl SYMBOL_NAME(arm2_processor_functions)
|
| 288 |
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SYMBOL_NAME(arm2_processor_functions):
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| 289 |
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.word _arm2_3_check_bugs
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| 290 |
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.word _arm2_proc_init
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| 291 |
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.word _arm2_proc_fin
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| 292 |
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.word _arm2_set_pgd
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| 293 |
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.word _arm2_xchg_1
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| 294 |
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.word _arm2_xchg_4
|
| 295 |
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| 296 |
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cpu_arm2_info:
|
| 297 |
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.long 0
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| 298 |
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.long _arm2_name
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| 299 |
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| 300 |
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.globl SYMBOL_NAME(arm250_processor_functions)
|
| 301 |
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SYMBOL_NAME(arm250_processor_functions):
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| 302 |
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.word _arm2_3_check_bugs
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| 303 |
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.word _arm2_proc_init
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| 304 |
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.word _arm2_proc_fin
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| 305 |
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.word _arm2_set_pgd
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| 306 |
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.word _arm3_xchg_1
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| 307 |
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.word _arm3_xchg_4
|
| 308 |
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| 309 |
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cpu_arm250_info:
|
| 310 |
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.long 0
|
| 311 |
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.long _arm250_name
|
| 312 |
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|
| 313 |
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.globl SYMBOL_NAME(arm3_processor_functions)
|
| 314 |
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SYMBOL_NAME(arm3_processor_functions):
|
| 315 |
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.word _arm2_3_check_bugs
|
| 316 |
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.word _arm3_proc_init
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| 317 |
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.word _arm3_proc_fin
|
| 318 |
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.word _arm3_set_pgd
|
| 319 |
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.word _arm3_xchg_1
|
| 320 |
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.word _arm3_xchg_4
|
| 321 |
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| 322 |
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cpu_arm3_info:
|
| 323 |
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.long 0
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| 324 |
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.long _arm3_name
|
| 325 |
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|
| 326 |
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arm2_arch_name: .asciz "armv1"
|
| 327 |
|
|
arm3_arch_name: .asciz "armv2"
|
| 328 |
|
|
arm2_elf_name: .asciz "v1"
|
| 329 |
|
|
arm3_elf_name: .asciz "v2"
|
| 330 |
|
|
.align
|
| 331 |
|
|
|
| 332 |
|
|
.section ".proc.info", #alloc, #execinstr
|
| 333 |
|
|
|
| 334 |
|
|
.long 0x41560200
|
| 335 |
|
|
.long 0xfffffff0
|
| 336 |
|
|
.long 0
|
| 337 |
|
|
mov pc, lr
|
| 338 |
|
|
.long arm2_arch_name
|
| 339 |
|
|
.long arm2_elf_name
|
| 340 |
|
|
.long 0
|
| 341 |
|
|
.long cpu_arm2_info
|
| 342 |
|
|
.long SYMBOL_NAME(arm2_processor_functions)
|
| 343 |
|
|
|
| 344 |
|
|
.long 0x41560250
|
| 345 |
|
|
.long 0xfffffff0
|
| 346 |
|
|
.long 0
|
| 347 |
|
|
mov pc, lr
|
| 348 |
|
|
.long arm3_arch_name
|
| 349 |
|
|
.long arm3_elf_name
|
| 350 |
|
|
.long 0
|
| 351 |
|
|
.long cpu_arm250_info
|
| 352 |
|
|
.long SYMBOL_NAME(arm250_processor_functions)
|
| 353 |
|
|
|
| 354 |
|
|
.long 0x41560300
|
| 355 |
|
|
.long 0xfffffff0
|
| 356 |
|
|
.long 0
|
| 357 |
|
|
mov pc, lr
|
| 358 |
|
|
.long arm3_arch_name
|
| 359 |
|
|
.long arm3_elf_name
|
| 360 |
|
|
.long 0
|
| 361 |
|
|
.long cpu_arm3_info
|
| 362 |
|
|
.long SYMBOL_NAME(arm3_processor_functions)
|
| 363 |
|
|
|
