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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [arm/] [mm/] [proc-arm922.S] - Blame information for rev 1765

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/*
 *  linux/arch/arm/mm/arm922.S: MMU functions for ARM922
 *
 *  Copyright (C) 1999,2000 ARM Limited
 *  Copyright (C) 2000 Deep Blue Solutions Ltd.
 *  Copyright (C) 2001 Altera Corporation
 *
 * This program is free software; you can redistribute it and/or modify
 * it under the terms of the GNU General Public License as published by
 * the Free Software Foundation; either version 2 of the License, or
 * (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
 *
 *
 * These are the low level assembler for performing cache and TLB
 * functions on the arm922.
 */
#include 
#include 
#include 
#include 
#include 
#include 
 
/*
 * This is the maximum size of an area which will be invalidated
 * using the single invalidate entry instructions.  Anything larger
 * than this, and we go for the whole cache.
 *
 * This value should be chosen such that we choose the cheapest
 * alternative.
 */
#define MAX_AREA_SIZE   8192
 
/*
 * the cache line size of the I and D cache
 */
#define DCACHELINESIZE  32
#define ICACHELINESIZE  32
 
/*
 * and the page size
 */
#define PAGESIZE        4096
 
        .text
 
/*
 * cpu_arm922_data_abort()
 *
 * obtain information about current aborted instruction
 *
 * r0 = address of aborted instruction
 *
 * Returns:
 *  r0 = address of abort
 *  r1 != 0 if writing
 *  r3 = FSR
 */
        .align  5
ENTRY(cpu_arm922_data_abort)
        ldr     r1, [r0]                        @ read aborted instruction
        mrc     p15, 0, r0, c6, c0, 0           @ get FAR
        tst     r1, r1, lsr #21                 @ C = bit 20
        mrc     p15, 0, r3, c5, c0, 0           @ get FSR
        sbc     r1, r1, r1                      @ r1 = C - 1
        and     r3, r3, #255
        mov     pc, lr
 
/*
 * cpu_arm922_check_bugs()
 */
ENTRY(cpu_arm922_check_bugs)
        mrs     ip, cpsr
        bic     ip, ip, #F_BIT
        msr     cpsr, ip
        mov     pc, lr
 
/*
 * cpu_arm922_proc_init()
 */
ENTRY(cpu_arm922_proc_init)
        mov     pc, lr
 
/*
 * cpu_arm922_proc_fin()
 */
ENTRY(cpu_arm922_proc_fin)
        stmfd   sp!, {lr}
        mov     ip, #F_BIT | I_BIT | SVC_MODE
        msr     cpsr_c, ip
        bl      cpu_arm922_cache_clean_invalidate_all
        mrc     p15, 0, r0, c1, c0, 0           @ ctrl register
        bic     r0, r0, #0x1000                 @ ...i............
        bic     r0, r0, #0x000e                 @ ............wca.
        mcr     p15, 0, r0, c1, c0, 0           @ disable caches
        ldmfd   sp!, {pc}
 
/*
 * cpu_arm922_reset(loc)
 *
 * Perform a soft reset of the system.  Put the CPU into the
 * same state as it would be if it had been reset, and branch
 * to what would be the reset vector.
 *
 * loc: location to jump to for soft reset
 */
        .align  5
ENTRY(cpu_arm922_reset)
        mov     ip, #0
        mcr     p15, 0, ip, c7, c7, 0           @ invalidate I,D caches
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
        mrc     p15, 0, ip, c1, c0, 0           @ ctrl register
        bic     ip, ip, #0x000f                 @ ............wcam
        bic     ip, ip, #0x1100                 @ ...i...s........
        mcr     p15, 0, ip, c1, c0, 0           @ ctrl register
        mov     pc, r0
 
/*
 * cpu_arm922_do_idle()
 */
        .align  5
ENTRY(cpu_arm922_do_idle)
        mcr     p15, 0, r0, c7, c0, 4           @ Wait for interrupt
        mov     pc, lr
 
/* ================================= CACHE ================================ */
 
 
/*
 * cpu_arm922_cache_clean_invalidate_all()
 *
 * clean and invalidate all cache lines
 *
 * Note:
 *  1. we should preserve r0 at all times
 */
        .align  5
ENTRY(cpu_arm922_cache_clean_invalidate_all)
        mov     r2, #1
cpu_arm922_cache_clean_invalidate_all_r2:
        mov     ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
        mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
#else
/*
 * 'Clean & Invalidate whole DCache'
 * Re-written to use Index Ops.
 * Uses registers r1, r3 and ip
 */
        mov     r1, #3 << 5                     @ 4 segments
1:      orr     r3, r1, #63 << 26               @ 64 entries
2:      mcr     p15, 0, r3, c7, c14, 2          @ clean & invalidate D index
        subs    r3, r3, #1 << 26
        bcs     2b                              @ entries 63 to 0
        subs    r1, r1, #1 << 5
        bcs     1b                              @ segments 7 to 0
#endif
        teq     r2, #0
        mcrne   p15, 0, ip, c7, c5, 0           @ invalidate I cache
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mov     pc, lr
 
/*
 * cpu_arm922_cache_clean_invalidate_range(start, end, flags)
 *
 * clean and invalidate all cache lines associated with this area of memory
 *
 * start: Area start address
 * end:   Area end address
 * flags: nonzero for I cache as well
 */
                .align  5
ENTRY(cpu_arm922_cache_clean_invalidate_range)
        bic     r0, r0, #DCACHELINESIZE - 1     @ && added by PGM
        bic     r1, r1, #DCACHELINESIZE - 1     @ && added by DHM
        sub     r3, r1, r0
        cmp     r3, #MAX_AREA_SIZE
        bgt     cpu_arm922_cache_clean_invalidate_all_r2
1:      teq     r2, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
        mcrne   p15, 0, r0, c7, c5, 1           @ invalidate I entry
        add     r0, r0, #DCACHELINESIZE
        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
        mcrne   p15, 0, r0, c7, c5, 1           @ invalidate I entry
        add     r0, r0, #DCACHELINESIZE
#else
        mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
        mcrne   p15, 0, r0, c7, c5, 1           @ invalidate I entry
        add     r0, r0, #DCACHELINESIZE
        mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
        mcrne   p15, 0, r0, c7, c5, 1           @ invalidate I entry
        add     r0, r0, #DCACHELINESIZE
#endif
        cmp     r0, r1
        blt     1b
 
        mcr     p15, 0, r1, c7, c10, 4          @ drain WB
        mov     pc, lr
 
/*
 * cpu_arm922_flush_ram_page(page)
 *
 * clean and invalidate all cache lines associated with this area of memory
 *
 * page: page to clean and invalidate
 */
        .align  5
ENTRY(cpu_arm922_flush_ram_page)
        mov     r1, #PAGESIZE
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
        add     r0, r0, #DCACHELINESIZE
        mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
        add     r0, r0, #DCACHELINESIZE
#else
1:      mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
        add     r0, r0, #DCACHELINESIZE
        mcr     p15, 0, r0, c7, c14, 1          @ clean and invalidate D entry
        add     r0, r0, #DCACHELINESIZE
#endif
        subs    r1, r1, #2 * DCACHELINESIZE
        bne     1b
        mcr     p15, 0, r1, c7, c10, 4          @ drain WB
        mov     pc, lr
 
/* ================================ D-CACHE =============================== */
 
/*
 * cpu_arm922_dcache_invalidate_range(start, end)
 *
 * throw away all D-cached data in specified region without an obligation
 * to write them back.  Note however that we must clean the D-cached entries
 * around the boundaries if the start and/or end address are not cache
 * aligned.
 *
 * start: virtual start address
 * end:   virtual end address
 */
        .align  5
ENTRY(cpu_arm922_dcache_invalidate_range)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
        tst     r0, #DCACHELINESIZE - 1
        mcrne   p15, 0, r0, c7, c10, 1          @ clean D entry
        tst     r1, #DCACHELINESIZE - 1
        mcrne   p15, 0, r1, c7, c10, 1          @ clean D entry
#endif          @ clean D entry
        bic     r0, r0, #DCACHELINESIZE - 1
        bic     r1, r1, #DCACHELINESIZE - 1
1:      mcr     p15, 0, r0, c7, c6, 1           @ invalidate D entry
        add     r0, r0, #DCACHELINESIZE
        cmp     r0, r1
        blt     1b
        mov     pc, lr
 
/*
 * cpu_arm922_dcache_clean_range(start, end)
 *
 * For the specified virtual address range, ensure that all caches contain
 * clean data, such that peripheral accesses to the physical RAM fetch
 * correct data.
 *
 * start: virtual start address
 * end:   virtual end address
 */
        .align  5
ENTRY(cpu_arm922_dcache_clean_range)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
        bic     r0, r0, #DCACHELINESIZE - 1
        sub     r1, r1, r0
        cmp     r1, #MAX_AREA_SIZE
        mov     r2, #0
        bgt     cpu_arm922_cache_clean_invalidate_all_r2
 
        bic     r1, r1, #DCACHELINESIZE -1
        add     r1, r1, #DCACHELINESIZE
 
1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #DCACHELINESIZE
        subs    r1, r1, #DCACHELINESIZE
        bpl     1b
#endif
        mcr     p15, 0, r2, c7, c10, 4          @ drain WB
        mov     pc, lr
 
/*
 * cpu_arm922_dcache_clean_page(page)
 *
 * Cleans a single page of dcache so that if we have any future aliased
 * mappings, they will be consistent at the time that they are created.
 *
 * page: virtual address of page to clean from dcache
 *
 * Note:
 *  1. we don't need to flush the write buffer in this case.
 *  2. we don't invalidate the entries since when we write the page
 *     out to disk, the entries may get reloaded into the cache.
 */
        .align  5
ENTRY(cpu_arm922_dcache_clean_page)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
        mov     r1, #PAGESIZE
1:      mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #DCACHELINESIZE
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        add     r0, r0, #DCACHELINESIZE
        subs    r1, r1, #2 * DCACHELINESIZE
        bne     1b
#endif
        mov     pc, lr
 
/*
 * cpu_arm922_dcache_clean_entry(addr)
 *
 * Clean the specified entry of any caches such that the MMU
 * translation fetches will obtain correct data.
 *
 * addr: cache-unaligned virtual address
 */
        .align  5
ENTRY(cpu_arm922_dcache_clean_entry)
#ifndef CONFIG_CPU_ARM922_WRITETHROUGH
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
#endif
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 
/* ================================ I-CACHE =============================== */
 
/*
 * cpu_arm922_icache_invalidate_range(start, end)
 *
 * invalidate a range of virtual addresses from the Icache
 *
 * This is a little misleading, it is not intended to clean out
 * the i-cache but to make sure that any data written to the
 * range is made consistant.  This means that when we execute code
 * in that region, everything works as we expect.
 *
 * This generally means writing back data in the Dcache and
 * write buffer and flushing the Icache over that region
 *
 * start: virtual start address
 * end:   virtual end address
 *
 * NOTE: ICACHELINESIZE == DCACHELINESIZE (so we don't need to
 * loop twice, once for i-cache, once for d-cache)
 */
        .align  5
ENTRY(cpu_arm922_icache_invalidate_range)
        bic     r0, r0, #ICACHELINESIZE - 1     @ Safety check
        sub     r1, r1, r0
        cmp     r1, #MAX_AREA_SIZE
        bgt     cpu_arm922_cache_clean_invalidate_all_r2
 
        bic     r1, r1, #ICACHELINESIZE - 1
        add     r1, r1, #ICACHELINESIZE
 
1:      mcr     p15, 0, r0, c7, c5, 1           @ Clean I entry
        mcr     p15, 0, r0, c7, c10, 1          @ Clean D entry
        add     r0, r0, #ICACHELINESIZE
        subs    r1, r1, #ICACHELINESIZE
        bne     1b
 
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 
ENTRY(cpu_arm922_icache_invalidate_page)
        mcr     p15, 0, r0, c7, c5, 0           @ invalidate I cache
        mov     pc, lr
 
/* ================================== TLB ================================= */
 
/*
 * cpu_arm922_tlb_invalidate_all()
 *
 * Invalidate all TLB entries
 */
        .align  5
ENTRY(cpu_arm922_tlb_invalidate_all)
        mov     r0, #0
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mcr     p15, 0, r0, c8, c7, 0           @ invalidate I & D TLBs
        mov     pc, lr
 
/*
 * cpu_arm922_tlb_invalidate_range(start, end)
 *
 * invalidate TLB entries covering the specified range
 *
 * start: range start address
 * end:   range end address
 */
        .align  5
ENTRY(cpu_arm922_tlb_invalidate_range)
        sub     r3, r1, r0
        cmp     r3, #256 * PAGESIZE             @ arbitary, should be tuned
        bhi     cpu_arm922_tlb_invalidate_all
 
        mov     r3, #0
        mcr     p15, 0, r3, c7, c10, 4          @ drain WB
 
        mov     r3, #PAGESIZE
        sub     r3, r3, #1
        bic     r0, r0, r3
        bic     r1, r1, r3
 
1:      mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
        mcr     p15, 0, r0, c8, c5, 1           @ invalidate I TLB entry
        add     r0, r0, #PAGESIZE
        cmp     r0, r1
        blt     1b
        mov     pc, lr
 
/*
 * cpu_arm922_tlb_invalidate_page(page, flags)
 *
 * invalidate the TLB entries for the specified page.
 *
 * page:  page to invalidate
 * flags: non-zero if we include the I TLB
 */
        .align  5
ENTRY(cpu_arm922_tlb_invalidate_page)
        mov     r3, #0
        mcr     p15, 0, r3, c7, c10, 4          @ drain WB
        teq     r1, #0
        mcr     p15, 0, r0, c8, c6, 1           @ invalidate D TLB entry
        mcrne   p15, 0, r0, c8, c5, 1           @ invalidate I TLB entry
        mov     pc, lr
 
/* =============================== PageTable ============================== */
 
/*
 * cpu_arm922_set_pgd(pgd)
 *
 * Set the translation base pointer to be as described by pgd.
 *
 * pgd: new page tables
 */
        .align  5
ENTRY(cpu_arm922_set_pgd)
        mov     ip, #0
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
        /* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */
        mcr     p15, 0, ip, c7, c6, 0           @ invalidate D cache
#else
@ && 'Clean & Invalidate whole DCache'
@ && Re-written to use Index Ops.
@ && Uses registers r1, r3 and ip
 
        mov     r1, #3 << 5                     @ 4 segments
1:      orr     r3, r1, #63 << 26               @ 64 entries
2:      mcr     p15, 0, r3, c7, c14, 2          @ clean & invalidate D index
        subs    r3, r3, #1 << 26
        bcs     2b                              @ entries 63 to 0
        subs    r1, r1, #1 << 5
        bcs     1b                              @ segments 7 to 0
#endif
        mcr     p15, 0, ip, c7, c5, 0           @ invalidate I cache
        mcr     p15, 0, ip, c7, c10, 4          @ drain WB
        mcr     p15, 0, r0, c2, c0, 0           @ load page table pointer
        mcr     p15, 0, ip, c8, c7, 0           @ invalidate I & D TLBs
        mov     pc, lr
 
/*
 * cpu_arm922_set_pmd(pmdp, pmd)
 *
 * Set a level 1 translation table entry, and clean it out of
 * any caches such that the MMUs can load it correctly.
 *
 * pmdp: pointer to PMD entry
 * pmd:  PMD value to store
 */
        .align  5
ENTRY(cpu_arm922_set_pmd)
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
        eor     r2, r1, #0x0a                   @ C & Section
        tst     r2, #0x0b
        biceq   r1, r1, #4                      @ clear bufferable bit
#endif
        str     r1, [r0]
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 
/*
 * cpu_arm922_set_pte(ptep, pte)
 *
 * Set a PTE and flush it out
 */
        .align  5
ENTRY(cpu_arm922_set_pte)
        str     r1, [r0], #-1024                @ linux version
 
        eor     r1, r1, #LPTE_PRESENT | LPTE_YOUNG | LPTE_WRITE | LPTE_DIRTY
 
        bic     r2, r1, #0xff0
        bic     r2, r2, #3
        orr     r2, r2, #HPTE_TYPE_SMALL
 
        tst     r1, #LPTE_USER | LPTE_EXEC      @ User or Exec?
        orrne   r2, r2, #HPTE_AP_READ
 
        tst     r1, #LPTE_WRITE | LPTE_DIRTY    @ Write and Dirty?
        orreq   r2, r2, #HPTE_AP_WRITE
 
        tst     r1, #LPTE_PRESENT | LPTE_YOUNG  @ Present and Young?
        movne   r2, #0
 
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
        eor     r3, r2, #0x0a                   @ C & small page?
        tst     r3, #0x0b
        biceq   r2, r2, #4
#endif
        str     r2, [r0]                        @ hardware version
        mov     r0, r0
        mcr     p15, 0, r0, c7, c10, 1          @ clean D entry
        mcr     p15, 0, r0, c7, c10, 4          @ drain WB
        mov     pc, lr
 
 
ENTRY(cpu_arm922_name)
        .ascii  "Arm922T"
#ifndef CONFIG_CPU_ICACHE_DISABLE
        .ascii  "i"
#endif
#ifndef CONFIG_CPU_DCACHE_DISABLE
        .ascii  "d"
#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH
        .ascii  "(wt)"
#else
        .ascii  "(wb)"
#endif
#endif
        .ascii  "\0"
        .align
 
        .section ".text.init", #alloc, #execinstr
 
__arm922_setup:
        mov     r0, #0
        mcr     p15, 0, r0, c7, c7              @ invalidate I,D caches on v4
        mcr     p15, 0, r0, c7, c10, 4          @ drain write buffer on v4
        mcr     p15, 0, r0, c8, c7              @ invalidate I,D TLBs on v4
        mcr     p15, 0, r4, c2, c0              @ load page table pointer
        mov     r0, #0x1f                       @ Domains 0, 1 = client
        mcr     p15, 0, r0, c3, c0              @ load domain access register
        mrc     p15, 0, r0, c1, c0              @ get control register v4
/*
 * Clear out 'unwanted' bits (then put them in if we need them)
 */
                                                @   VI ZFRS BLDP WCAM
        bic     r0, r0, #0x0e00
        bic     r0, r0, #0x0002
        bic     r0, r0, #0x000c
        bic     r0, r0, #0x1000                 @ ...0 000. .... 000.
/*
 * Turn on what we want
 */
        orr     r0, r0, #0x0031
        orr     r0, r0, #0x2100                 @ ..1. ...1 ..11 ...1
 
#ifndef CONFIG_CPU_DCACHE_DISABLE
        orr     r0, r0, #0x0004                 @ .... .... .... .1..
#endif
#ifndef CONFIG_CPU_ICACHE_DISABLE
        orr     r0, r0, #0x1000                 @ ...1 .... .... ....
#endif
        mov     pc, lr
 
        .text
 
/*
 * Purpose : Function pointers used to access above functions - all calls
 *           come through these
 */
        .type   arm922_processor_functions, #object
arm922_processor_functions:
        .word   cpu_arm922_data_abort
        .word   cpu_arm922_check_bugs
        .word   cpu_arm922_proc_init
        .word   cpu_arm922_proc_fin
        .word   cpu_arm922_reset
        .word   cpu_arm922_do_idle
 
        /* cache */
        .word   cpu_arm922_cache_clean_invalidate_all
        .word   cpu_arm922_cache_clean_invalidate_range
        .word   cpu_arm922_flush_ram_page
 
        /* dcache */
        .word   cpu_arm922_dcache_invalidate_range
        .word   cpu_arm922_dcache_clean_range
        .word   cpu_arm922_dcache_clean_page
        .word   cpu_arm922_dcache_clean_entry
 
        /* icache */
        .word   cpu_arm922_icache_invalidate_range
        .word   cpu_arm922_icache_invalidate_page
 
        /* tlb */
        .word   cpu_arm922_tlb_invalidate_all
        .word   cpu_arm922_tlb_invalidate_range
        .word   cpu_arm922_tlb_invalidate_page
 
        /* pgtable */
        .word   cpu_arm922_set_pgd
        .word   cpu_arm922_set_pmd
        .word   cpu_arm922_set_pte
        .size   arm922_processor_functions, . - arm922_processor_functions
 
        .type   cpu_arm922_info, #object
cpu_arm922_info:
        .long   0
        .long   cpu_arm922_name
        .size   cpu_arm922_info, . - cpu_arm922_info
 
        .type   cpu_arch_name, #object
cpu_arch_name:
        .asciz  "armv4"
        .size   cpu_arch_name, . - cpu_arch_name
 
        .type   cpu_elf_name, #object
cpu_elf_name:
        .asciz  "v4"
        .size   cpu_elf_name, . - cpu_elf_name
        .align
 
        .section ".proc.info", #alloc, #execinstr
 
        .type   __arm922_proc_info,#object
__arm922_proc_info:
        .long   0x41009220
        .long   0xff00fff0
        .long   0x00000c1e                      @ mmuflags
        b       __arm922_setup
        .long   cpu_arch_name
        .long   cpu_elf_name
        .long   HWCAP_SWP | HWCAP_HALF | HWCAP_THUMB
        .long   cpu_arm922_info
        .long   arm922_processor_functions
        .size   __arm922_proc_info, . - __arm922_proc_info

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [arm/] [mm/] [proc-arm922.S] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	1275	phoenix	`/*`
2			`* linux/arch/arm/mm/arm922.S: MMU functions for ARM922`
3			`*`
4			`* Copyright (C) 1999,2000 ARM Limited`
5			`* Copyright (C) 2000 Deep Blue Solutions Ltd.`
6			`* Copyright (C) 2001 Altera Corporation`
7			`*`
8			`* This program is free software; you can redistribute it and/or modify`
9			`* it under the terms of the GNU General Public License as published by`
10			`* the Free Software Foundation; either version 2 of the License, or`
11			`* (at your option) any later version.`
12			`*`
13			`* This program is distributed in the hope that it will be useful,`
14			`* but WITHOUT ANY WARRANTY; without even the implied warranty of`
15			`* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the`
16			`* GNU General Public License for more details.`
17			`*`
18			`* You should have received a copy of the GNU General Public License`
19			`* along with this program; if not, write to the Free Software`
20			`* Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA`
21			`*`
22			`*`
23			`* These are the low level assembler for performing cache and TLB`
24			`* functions on the arm922.`
25			`*/`
26			`#include`
27			`#include`
28			`#include`
29			`#include`
30			`#include`
31			`#include`
32
33			`/*`
34			`* This is the maximum size of an area which will be invalidated`
35			`* using the single invalidate entry instructions. Anything larger`
36			`* than this, and we go for the whole cache.`
37			`*`
38			`* This value should be chosen such that we choose the cheapest`
39			`* alternative.`
40			`*/`
41			`#define MAX_AREA_SIZE 8192`
42
43			`/*`
44			`* the cache line size of the I and D cache`
45			`*/`
46			`#define DCACHELINESIZE 32`
47			`#define ICACHELINESIZE 32`
48
49			`/*`
50			`* and the page size`
51			`*/`
52			`#define PAGESIZE 4096`
53
54			`.text`
55
56			`/*`
57			`* cpu_arm922_data_abort()`
58			`*`
59			`* obtain information about current aborted instruction`
60			`*`
61			`* r0 = address of aborted instruction`
62			`*`
63			`* Returns:`
64			`* r0 = address of abort`
65			`* r1 != 0 if writing`
66			`* r3 = FSR`
67			`*/`
68			`.align 5`
69			`ENTRY(cpu_arm922_data_abort)`
70			`ldr r1, [r0] @ read aborted instruction`
71			`mrc p15, 0, r0, c6, c0, 0 @ get FAR`
72			`tst r1, r1, lsr #21 @ C = bit 20`
73			`mrc p15, 0, r3, c5, c0, 0 @ get FSR`
74			`sbc r1, r1, r1 @ r1 = C - 1`
75			`and r3, r3, #255`
76			`mov pc, lr`
77
78			`/*`
79			`* cpu_arm922_check_bugs()`
80			`*/`
81			`ENTRY(cpu_arm922_check_bugs)`
82			`mrs ip, cpsr`
83			`bic ip, ip, #F_BIT`
84			`msr cpsr, ip`
85			`mov pc, lr`
86
87			`/*`
88			`* cpu_arm922_proc_init()`
89			`*/`
90			`ENTRY(cpu_arm922_proc_init)`
91			`mov pc, lr`
92
93			`/*`
94			`* cpu_arm922_proc_fin()`
95			`*/`
96			`ENTRY(cpu_arm922_proc_fin)`
97			`stmfd sp!, {lr}`
98			`mov ip, #F_BIT \| I_BIT \| SVC_MODE`
99			`msr cpsr_c, ip`
100			`bl cpu_arm922_cache_clean_invalidate_all`
101			`mrc p15, 0, r0, c1, c0, 0 @ ctrl register`
102			`bic r0, r0, #0x1000 @ ...i............`
103			`bic r0, r0, #0x000e @ ............wca.`
104			`mcr p15, 0, r0, c1, c0, 0 @ disable caches`
105			`ldmfd sp!, {pc}`
106
107			`/*`
108			`* cpu_arm922_reset(loc)`
109			`*`
110			`* Perform a soft reset of the system. Put the CPU into the`
111			`* same state as it would be if it had been reset, and branch`
112			`* to what would be the reset vector.`
113			`*`
114			`* loc: location to jump to for soft reset`
115			`*/`
116			`.align 5`
117			`ENTRY(cpu_arm922_reset)`
118			`mov ip, #0`
119			`mcr p15, 0, ip, c7, c7, 0 @ invalidate I,D caches`
120			`mcr p15, 0, ip, c7, c10, 4 @ drain WB`
121			`mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs`
122			`mrc p15, 0, ip, c1, c0, 0 @ ctrl register`
123			`bic ip, ip, #0x000f @ ............wcam`
124			`bic ip, ip, #0x1100 @ ...i...s........`
125			`mcr p15, 0, ip, c1, c0, 0 @ ctrl register`
126			`mov pc, r0`
127
128			`/*`
129			`* cpu_arm922_do_idle()`
130			`*/`
131			`.align 5`
132			`ENTRY(cpu_arm922_do_idle)`
133			`mcr p15, 0, r0, c7, c0, 4 @ Wait for interrupt`
134			`mov pc, lr`
135
136			`/* ================================= CACHE ================================ */`
137
138
139			`/*`
140			`* cpu_arm922_cache_clean_invalidate_all()`
141			`*`
142			`* clean and invalidate all cache lines`
143			`*`
144			`* Note:`
145			`* 1. we should preserve r0 at all times`
146			`*/`
147			`.align 5`
148			`ENTRY(cpu_arm922_cache_clean_invalidate_all)`
149			`mov r2, #1`
150			`cpu_arm922_cache_clean_invalidate_all_r2:`
151			`mov ip, #0`
152			`#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH`
153			`mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache`
154			`#else`
155			`/*`
156			`* 'Clean & Invalidate whole DCache'`
157			`* Re-written to use Index Ops.`
158			`* Uses registers r1, r3 and ip`
159			`*/`
160			`mov r1, #3 << 5 @ 4 segments`
161			`1: orr r3, r1, #63 << 26 @ 64 entries`
162			`2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index`
163			`subs r3, r3, #1 << 26`
164			`bcs 2b @ entries 63 to 0`
165			`subs r1, r1, #1 << 5`
166			`bcs 1b @ segments 7 to 0`
167			`#endif`
168			`teq r2, #0`
169			`mcrne p15, 0, ip, c7, c5, 0 @ invalidate I cache`
170			`mcr p15, 0, ip, c7, c10, 4 @ drain WB`
171			`mov pc, lr`
172
173			`/*`
174			`* cpu_arm922_cache_clean_invalidate_range(start, end, flags)`
175			`*`
176			`* clean and invalidate all cache lines associated with this area of memory`
177			`*`
178			`* start: Area start address`
179			`* end: Area end address`
180			`* flags: nonzero for I cache as well`
181			`*/`
182			`.align 5`
183			`ENTRY(cpu_arm922_cache_clean_invalidate_range)`
184			`bic r0, r0, #DCACHELINESIZE - 1 @ && added by PGM`
185			`bic r1, r1, #DCACHELINESIZE - 1 @ && added by DHM`
186			`sub r3, r1, r0`
187			`cmp r3, #MAX_AREA_SIZE`
188			`bgt cpu_arm922_cache_clean_invalidate_all_r2`
189			`1: teq r2, #0`
190			`#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH`
191			`mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry`
192			`mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry`
193			`add r0, r0, #DCACHELINESIZE`
194			`mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry`
195			`mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry`
196			`add r0, r0, #DCACHELINESIZE`
197			`#else`
198			`mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry`
199			`mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry`
200			`add r0, r0, #DCACHELINESIZE`
201			`mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry`
202			`mcrne p15, 0, r0, c7, c5, 1 @ invalidate I entry`
203			`add r0, r0, #DCACHELINESIZE`
204			`#endif`
205			`cmp r0, r1`
206			`blt 1b`
207
208			`mcr p15, 0, r1, c7, c10, 4 @ drain WB`
209			`mov pc, lr`
210
211			`/*`
212			`* cpu_arm922_flush_ram_page(page)`
213			`*`
214			`* clean and invalidate all cache lines associated with this area of memory`
215			`*`
216			`* page: page to clean and invalidate`
217			`*/`
218			`.align 5`
219			`ENTRY(cpu_arm922_flush_ram_page)`
220			`mov r1, #PAGESIZE`
221			`#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH`
222			`1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry`
223			`add r0, r0, #DCACHELINESIZE`
224			`mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry`
225			`add r0, r0, #DCACHELINESIZE`
226			`#else`
227			`1: mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry`
228			`add r0, r0, #DCACHELINESIZE`
229			`mcr p15, 0, r0, c7, c14, 1 @ clean and invalidate D entry`
230			`add r0, r0, #DCACHELINESIZE`
231			`#endif`
232			`subs r1, r1, #2 * DCACHELINESIZE`
233			`bne 1b`
234			`mcr p15, 0, r1, c7, c10, 4 @ drain WB`
235			`mov pc, lr`
236
237			`/* ================================ D-CACHE =============================== */`
238
239			`/*`
240			`* cpu_arm922_dcache_invalidate_range(start, end)`
241			`*`
242			`* throw away all D-cached data in specified region without an obligation`
243			`* to write them back. Note however that we must clean the D-cached entries`
244			`* around the boundaries if the start and/or end address are not cache`
245			`* aligned.`
246			`*`
247			`* start: virtual start address`
248			`* end: virtual end address`
249			`*/`
250			`.align 5`
251			`ENTRY(cpu_arm922_dcache_invalidate_range)`
252			`#ifndef CONFIG_CPU_ARM922_WRITETHROUGH`
253			`tst r0, #DCACHELINESIZE - 1`
254			`mcrne p15, 0, r0, c7, c10, 1 @ clean D entry`
255			`tst r1, #DCACHELINESIZE - 1`
256			`mcrne p15, 0, r1, c7, c10, 1 @ clean D entry`
257			`#endif @ clean D entry`
258			`bic r0, r0, #DCACHELINESIZE - 1`
259			`bic r1, r1, #DCACHELINESIZE - 1`
260			`1: mcr p15, 0, r0, c7, c6, 1 @ invalidate D entry`
261			`add r0, r0, #DCACHELINESIZE`
262			`cmp r0, r1`
263			`blt 1b`
264			`mov pc, lr`
265
266			`/*`
267			`* cpu_arm922_dcache_clean_range(start, end)`
268			`*`
269			`* For the specified virtual address range, ensure that all caches contain`
270			`* clean data, such that peripheral accesses to the physical RAM fetch`
271			`* correct data.`
272			`*`
273			`* start: virtual start address`
274			`* end: virtual end address`
275			`*/`
276			`.align 5`
277			`ENTRY(cpu_arm922_dcache_clean_range)`
278			`#ifndef CONFIG_CPU_ARM922_WRITETHROUGH`
279			`bic r0, r0, #DCACHELINESIZE - 1`
280			`sub r1, r1, r0`
281			`cmp r1, #MAX_AREA_SIZE`
282			`mov r2, #0`
283			`bgt cpu_arm922_cache_clean_invalidate_all_r2`
284
285			`bic r1, r1, #DCACHELINESIZE -1`
286			`add r1, r1, #DCACHELINESIZE`
287
288			`1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry`
289			`add r0, r0, #DCACHELINESIZE`
290			`subs r1, r1, #DCACHELINESIZE`
291			`bpl 1b`
292			`#endif`
293			`mcr p15, 0, r2, c7, c10, 4 @ drain WB`
294			`mov pc, lr`
295
296			`/*`
297			`* cpu_arm922_dcache_clean_page(page)`
298			`*`
299			`* Cleans a single page of dcache so that if we have any future aliased`
300			`* mappings, they will be consistent at the time that they are created.`
301			`*`
302			`* page: virtual address of page to clean from dcache`
303			`*`
304			`* Note:`
305			`* 1. we don't need to flush the write buffer in this case.`
306			`* 2. we don't invalidate the entries since when we write the page`
307			`* out to disk, the entries may get reloaded into the cache.`
308			`*/`
309			`.align 5`
310			`ENTRY(cpu_arm922_dcache_clean_page)`
311			`#ifndef CONFIG_CPU_ARM922_WRITETHROUGH`
312			`mov r1, #PAGESIZE`
313			`1: mcr p15, 0, r0, c7, c10, 1 @ clean D entry`
314			`add r0, r0, #DCACHELINESIZE`
315			`mcr p15, 0, r0, c7, c10, 1 @ clean D entry`
316			`add r0, r0, #DCACHELINESIZE`
317			`subs r1, r1, #2 * DCACHELINESIZE`
318			`bne 1b`
319			`#endif`
320			`mov pc, lr`
321
322			`/*`
323			`* cpu_arm922_dcache_clean_entry(addr)`
324			`*`
325			`* Clean the specified entry of any caches such that the MMU`
326			`* translation fetches will obtain correct data.`
327			`*`
328			`* addr: cache-unaligned virtual address`
329			`*/`
330			`.align 5`
331			`ENTRY(cpu_arm922_dcache_clean_entry)`
332			`#ifndef CONFIG_CPU_ARM922_WRITETHROUGH`
333			`mcr p15, 0, r0, c7, c10, 1 @ clean D entry`
334			`#endif`
335			`mcr p15, 0, r0, c7, c10, 4 @ drain WB`
336			`mov pc, lr`
337
338			`/* ================================ I-CACHE =============================== */`
339
340			`/*`
341			`* cpu_arm922_icache_invalidate_range(start, end)`
342			`*`
343			`* invalidate a range of virtual addresses from the Icache`
344			`*`
345			`* This is a little misleading, it is not intended to clean out`
346			`* the i-cache but to make sure that any data written to the`
347			`* range is made consistant. This means that when we execute code`
348			`* in that region, everything works as we expect.`
349			`*`
350			`* This generally means writing back data in the Dcache and`
351			`* write buffer and flushing the Icache over that region`
352			`*`
353			`* start: virtual start address`
354			`* end: virtual end address`
355			`*`
356			`* NOTE: ICACHELINESIZE == DCACHELINESIZE (so we don't need to`
357			`* loop twice, once for i-cache, once for d-cache)`
358			`*/`
359			`.align 5`
360			`ENTRY(cpu_arm922_icache_invalidate_range)`
361			`bic r0, r0, #ICACHELINESIZE - 1 @ Safety check`
362			`sub r1, r1, r0`
363			`cmp r1, #MAX_AREA_SIZE`
364			`bgt cpu_arm922_cache_clean_invalidate_all_r2`
365
366			`bic r1, r1, #ICACHELINESIZE - 1`
367			`add r1, r1, #ICACHELINESIZE`
368
369			`1: mcr p15, 0, r0, c7, c5, 1 @ Clean I entry`
370			`mcr p15, 0, r0, c7, c10, 1 @ Clean D entry`
371			`add r0, r0, #ICACHELINESIZE`
372			`subs r1, r1, #ICACHELINESIZE`
373			`bne 1b`
374
375			`mov r0, #0`
376			`mcr p15, 0, r0, c7, c10, 4 @ drain WB`
377			`mov pc, lr`
378
379			`ENTRY(cpu_arm922_icache_invalidate_page)`
380			`mcr p15, 0, r0, c7, c5, 0 @ invalidate I cache`
381			`mov pc, lr`
382
383			`/* ================================== TLB ================================= */`
384
385			`/*`
386			`* cpu_arm922_tlb_invalidate_all()`
387			`*`
388			`* Invalidate all TLB entries`
389			`*/`
390			`.align 5`
391			`ENTRY(cpu_arm922_tlb_invalidate_all)`
392			`mov r0, #0`
393			`mcr p15, 0, r0, c7, c10, 4 @ drain WB`
394			`mcr p15, 0, r0, c8, c7, 0 @ invalidate I & D TLBs`
395			`mov pc, lr`
396
397			`/*`
398			`* cpu_arm922_tlb_invalidate_range(start, end)`
399			`*`
400			`* invalidate TLB entries covering the specified range`
401			`*`
402			`* start: range start address`
403			`* end: range end address`
404			`*/`
405			`.align 5`
406			`ENTRY(cpu_arm922_tlb_invalidate_range)`
407			`sub r3, r1, r0`
408			`cmp r3, #256 * PAGESIZE @ arbitary, should be tuned`
409			`bhi cpu_arm922_tlb_invalidate_all`
410
411			`mov r3, #0`
412			`mcr p15, 0, r3, c7, c10, 4 @ drain WB`
413
414			`mov r3, #PAGESIZE`
415			`sub r3, r3, #1`
416			`bic r0, r0, r3`
417			`bic r1, r1, r3`
418
419			`1: mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry`
420			`mcr p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry`
421			`add r0, r0, #PAGESIZE`
422			`cmp r0, r1`
423			`blt 1b`
424			`mov pc, lr`
425
426			`/*`
427			`* cpu_arm922_tlb_invalidate_page(page, flags)`
428			`*`
429			`* invalidate the TLB entries for the specified page.`
430			`*`
431			`* page: page to invalidate`
432			`* flags: non-zero if we include the I TLB`
433			`*/`
434			`.align 5`
435			`ENTRY(cpu_arm922_tlb_invalidate_page)`
436			`mov r3, #0`
437			`mcr p15, 0, r3, c7, c10, 4 @ drain WB`
438			`teq r1, #0`
439			`mcr p15, 0, r0, c8, c6, 1 @ invalidate D TLB entry`
440			`mcrne p15, 0, r0, c8, c5, 1 @ invalidate I TLB entry`
441			`mov pc, lr`
442
443			`/* =============================== PageTable ============================== */`
444
445			`/*`
446			`* cpu_arm922_set_pgd(pgd)`
447			`*`
448			`* Set the translation base pointer to be as described by pgd.`
449			`*`
450			`* pgd: new page tables`
451			`*/`
452			`.align 5`
453			`ENTRY(cpu_arm922_set_pgd)`
454			`mov ip, #0`
455			`#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH`
456			`/* Any reason why we don't use mcr p15, 0, r0, c7, c7, 0 here? --rmk */`
457			`mcr p15, 0, ip, c7, c6, 0 @ invalidate D cache`
458			`#else`
459			`@ && 'Clean & Invalidate whole DCache'`
460			`@ && Re-written to use Index Ops.`
461			`@ && Uses registers r1, r3 and ip`
462
463			`mov r1, #3 << 5 @ 4 segments`
464			`1: orr r3, r1, #63 << 26 @ 64 entries`
465			`2: mcr p15, 0, r3, c7, c14, 2 @ clean & invalidate D index`
466			`subs r3, r3, #1 << 26`
467			`bcs 2b @ entries 63 to 0`
468			`subs r1, r1, #1 << 5`
469			`bcs 1b @ segments 7 to 0`
470			`#endif`
471			`mcr p15, 0, ip, c7, c5, 0 @ invalidate I cache`
472			`mcr p15, 0, ip, c7, c10, 4 @ drain WB`
473			`mcr p15, 0, r0, c2, c0, 0 @ load page table pointer`
474			`mcr p15, 0, ip, c8, c7, 0 @ invalidate I & D TLBs`
475			`mov pc, lr`
476
477			`/*`
478			`* cpu_arm922_set_pmd(pmdp, pmd)`
479			`*`
480			`* Set a level 1 translation table entry, and clean it out of`
481			`* any caches such that the MMUs can load it correctly.`
482			`*`
483			`* pmdp: pointer to PMD entry`
484			`* pmd: PMD value to store`
485			`*/`
486			`.align 5`
487			`ENTRY(cpu_arm922_set_pmd)`
488			`#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH`
489			`eor r2, r1, #0x0a @ C & Section`
490			`tst r2, #0x0b`
491			`biceq r1, r1, #4 @ clear bufferable bit`
492			`#endif`
493			`str r1, [r0]`
494			`mcr p15, 0, r0, c7, c10, 1 @ clean D entry`
495			`mcr p15, 0, r0, c7, c10, 4 @ drain WB`
496			`mov pc, lr`
497
498			`/*`
499			`* cpu_arm922_set_pte(ptep, pte)`
500			`*`
501			`* Set a PTE and flush it out`
502			`*/`
503			`.align 5`
504			`ENTRY(cpu_arm922_set_pte)`
505			`str r1, [r0], #-1024 @ linux version`
506
507			`eor r1, r1, #LPTE_PRESENT \| LPTE_YOUNG \| LPTE_WRITE \| LPTE_DIRTY`
508
509			`bic r2, r1, #0xff0`
510			`bic r2, r2, #3`
511			`orr r2, r2, #HPTE_TYPE_SMALL`
512
513			`tst r1, #LPTE_USER \| LPTE_EXEC @ User or Exec?`
514			`orrne r2, r2, #HPTE_AP_READ`
515
516			`tst r1, #LPTE_WRITE \| LPTE_DIRTY @ Write and Dirty?`
517			`orreq r2, r2, #HPTE_AP_WRITE`
518
519			`tst r1, #LPTE_PRESENT \| LPTE_YOUNG @ Present and Young?`
520			`movne r2, #0`
521
522			`#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH`
523			`eor r3, r2, #0x0a @ C & small page?`
524			`tst r3, #0x0b`
525			`biceq r2, r2, #4`
526			`#endif`
527			`str r2, [r0] @ hardware version`
528			`mov r0, r0`
529			`mcr p15, 0, r0, c7, c10, 1 @ clean D entry`
530			`mcr p15, 0, r0, c7, c10, 4 @ drain WB`
531			`mov pc, lr`
532
533
534			`ENTRY(cpu_arm922_name)`
535			`.ascii "Arm922T"`
536			`#ifndef CONFIG_CPU_ICACHE_DISABLE`
537			`.ascii "i"`
538			`#endif`
539			`#ifndef CONFIG_CPU_DCACHE_DISABLE`
540			`.ascii "d"`
541			`#ifdef CONFIG_CPU_DCACHE_WRITETHROUGH`
542			`.ascii "(wt)"`
543			`#else`
544			`.ascii "(wb)"`
545			`#endif`
546			`#endif`
547			`.ascii "\0"`
548			`.align`
549
550			`.section ".text.init", #alloc, #execinstr`
551
552			`__arm922_setup:`
553			`mov r0, #0`
554			`mcr p15, 0, r0, c7, c7 @ invalidate I,D caches on v4`
555			`mcr p15, 0, r0, c7, c10, 4 @ drain write buffer on v4`
556			`mcr p15, 0, r0, c8, c7 @ invalidate I,D TLBs on v4`
557			`mcr p15, 0, r4, c2, c0 @ load page table pointer`
558			`mov r0, #0x1f @ Domains 0, 1 = client`
559			`mcr p15, 0, r0, c3, c0 @ load domain access register`
560			`mrc p15, 0, r0, c1, c0 @ get control register v4`
561			`/*`
562			`* Clear out 'unwanted' bits (then put them in if we need them)`
563			`*/`
564			`@ VI ZFRS BLDP WCAM`
565			`bic r0, r0, #0x0e00`
566			`bic r0, r0, #0x0002`
567			`bic r0, r0, #0x000c`
568			`bic r0, r0, #0x1000 @ ...0 000. .... 000.`
569			`/*`
570			`* Turn on what we want`
571			`*/`
572			`orr r0, r0, #0x0031`
573			`orr r0, r0, #0x2100 @ ..1. ...1 ..11 ...1`
574
575			`#ifndef CONFIG_CPU_DCACHE_DISABLE`
576			`orr r0, r0, #0x0004 @ .... .... .... .1..`
577			`#endif`
578			`#ifndef CONFIG_CPU_ICACHE_DISABLE`
579			`orr r0, r0, #0x1000 @ ...1 .... .... ....`
580			`#endif`
581			`mov pc, lr`
582
583			`.text`
584
585			`/*`
586			`* Purpose : Function pointers used to access above functions - all calls`
587			`* come through these`
588			`*/`
589			`.type arm922_processor_functions, #object`
590			`arm922_processor_functions:`
591			`.word cpu_arm922_data_abort`
592			`.word cpu_arm922_check_bugs`
593			`.word cpu_arm922_proc_init`
594			`.word cpu_arm922_proc_fin`
595			`.word cpu_arm922_reset`
596			`.word cpu_arm922_do_idle`
597
598			`/* cache */`
599			`.word cpu_arm922_cache_clean_invalidate_all`
600			`.word cpu_arm922_cache_clean_invalidate_range`
601			`.word cpu_arm922_flush_ram_page`
602
603			`/* dcache */`
604			`.word cpu_arm922_dcache_invalidate_range`
605			`.word cpu_arm922_dcache_clean_range`
606			`.word cpu_arm922_dcache_clean_page`
607			`.word cpu_arm922_dcache_clean_entry`
608
609			`/* icache */`
610			`.word cpu_arm922_icache_invalidate_range`
611			`.word cpu_arm922_icache_invalidate_page`
612
613			`/* tlb */`
614			`.word cpu_arm922_tlb_invalidate_all`
615			`.word cpu_arm922_tlb_invalidate_range`
616			`.word cpu_arm922_tlb_invalidate_page`
617
618			`/* pgtable */`
619			`.word cpu_arm922_set_pgd`
620			`.word cpu_arm922_set_pmd`
621			`.word cpu_arm922_set_pte`
622			`.size arm922_processor_functions, . - arm922_processor_functions`
623
624			`.type cpu_arm922_info, #object`
625			`cpu_arm922_info:`
626			`.long 0`
627			`.long cpu_arm922_name`
628			`.size cpu_arm922_info, . - cpu_arm922_info`
629
630			`.type cpu_arch_name, #object`
631			`cpu_arch_name:`
632			`.asciz "armv4"`
633			`.size cpu_arch_name, . - cpu_arch_name`
634
635			`.type cpu_elf_name, #object`
636			`cpu_elf_name:`
637			`.asciz "v4"`
638			`.size cpu_elf_name, . - cpu_elf_name`
639			`.align`
640
641			`.section ".proc.info", #alloc, #execinstr`
642
643			`.type __arm922_proc_info,#object`
644			`__arm922_proc_info:`
645			`.long 0x41009220`
646			`.long 0xff00fff0`
647			`.long 0x00000c1e @ mmuflags`
648			`b __arm922_setup`
649			`.long cpu_arch_name`
650			`.long cpu_elf_name`
651			`.long HWCAP_SWP \| HWCAP_HALF \| HWCAP_THUMB`
652			`.long cpu_arm922_info`
653			`.long arm922_processor_functions`
654			`.size __arm922_proc_info, . - __arm922_proc_info`