1 |
1275 |
phoenix |
/*
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* Parallel port driver for ETRAX.
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*
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* NOTE!
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* Since par0 shares DMA with ser2 and par 1 shares DMA with ser3
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* this should be handled if both are enabled at the same time.
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* THIS IS NOT HANDLED YET!
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*
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* Copyright (c) 2001, 2002, 2003 Axis Communications AB
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*
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* Author: Fredrik Hugosson
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*
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*/
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#include <linux/module.h>
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#include <linux/init.h>
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#include <linux/parport.h>
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#include <linux/ioport.h>
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#include <linux/config.h>
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#include <linux/errno.h>
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#include <linux/kernel.h>
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#include <linux/major.h>
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#include <linux/sched.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <asm/setup.h>
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#include <asm/irq.h>
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#include <asm/io.h>
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#include <asm/segment.h>
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#include <asm/system.h>
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#include <asm/svinto.h>
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#undef DEBUG
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#ifdef DEBUG
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#define DPRINTK printk
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#else
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static inline int DPRINTK(void *nothing, ...) {return 0;}
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#endif
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/*
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* Etrax100 DMAchannels:
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* Par0 out : DMA2
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* Par0 in : DMA3
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* Par1 out : DMA4
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* Par1 in : DMA5
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* NOTE! par0 is shared with ser2 and par1 is shared with ser3 regarding
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* DMA and DMA irq
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*/
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//#define CONFIG_PAR0_INT 1
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//#define CONFIG_PAR1_INT 1
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/* Define some macros to access ETRAX 100 registers */
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#define SETF(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
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IO_FIELD_(reg##_, field##_, val)
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#define SETS(var, reg, field, val) var = (var & ~IO_MASK_(reg##_, field##_)) | \
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IO_STATE_(reg##_, field##_, _##val)
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struct etrax100par_struct {
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/* parallell port control */
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volatile u32 *reg_ctrl_data; /* R_PARx_CTRL_DATA */
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const volatile u32 *reg_status_data; /* R_PARx_STATUS_DATA */
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volatile u32 *reg_config; /* R_PARx_CONFIG */
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volatile u32 *reg_delay; /* R_PARx_DELAY */
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/* DMA control */
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int odma;
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unsigned long dma_irq; /* bitnr in R_IRQ_MASK2 for dmaX_descr */
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volatile char *oclrintradr; /* adr to R_DMA_CHx_CLR_INTR, output */
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volatile u32 *ofirstadr; /* adr to R_DMA_CHx_FIRST, output */
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volatile char *ocmdadr; /* adr to R_DMA_CHx_CMD, output */
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volatile char *iclrintradr; /* adr to R_DMA_CHx_CLR_INTR, input */
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volatile u32 *ifirstadr; /* adr to R_DMA_CHx_FIRST, input */
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volatile char *icmdadr; /* adr to R_DMA_CHx_CMD, input */
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/* Non DMA interrupt stuff */
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unsigned long int_irq; /* R_VECT_MASK_RD */
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const volatile u32 *irq_mask_rd; /* R_IRQ_MASKX_RD */
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volatile u32 *irq_mask_clr; /* R_IRQ_MASKX_RD */
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const volatile u32 *irq_read; /* R_IRQ_READX */
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volatile u32 *irq_mask_set; /* R_IRQ_MASKX_SET */
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unsigned long irq_mask_tx; /* bitmask in R_IRQ_ for tx (ready) int */
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unsigned long irq_mask_rx; /* bitmask in R_IRQ_ for rx (data) int */
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unsigned long irq_mask_ecp_cmd; /* mask in R_IRQ_ for ecp_cmd int */
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unsigned long irq_mask_peri; /* bitmask in R_IRQ_ for peri int */
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int portnr;
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/* ----- end of fields initialised in port_table[] below ----- */
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struct parport *port;
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/* Shadow registers */
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volatile unsigned long reg_ctrl_data_shadow; /* for R_PARx_CTRL_DATA */
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volatile unsigned long reg_config_shadow; /* for R_PARx_CONFIG */
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volatile unsigned long reg_delay_shadow; /* for R_PARx_DELAY */
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};
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/* Always have the complete structs here, even if the port is not used!
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* (that way we can index this by the port number)
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*/
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static struct etrax100par_struct port_table[] = {
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{
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R_PAR0_CTRL_DATA,
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R_PAR0_STATUS_DATA,
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R_PAR0_CONFIG,
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R_PAR0_DELAY,
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/* DMA interrupt stuff */
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2,
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1U << 4, /* uses DMA 2 and 3 */
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R_DMA_CH2_CLR_INTR,
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R_DMA_CH2_FIRST,
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R_DMA_CH2_CMD,
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R_DMA_CH3_CLR_INTR,
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R_DMA_CH3_FIRST,
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R_DMA_CH3_CMD,
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/* Non DMA interrupt stuff */
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IO_BITNR(R_VECT_MASK_RD, par0),
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R_IRQ_MASK0_RD,
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R_IRQ_MASK0_CLR,
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R_IRQ_READ0,
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R_IRQ_MASK0_SET,
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IO_FIELD(R_IRQ_MASK0_RD, par0_ready, 1U), /* tx (ready)*/
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IO_FIELD(R_IRQ_MASK0_RD, par0_data, 1U), /* rx (data)*/
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IO_FIELD(R_IRQ_MASK0_RD, par0_ecp_cmd, 1U), /* ecp_cmd */
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IO_FIELD(R_IRQ_MASK0_RD, par0_peri, 1U), /* peri */
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},
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{
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R_PAR1_CTRL_DATA,
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R_PAR1_STATUS_DATA,
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R_PAR1_CONFIG,
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R_PAR1_DELAY,
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/* DMA interrupt stuff */
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4,
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1U << 8, /* uses DMA 4 and 5 */
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R_DMA_CH4_CLR_INTR,
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R_DMA_CH4_FIRST,
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R_DMA_CH4_CMD,
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R_DMA_CH5_CLR_INTR,
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R_DMA_CH5_FIRST,
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R_DMA_CH5_CMD,
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/* Non DMA interrupt stuff */
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IO_BITNR(R_VECT_MASK_RD, par1),
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R_IRQ_MASK1_RD,
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R_IRQ_MASK1_CLR,
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R_IRQ_READ1,
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R_IRQ_MASK1_SET,
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IO_FIELD(R_IRQ_MASK1_RD, par1_ready, 1U), /* tx (ready)*/
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IO_FIELD(R_IRQ_MASK1_RD, par1_data, 1U), /* rx (data)*/
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IO_FIELD(R_IRQ_MASK1_RD, par1_ecp_cmd, 1U), /* ecp_cmd */
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IO_FIELD(R_IRQ_MASK1_RD, par1_peri, 1U), /* peri */
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1
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}
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};
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#define NR_PORTS (sizeof(port_table)/sizeof(struct etrax100par_struct))
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static void
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parport_etrax_write_data(struct parport *p, unsigned char value)
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{
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struct etrax100par_struct *info =
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(struct etrax100par_struct *)p->private_data;
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DPRINTK("* E100 PP %d: etrax_write_data %02X\n", p->portnum, value);
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SETF(info->reg_ctrl_data_shadow, R_PAR0_CTRL_DATA, data, value);
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*info->reg_ctrl_data = info->reg_ctrl_data_shadow;
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}
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static unsigned char
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parport_etrax_read_data(struct parport *p)
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{
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unsigned char ret;
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struct etrax100par_struct *info =
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(struct etrax100par_struct *)p->private_data;
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ret = IO_EXTRACT(R_PAR0_STATUS_DATA, data, *info->reg_status_data);
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DPRINTK("* E100 PP %d: etrax_read_data %02X\n", p->portnum, ret);
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return ret;
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}
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static void
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parport_etrax_write_control(struct parport *p, unsigned char control)
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{
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struct etrax100par_struct *info =
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(struct etrax100par_struct *)p->private_data;
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DPRINTK("* E100 PP %d: etrax_write_control %02x\n", p->portnum, control);
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SETF(info->reg_ctrl_data_shadow, R_PAR0_CTRL_DATA, strb,
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(control & PARPORT_CONTROL_STROBE) > 0);
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SETF(info->reg_ctrl_data_shadow, R_PAR0_CTRL_DATA, autofd,
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(control & PARPORT_CONTROL_AUTOFD) > 0);
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SETF(info->reg_ctrl_data_shadow, R_PAR0_CTRL_DATA, init,
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(control & PARPORT_CONTROL_INIT) == 0);
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SETF(info->reg_ctrl_data_shadow, R_PAR0_CTRL_DATA, seli,
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(control & PARPORT_CONTROL_SELECT) > 0);
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*info->reg_ctrl_data = info->reg_ctrl_data_shadow;
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}
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static unsigned char
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parport_etrax_read_control( struct parport *p)
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{
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unsigned char ret = 0;
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struct etrax100par_struct *info =
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(struct etrax100par_struct *)p->private_data;
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if (IO_EXTRACT(R_PAR0_CTRL_DATA, strb, info->reg_ctrl_data_shadow))
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ret |= PARPORT_CONTROL_STROBE;
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if (IO_EXTRACT(R_PAR0_CTRL_DATA, autofd, info->reg_ctrl_data_shadow))
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ret |= PARPORT_CONTROL_AUTOFD;
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if (!IO_EXTRACT(R_PAR0_CTRL_DATA, init, info->reg_ctrl_data_shadow))
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ret |= PARPORT_CONTROL_INIT;
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if (IO_EXTRACT(R_PAR0_CTRL_DATA, seli, info->reg_ctrl_data_shadow))
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ret |= PARPORT_CONTROL_SELECT;
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DPRINTK("* E100 PP %d: etrax_read_control %02x\n", p->portnum, ret);
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return ret;
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}
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static unsigned char
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parport_etrax_frob_control(struct parport *p, unsigned char mask,
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unsigned char val)
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{
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unsigned char old;
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DPRINTK("* E100 PP %d: frob_control mask %02x, value %02x\n",
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p->portnum, mask, val);
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old = parport_etrax_read_control(p);
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parport_etrax_write_control(p, (old & ~mask) ^ val);
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return old;
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}
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static unsigned char
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parport_etrax_read_status(struct parport *p)
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{
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unsigned char ret = 0;
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struct etrax100par_struct *info =
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(struct etrax100par_struct *)p->private_data;
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if (IO_EXTRACT(R_PAR0_STATUS_DATA, fault, *info->reg_status_data))
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ret |= PARPORT_STATUS_ERROR;
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if (IO_EXTRACT(R_PAR0_STATUS_DATA, sel, *info->reg_status_data))
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ret |= PARPORT_STATUS_SELECT;
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if (IO_EXTRACT(R_PAR0_STATUS_DATA, perr, *info->reg_status_data))
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ret |= PARPORT_STATUS_PAPEROUT;
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if (IO_EXTRACT(R_PAR0_STATUS_DATA, ack, *info->reg_status_data))
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ret |= PARPORT_STATUS_ACK;
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if (!IO_EXTRACT(R_PAR0_STATUS_DATA, busy, *info->reg_status_data))
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ret |= PARPORT_STATUS_BUSY;
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DPRINTK("* E100 PP %d: status register %04x\n",
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p->portnum, *info->reg_status_data);
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DPRINTK("* E100 PP %d: read_status %02x\n", p->portnum, ret);
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return ret;
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}
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static void
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parport_etrax_enable_irq(struct parport *p)
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{
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struct etrax100par_struct *info =
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(struct etrax100par_struct *)p->private_data;
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*info->irq_mask_set = info->irq_mask_tx;
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DPRINTK("* E100 PP %d: enable irq\n", p->portnum);
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}
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static void
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parport_etrax_disable_irq(struct parport *p)
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{
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struct etrax100par_struct *info =
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(struct etrax100par_struct *)p->private_data;
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*info->irq_mask_clr = info->irq_mask_tx;
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DPRINTK("* E100 PP %d: disable irq\n", p->portnum);
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}
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static void
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parport_etrax_data_forward(struct parport *p)
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{
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298 |
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struct etrax100par_struct *info =
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(struct etrax100par_struct *)p->private_data;
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301 |
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DPRINTK("* E100 PP %d: forward mode\n", p->portnum);
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SETS(info->reg_ctrl_data_shadow, R_PAR0_CTRL_DATA, oe, enable);
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*info->reg_ctrl_data = info->reg_ctrl_data_shadow;
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}
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306 |
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307 |
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static void
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308 |
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parport_etrax_data_reverse(struct parport *p)
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{
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310 |
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struct etrax100par_struct *info =
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(struct etrax100par_struct *)p->private_data;
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312 |
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313 |
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DPRINTK("* E100 PP %d: reverse mode\n", p->portnum);
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314 |
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SETS(info->reg_ctrl_data_shadow, R_PAR0_CTRL_DATA, oe, disable);
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*info->reg_ctrl_data = info->reg_ctrl_data_shadow;
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}
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317 |
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318 |
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319 |
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static void
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320 |
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parport_etrax_init_state(struct pardevice *dev, struct parport_state *s)
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321 |
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{
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322 |
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DPRINTK("* E100 PP: parport_etrax_init_state\n");
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}
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325 |
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326 |
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static void
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327 |
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parport_etrax_save_state(struct parport *p, struct parport_state *s)
|
328 |
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{
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329 |
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DPRINTK("* E100 PP: parport_etrax_save_state\n");
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330 |
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}
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331 |
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332 |
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333 |
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static void
|
334 |
|
|
parport_etrax_restore_state(struct parport *p, struct parport_state *s)
|
335 |
|
|
{
|
336 |
|
|
DPRINTK("* E100 PP: parport_etrax_restore_state\n");
|
337 |
|
|
}
|
338 |
|
|
|
339 |
|
|
|
340 |
|
|
static void
|
341 |
|
|
parport_etrax_inc_use_count(void)
|
342 |
|
|
{
|
343 |
|
|
MOD_INC_USE_COUNT;
|
344 |
|
|
}
|
345 |
|
|
|
346 |
|
|
|
347 |
|
|
static void
|
348 |
|
|
parport_etrax_dec_use_count(void)
|
349 |
|
|
{
|
350 |
|
|
MOD_DEC_USE_COUNT;
|
351 |
|
|
}
|
352 |
|
|
|
353 |
|
|
|
354 |
|
|
static struct
|
355 |
|
|
parport_operations pp_etrax_ops = {
|
356 |
|
|
parport_etrax_write_data,
|
357 |
|
|
parport_etrax_read_data,
|
358 |
|
|
|
359 |
|
|
parport_etrax_write_control,
|
360 |
|
|
parport_etrax_read_control,
|
361 |
|
|
parport_etrax_frob_control,
|
362 |
|
|
|
363 |
|
|
parport_etrax_read_status,
|
364 |
|
|
|
365 |
|
|
parport_etrax_enable_irq,
|
366 |
|
|
parport_etrax_disable_irq,
|
367 |
|
|
|
368 |
|
|
parport_etrax_data_forward,
|
369 |
|
|
parport_etrax_data_reverse,
|
370 |
|
|
|
371 |
|
|
parport_etrax_init_state,
|
372 |
|
|
parport_etrax_save_state,
|
373 |
|
|
parport_etrax_restore_state,
|
374 |
|
|
|
375 |
|
|
parport_etrax_inc_use_count,
|
376 |
|
|
parport_etrax_dec_use_count,
|
377 |
|
|
|
378 |
|
|
parport_ieee1284_epp_write_data,
|
379 |
|
|
parport_ieee1284_epp_read_data,
|
380 |
|
|
parport_ieee1284_epp_write_addr,
|
381 |
|
|
parport_ieee1284_epp_read_addr,
|
382 |
|
|
|
383 |
|
|
parport_ieee1284_ecp_write_data,
|
384 |
|
|
parport_ieee1284_ecp_read_data,
|
385 |
|
|
parport_ieee1284_ecp_write_addr,
|
386 |
|
|
|
387 |
|
|
parport_ieee1284_write_compat,
|
388 |
|
|
parport_ieee1284_read_nibble,
|
389 |
|
|
parport_ieee1284_read_byte,
|
390 |
|
|
};
|
391 |
|
|
|
392 |
|
|
|
393 |
|
|
static void
|
394 |
|
|
parport_etrax_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
395 |
|
|
{
|
396 |
|
|
struct etrax100par_struct *info = (struct etrax100par_struct *)
|
397 |
|
|
((struct parport *)dev_id)->private_data;
|
398 |
|
|
DPRINTK("* E100 PP %d: Interrupt received\n",
|
399 |
|
|
((struct parport *)dev_id)->portnum);
|
400 |
|
|
*info->irq_mask_clr = info->irq_mask_tx;
|
401 |
|
|
parport_generic_irq(irq, (struct parport *)dev_id, regs);
|
402 |
|
|
}
|
403 |
|
|
|
404 |
|
|
/* ----------- Initialisation code --------------------------------- */
|
405 |
|
|
|
406 |
|
|
static void __init
|
407 |
|
|
parport_etrax_show_parallel_version(void)
|
408 |
|
|
{
|
409 |
|
|
printk("ETRAX 100LX parallel port driver v1.0, (c) 2001-2003 Axis Communications AB\n");
|
410 |
|
|
}
|
411 |
|
|
|
412 |
|
|
#ifdef CONFIG_ETRAX_PAR0_DMA
|
413 |
|
|
#define PAR0_USE_DMA 1
|
414 |
|
|
#else
|
415 |
|
|
#define PAR0_USE_DMA 0
|
416 |
|
|
#endif
|
417 |
|
|
|
418 |
|
|
#ifdef CONFIG_ETRAX_PAR1_DMA
|
419 |
|
|
#define PAR1_USE_DMA 1
|
420 |
|
|
#else
|
421 |
|
|
#define PAR1_USE_DMA 0
|
422 |
|
|
#endif
|
423 |
|
|
|
424 |
|
|
static void __init
|
425 |
|
|
parport_etrax_init_registers(void)
|
426 |
|
|
{
|
427 |
|
|
struct etrax100par_struct *info;
|
428 |
|
|
int i;
|
429 |
|
|
|
430 |
|
|
for (i = 0, info = port_table; i < 2; i++, info++) {
|
431 |
|
|
#ifndef CONFIG_ETRAX_PARALLEL_PORT0
|
432 |
|
|
if (i == 0)
|
433 |
|
|
continue;
|
434 |
|
|
#endif
|
435 |
|
|
#ifndef CONFIG_ETRAX_PARALLEL_PORT1
|
436 |
|
|
if (i == 1)
|
437 |
|
|
continue;
|
438 |
|
|
#endif
|
439 |
|
|
info->reg_config_shadow =
|
440 |
|
|
IO_STATE(R_PAR0_CONFIG, iseli, inv) |
|
441 |
|
|
IO_STATE(R_PAR0_CONFIG, iautofd, inv) |
|
442 |
|
|
IO_STATE(R_PAR0_CONFIG, istrb, inv) |
|
443 |
|
|
IO_STATE(R_PAR0_CONFIG, iinit, inv) |
|
444 |
|
|
IO_STATE(R_PAR0_CONFIG, rle_in, disable) |
|
445 |
|
|
IO_STATE(R_PAR0_CONFIG, rle_out, disable) |
|
446 |
|
|
IO_STATE(R_PAR0_CONFIG, enable, on) |
|
447 |
|
|
IO_STATE(R_PAR0_CONFIG, force, off) |
|
448 |
|
|
IO_STATE(R_PAR0_CONFIG, ign_ack, wait) |
|
449 |
|
|
IO_STATE(R_PAR0_CONFIG, oe_ack, wait_oe) |
|
450 |
|
|
IO_STATE(R_PAR0_CONFIG, mode, manual);
|
451 |
|
|
|
452 |
|
|
if ((i == 0 && PAR0_USE_DMA) || (i == 1 && PAR1_USE_DMA))
|
453 |
|
|
info->reg_config_shadow |=
|
454 |
|
|
IO_STATE(R_PAR0_CONFIG, dma, enable);
|
455 |
|
|
else
|
456 |
|
|
info->reg_config_shadow |=
|
457 |
|
|
IO_STATE(R_PAR0_CONFIG, dma, disable);
|
458 |
|
|
|
459 |
|
|
*info->reg_config = info->reg_config_shadow;
|
460 |
|
|
|
461 |
|
|
info->reg_ctrl_data_shadow =
|
462 |
|
|
IO_STATE(R_PAR0_CTRL_DATA, peri_int, nop) |
|
463 |
|
|
IO_STATE(R_PAR0_CTRL_DATA, oe, enable) |
|
464 |
|
|
IO_STATE(R_PAR0_CTRL_DATA, seli, inactive) |
|
465 |
|
|
IO_STATE(R_PAR0_CTRL_DATA, autofd, inactive) |
|
466 |
|
|
IO_STATE(R_PAR0_CTRL_DATA, strb, inactive) |
|
467 |
|
|
IO_STATE(R_PAR0_CTRL_DATA, init, inactive) |
|
468 |
|
|
IO_STATE(R_PAR0_CTRL_DATA, ecp_cmd, data) |
|
469 |
|
|
IO_FIELD(R_PAR0_CTRL_DATA, data, 0);
|
470 |
|
|
*info->reg_ctrl_data = info->reg_ctrl_data_shadow;
|
471 |
|
|
|
472 |
|
|
/* Clear peri int without setting shadow */
|
473 |
|
|
*info->reg_ctrl_data = info->reg_ctrl_data_shadow |
|
474 |
|
|
IO_STATE(R_PAR0_CTRL_DATA, peri_int, ack);
|
475 |
|
|
|
476 |
|
|
info->reg_delay_shadow =
|
477 |
|
|
IO_FIELD(R_PAR0_DELAY, setup, 5) |
|
478 |
|
|
IO_FIELD(R_PAR0_DELAY, strobe, 5) |
|
479 |
|
|
IO_FIELD(R_PAR0_DELAY, hold, 5);
|
480 |
|
|
*info->reg_delay = info->reg_delay_shadow;
|
481 |
|
|
}
|
482 |
|
|
|
483 |
|
|
#ifdef CONFIG_ETRAX_PARALLEL_PORT0
|
484 |
|
|
#ifdef CONFIG_ETRAX_PAR0_DMA
|
485 |
|
|
RESET_DMA(PAR0_TX_DMA_NBR);
|
486 |
|
|
WAIT_DMA(PAR0_TX_DMA_NBR);
|
487 |
|
|
#ifdef CONFIG_ETRAX_SERIAL_PORT2
|
488 |
|
|
printk(" Warning - DMA clash with ser2!\n");
|
489 |
|
|
#endif /* SERIAL_PORT2 */
|
490 |
|
|
#endif /* DMA */
|
491 |
|
|
#endif /* PORT0 */
|
492 |
|
|
|
493 |
|
|
#ifdef CONFIG_ETRAX_PARALLEL_PORT1
|
494 |
|
|
#ifdef CONFIG_ETRAX_PAR1_DMA
|
495 |
|
|
RESET_DMA(PAR1_TX_DMA_NBR);
|
496 |
|
|
WAIT_DMA(PAR1_TX_DMA_NBR);
|
497 |
|
|
#ifdef CONFIG_ETRAX_SERIAL_PORT3
|
498 |
|
|
printk(" Warning - DMA clash with ser3!\n");
|
499 |
|
|
#endif /* SERIAL_PORT3 */
|
500 |
|
|
#endif /* DMA */
|
501 |
|
|
#endif /* PORT1 */
|
502 |
|
|
}
|
503 |
|
|
|
504 |
|
|
|
505 |
|
|
int __init
|
506 |
|
|
parport_etrax_init(void)
|
507 |
|
|
{
|
508 |
|
|
struct parport *p;
|
509 |
|
|
int port_exists = 0;
|
510 |
|
|
int i;
|
511 |
|
|
struct etrax100par_struct *info;
|
512 |
|
|
const char *names[] = { "parallel 0 tx+rx", "parallel 1 tx+rx" };
|
513 |
|
|
|
514 |
|
|
parport_etrax_show_parallel_version();
|
515 |
|
|
parport_etrax_init_registers();
|
516 |
|
|
|
517 |
|
|
for (i = 0, info = port_table; i < NR_PORTS; i++, info++) {
|
518 |
|
|
#ifndef CONFIG_ETRAX_PARALLEL_PORT0
|
519 |
|
|
if (i == 0)
|
520 |
|
|
continue;
|
521 |
|
|
#endif
|
522 |
|
|
#ifndef CONFIG_ETRAX_PARALLEL_PORT1
|
523 |
|
|
if (i == 1)
|
524 |
|
|
continue;
|
525 |
|
|
#endif
|
526 |
|
|
p = parport_register_port((unsigned long)0, info->int_irq,
|
527 |
|
|
PARPORT_DMA_NONE, &pp_etrax_ops);
|
528 |
|
|
if (!p)
|
529 |
|
|
continue;
|
530 |
|
|
|
531 |
|
|
info->port = p;
|
532 |
|
|
p->private_data = info;
|
533 |
|
|
/* Axis FIXME: Set mode flags. */
|
534 |
|
|
/* p->modes = PARPORT_MODE_TRISTATE | PARPORT_MODE_SAFEININT; */
|
535 |
|
|
|
536 |
|
|
if(request_irq(info->int_irq, parport_etrax_interrupt,
|
537 |
|
|
SA_SHIRQ, names[i], p)) {
|
538 |
|
|
parport_unregister_port (p);
|
539 |
|
|
continue;
|
540 |
|
|
}
|
541 |
|
|
|
542 |
|
|
printk(KERN_INFO "%s: ETRAX 100LX port %d using irq\n",
|
543 |
|
|
p->name, i);
|
544 |
|
|
parport_proc_register(p);
|
545 |
|
|
parport_announce_port(p);
|
546 |
|
|
port_exists = 1;
|
547 |
|
|
}
|
548 |
|
|
|
549 |
|
|
return port_exists;
|
550 |
|
|
}
|
551 |
|
|
|
552 |
|
|
void __exit
|
553 |
|
|
parport_etrax_exit(void)
|
554 |
|
|
{
|
555 |
|
|
int i;
|
556 |
|
|
struct etrax100par_struct *info;
|
557 |
|
|
|
558 |
|
|
for (i = 0, info = port_table; i < NR_PORTS; i++, info++) {
|
559 |
|
|
#ifndef CONFIG_ETRAX_PARALLEL_PORT0
|
560 |
|
|
if (i == 0)
|
561 |
|
|
continue;
|
562 |
|
|
#endif
|
563 |
|
|
#ifndef CONFIG_ETRAX_PARALLEL_PORT1
|
564 |
|
|
if (i == 1)
|
565 |
|
|
continue;
|
566 |
|
|
#endif
|
567 |
|
|
if (info->int_irq != PARPORT_IRQ_NONE)
|
568 |
|
|
free_irq(info->int_irq, info->port);
|
569 |
|
|
parport_proc_unregister(info->port);
|
570 |
|
|
parport_unregister_port(info->port);
|
571 |
|
|
}
|
572 |
|
|
}
|