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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [i386/] [lib/] [dec_and_lock.c] - Blame information for rev 1765

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Line No. Rev Author Line
1 1275 phoenix
/*
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 * x86 version of "atomic_dec_and_lock()" using
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 * the atomic "cmpxchg" instruction.
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 *
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 * (For CPU's lacking cmpxchg, we use the slow
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 * generic version, and this one never even gets
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 * compiled).
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 */
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#include <linux/spinlock.h>
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#include <asm/atomic.h>
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int atomic_dec_and_lock(atomic_t *atomic, spinlock_t *lock)
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{
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        int counter;
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        int newcount;
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repeat:
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        counter = atomic_read(atomic);
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        newcount = counter-1;
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        if (!newcount)
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                goto slow_path;
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        asm volatile("lock; cmpxchgl %1,%2"
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                :"=a" (newcount)
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                :"r" (newcount), "m" (atomic->counter), "0" (counter));
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        /* If the above failed, "eax" will have changed */
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        if (newcount != counter)
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                goto repeat;
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        return 0;
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slow_path:
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        spin_lock(lock);
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        if (atomic_dec_and_test(atomic))
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                return 1;
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        spin_unlock(lock);
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        return 0;
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}

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