OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [ia64/] [kernel/] [perfmon_mckinley.h] - Blame information for rev 1765

Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1275 phoenix 
/*
2 
 * This file contains the McKinley PMU register description tables
3 
 * and pmc checker used by perfmon.c.
4 
 *
5 
 * Copyright (C) 2002  Hewlett Packard Co
6 
 *               Stephane Eranian <eranian@hpl.hp.com>
7 
 */
8 
 
9 
#define RDEP(x) (1UL<<(x))
10 
 
11 
#ifndef CONFIG_MCKINLEY
12 
#error "This file is only valid when CONFIG_MCKINLEY is defined"
13 
#endif
14 
 
15 
static int pfm_mck_reserved(struct task_struct *task, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
16 
static int pfm_mck_pmc_check(struct task_struct *task, unsigned int cnum, unsigned long *val, struct pt_regs *regs);
17 
static int pfm_write_ibr_dbr(int mode, struct task_struct *task, void *arg, int count, struct pt_regs *regs);
18 
 
19 
static pfm_reg_desc_t pfm_mck_pmc_desc[PMU_MAX_PMCS]={
20 
/* pmc0  */ { PFM_REG_CONTROL , 0, 0x1UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
21 
/* pmc1  */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
22 
/* pmc2  */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
23 
/* pmc3  */ { PFM_REG_CONTROL , 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
24 
/* pmc4  */ { PFM_REG_COUNTING, 6, 0x0000000000800000UL, 0xfffff7fUL, NULL, pfm_mck_pmc_check, {RDEP(4),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
25 
/* pmc5  */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL,  pfm_mck_reserved, {RDEP(5),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
26 
/* pmc6  */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL,  pfm_mck_reserved, {RDEP(6),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
27 
/* pmc7  */ { PFM_REG_COUNTING, 6, 0x0UL, 0xfffff7fUL, NULL,  pfm_mck_reserved, {RDEP(7),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
28 
/* pmc8  */ { PFM_REG_CONFIG  , 0, 0xffffffff3fffffffUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
29 
/* pmc9  */ { PFM_REG_CONFIG  , 0, 0xffffffff3ffffffcUL, 0xffffffff3ffffffbUL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
30 
/* pmc10 */ { PFM_REG_MONITOR , 4, 0x0UL, 0xffffUL, NULL, pfm_mck_reserved, {RDEP(0)|RDEP(1),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
31 
/* pmc11 */ { PFM_REG_MONITOR , 6, 0x0UL, 0x30f01cf, NULL,  pfm_mck_reserved, {RDEP(2)|RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
32 
/* pmc12 */ { PFM_REG_MONITOR , 6, 0x0UL, 0xffffUL, NULL,  pfm_mck_reserved, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
33 
/* pmc13 */ { PFM_REG_CONFIG  , 0, 0x00002078fefefefeUL, 0x1e00018181818UL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
34 
/* pmc14 */ { PFM_REG_CONFIG  , 0, 0x0db60db60db60db6UL, 0x2492UL, NULL, pfm_mck_pmc_check, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
35 
/* pmc15 */ { PFM_REG_CONFIG  , 0, 0x00000000fffffff0UL, 0xfUL, NULL, pfm_mck_reserved, {0UL,0UL, 0UL, 0UL}, {0UL,0UL, 0UL, 0UL}},
36 
            { PFM_REG_END     , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
37 
};
38 
 
39 
static pfm_reg_desc_t pfm_mck_pmd_desc[PMU_MAX_PMDS]={
40 
/* pmd0  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(1),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
41 
/* pmd1  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(0),0UL, 0UL, 0UL}, {RDEP(10),0UL, 0UL, 0UL}},
42 
/* pmd2  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(3)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
43 
/* pmd3  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(17),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
44 
/* pmd4  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(4),0UL, 0UL, 0UL}},
45 
/* pmd5  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(5),0UL, 0UL, 0UL}},
46 
/* pmd6  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(6),0UL, 0UL, 0UL}},
47 
/* pmd7  */ { PFM_REG_COUNTING, 0, 0x0UL, -1UL, NULL, NULL, {0UL,0UL, 0UL, 0UL}, {RDEP(7),0UL, 0UL, 0UL}},
48 
/* pmd8  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
49 
/* pmd9  */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
50 
/* pmd10 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
51 
/* pmd11 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
52 
/* pmd12 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(13)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
53 
/* pmd13 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(14)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
54 
/* pmd14 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(15)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
55 
/* pmd15 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(16),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
56 
/* pmd16 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(8)|RDEP(9)|RDEP(10)|RDEP(11)|RDEP(12)|RDEP(13)|RDEP(14)|RDEP(15),0UL, 0UL, 0UL}, {RDEP(12),0UL, 0UL, 0UL}},
57 
/* pmd17 */ { PFM_REG_BUFFER  , 0, 0x0UL, -1UL, NULL, NULL, {RDEP(2)|RDEP(3),0UL, 0UL, 0UL}, {RDEP(11),0UL, 0UL, 0UL}},
58 
            { PFM_REG_END     , 0, 0x0UL, -1UL, NULL, NULL, {0,}, {0,}}, /* end marker */
59 
};
60 
 
61 
/*
62 
 * impl_pmcs, impl_pmds are computed at runtime to minimize errors!
63 
 */
64 
static pmu_config_t pmu_conf={
65 
        disabled:       1,
66 
        ovfl_val:       (1UL << 47) - 1,
67 
        num_ibrs:       8,
68 
        num_dbrs:       8,
69 
        pmd_desc:       pfm_mck_pmd_desc,
70 
        pmc_desc:       pfm_mck_pmc_desc
71 
};
72 
 
73 
 
74 
/*
75 
 * PMC reserved fields must have their power-up values preserved
76 
 */
77 
static int
78 
pfm_mck_reserved(struct task_struct *task, unsigned int cnum, unsigned long *val, struct pt_regs *regs)
79 
{
80 
        unsigned long tmp1, tmp2, ival = *val;
81 
 
82 
        /* remove reserved areas from user value */
83 
        tmp1 = ival & PMC_RSVD_MASK(cnum);
84 
 
85 
        /* get reserved fields values */
86 
        tmp2 = PMC_DFL_VAL(cnum) & ~PMC_RSVD_MASK(cnum);
87 
 
88 
        *val = tmp1 | tmp2;
89 
 
90 
        DBprintk(("pmc[%d]=0x%lx, mask=0x%lx, reset=0x%lx, val=0x%lx\n",
91 
                  cnum, ival, PMC_RSVD_MASK(cnum), PMC_DFL_VAL(cnum), *val));
92 
        return 0;
93 
}
94 
 
95 
static int
96 
pfm_mck_pmc_check(struct task_struct *task, unsigned int cnum, unsigned long *val, struct pt_regs *regs)
97 
{
98 
        struct thread_struct *th = &task->thread;
99 
        pfm_context_t *ctx = task->thread.pfm_context;
100 
        int ret = 0, check_case1 = 0;
101 
        unsigned long val8 = 0, val14 = 0, val13 = 0;
102 
 
103 
        /* first preserve the reserved fields */
104 
        pfm_mck_reserved(task, cnum, val, regs);
105 
 
106 
        /*
107 
         * we must clear the debug registers if any pmc13.ena_dbrpX bit is enabled
108 
         * before they are written (fl_using_dbreg==0) to avoid picking up stale information.
109 
         */
110 
        if (cnum == 13 && (*val & (0xfUL << 45)) && ctx->ctx_fl_using_dbreg == 0) {
111 
 
112 
                /* don't mix debug with perfmon */
113 
                if ((task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
114 
 
115 
                /*
116 
                 * a count of 0 will mark the debug registers as in use and also
117 
                 * ensure that they are properly cleared.
118 
                 */
119 
                ret = pfm_write_ibr_dbr(1, task, NULL, 0, regs);
120 
                if (ret) return ret;
121 
        }
122 
        /*
123 
         * we must clear the (instruction) debug registers if any pmc14.ibrpX bit is enabled
124 
         * before they are (fl_using_dbreg==0) to avoid picking up stale information.
125 
         */
126 
        if (cnum == 14 && ((*val & 0x2222) != 0x2222) && ctx->ctx_fl_using_dbreg == 0) {
127 
 
128 
                /* don't mix debug with perfmon */
129 
                if ((task->thread.flags & IA64_THREAD_DBG_VALID) != 0) return -EINVAL;
130 
 
131 
                /*
132 
                 * a count of 0 will mark the debug registers as in use and also
133 
                 * ensure that they are properly cleared.
134 
                 */
135 
                ret = pfm_write_ibr_dbr(0, task, NULL, 0, regs);
136 
                if (ret) return ret;
137 
 
138 
        }
139 
 
140 
        switch(cnum) {
141 
                case  4: *val |= 1UL << 23; /* force power enable bit */
142 
                         break;
143 
                case  8: val8 = *val;
144 
                         val13 = th->pmc[13];
145 
                         val14 = th->pmc[14];
146 
                         check_case1 = 1;
147 
                         break;
148 
                case 13: val8  = th->pmc[8];
149 
                         val13 = *val;
150 
                         val14 = th->pmc[14];
151 
                         check_case1 = 1;
152 
                         break;
153 
                case 14: val8  = th->pmc[13];
154 
                         val13 = th->pmc[13];
155 
                         val14 = *val;
156 
                         check_case1 = 1;
157 
                         break;
158 
        }
159 
        /* check illegal configuration which can produce inconsistencies in tagging
160 
         * i-side events in L1D and L2 caches
161 
         */
162 
        if (check_case1) {
163 
                ret =   ((val13 >> 45) & 0xf) == 0
164 
                   && ((val8 & 0x1) == 0)
165 
                   && ((((val14>>1) & 0x3) == 0x2 || ((val14>>1) & 0x3) == 0x0)
166 
                       ||(((val14>>4) & 0x3) == 0x2 || ((val14>>4) & 0x3) == 0x0));
167 
 
168 
                if (ret) printk(KERN_DEBUG "perfmon: failure check_case1\n");
169 
        }
170 
 
171 
        return ret ? -EINVAL : 0;
172 
}

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.