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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [mips/] [baget/] [bagetIRQ.S] - Blame information for rev 1765

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/*
 * bagetIRQ.S: Interrupt exception dispatch code for Baget/MIPS
 *
 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
 */
#include 
#include 
#include 
#include 
#include 
 
        .text
        .set    mips1
        .set    reorder
        .set    macro
        .set    noat
        .align  5
 
NESTED(bagetIRQ, PT_SIZE, sp)
        SAVE_ALL
        CLI                             # Important: mark KERNEL mode !
 
        la      a1, baget_interrupt
        .set    push
        .set    noreorder
        jal     a1
        .set    pop
        move    a0, sp
 
        la      a1, ret_from_irq
        jr      a1
END(bagetIRQ)
 
#define DBE_HANDLER       0x1C
 
NESTED(try_read, PT_SIZE, sp)
        mfc0    t3, CP0_STATUS          # save flags and
        CLI                             #  disable interrupts
 
        li      t0, KSEG2
        sltu    t1, t0, a0              # Is it KSEG2 address ?
        beqz    t1, mapped              # No - already mapped !
 
        move    t0, a0
        ori     t0, 0xfff
        xori    t0, 0xfff               # round address to page
 
        ori     t1, t0, 0xf00           # prepare EntryLo (N,V,D,G)
 
        mfc0    t2,   CP0_ENTRYHI       # save ASID value
        mtc0    zero, CP0_INDEX
        mtc0    t0,   CP0_ENTRYHI       # Load MMU values ...
        mtc0    t1,   CP0_ENTRYLO0
        nop                             # let it understand
        nop
        tlbwi                           # ... and write ones
        nop
        nop
        mtc0    t2,  CP0_ENTRYHI
 
mapped:
        la      t0, exception_handlers
        lw      t1, DBE_HANDLER(t0)     # save real handler
        la      t2, dbe_handler
        sw      t2, DBE_HANDLER(t0)     # set temporary local handler
        li      v0, -1                  # default (failure) value
 
        li      t2, 1
        beq     t2, a1, 1f
        li      t2, 2
        beq     t2, a1, 2f
        li      t2, 4
        beq     t2, a1, 4f
        b       out
 
1:      lbu     v0, (a0)                # byte
        b       out
 
2:      lhu     v0, (a0)                # short
        b       out
 
4:      lw      v0, (a0)                # word
 
out:
        sw      t1, DBE_HANDLER(t0)     # restore real handler
        mtc0    t3, CP0_STATUS          # restore CPU flags
        jr      ra
 
dbe_handler:
        li      v0, -1                  # mark our failure
        .set    push
        .set    noreorder
        b       out                     # "no problems !"
        rfe                             #   return from trap
        .set    pop
END(try_read)

Line No.	Rev	Author	Line
1	1275	phoenix	`/*`
2			`* bagetIRQ.S: Interrupt exception dispatch code for Baget/MIPS`
3			`*`
4			`* Copyright (C) 1998 Gleb Raiko & Vladimir Roganov`
5			`*/`
6			`#include`
7			`#include`
8			`#include`
9			`#include`
10			`#include`
11
12			`.text`
13			`.set mips1`
14			`.set reorder`
15			`.set macro`
16			`.set noat`
17			`.align 5`
18
19			`NESTED(bagetIRQ, PT_SIZE, sp)`
20			`SAVE_ALL`
21			`CLI # Important: mark KERNEL mode !`
22
23			`la a1, baget_interrupt`
24			`.set push`
25			`.set noreorder`
26			`jal a1`
27			`.set pop`
28			`move a0, sp`
29
30			`la a1, ret_from_irq`
31			`jr a1`
32			`END(bagetIRQ)`
33
34			`#define DBE_HANDLER 0x1C`
35
36			`NESTED(try_read, PT_SIZE, sp)`
37			`mfc0 t3, CP0_STATUS # save flags and`
38			`CLI # disable interrupts`
39
40			`li t0, KSEG2`
41			`sltu t1, t0, a0 # Is it KSEG2 address ?`
42			`beqz t1, mapped # No - already mapped !`
43
44			`move t0, a0`
45			`ori t0, 0xfff`
46			`xori t0, 0xfff # round address to page`
47
48			`ori t1, t0, 0xf00 # prepare EntryLo (N,V,D,G)`
49
50			`mfc0 t2, CP0_ENTRYHI # save ASID value`
51			`mtc0 zero, CP0_INDEX`
52			`mtc0 t0, CP0_ENTRYHI # Load MMU values ...`
53			`mtc0 t1, CP0_ENTRYLO0`
54			`nop # let it understand`
55			`nop`
56			`tlbwi # ... and write ones`
57			`nop`
58			`nop`
59			`mtc0 t2, CP0_ENTRYHI`
60
61			`mapped:`
62			`la t0, exception_handlers`
63			`lw t1, DBE_HANDLER(t0) # save real handler`
64			`la t2, dbe_handler`
65			`sw t2, DBE_HANDLER(t0) # set temporary local handler`
66			`li v0, -1 # default (failure) value`
67
68			`li t2, 1`
69			`beq t2, a1, 1f`
70			`li t2, 2`
71			`beq t2, a1, 2f`
72			`li t2, 4`
73			`beq t2, a1, 4f`
74			`b out`
75
76			`1: lbu v0, (a0) # byte`
77			`b out`
78
79			`2: lhu v0, (a0) # short`
80			`b out`
81
82			`4: lw v0, (a0) # word`
83
84			`out:`
85			`sw t1, DBE_HANDLER(t0) # restore real handler`
86			`mtc0 t3, CP0_STATUS # restore CPU flags`
87			`jr ra`
88
89			`dbe_handler:`
90			`li v0, -1 # mark our failure`
91			`.set push`
92			`.set noreorder`
93			`b out # "no problems !"`
94			`rfe # return from trap`
95			`.set pop`
96			`END(try_read)`

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [mips/] [baget/] [bagetIRQ.S] - Blame information for rev 1765