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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [mips/] [baget/] [balo_supp.S] - Blame information for rev 1765

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/*
 * balo_supp.S: BAget Loader supplement
 *
 * Copyright (C) 1998 Gleb Raiko & Vladimir Roganov
 */
#include 
#include 
#include 
#include 
#include 
 
        .text
        .set    mips1
 
        /* General exception vector. */
NESTED(except_vec3_generic, 0, sp)
        .set    noat
        la      k0, except_vec3_generic_code
        jr      k0
END(except_vec3_generic)
 
NESTED(except_vec3_generic_code, 0, sp)
        SAVE_ALL
        mfc0    k1, CP0_CAUSE
        la      k0, int_cause
        sw      k1, (k0)
 
        mfc0    k1, CP0_EPC
        la      k0, epc
        sw      k1, (k0)
 
        mfc0    k1, CP0_BADVADDR
        la      k0, badvaddr
        sw      k1, (k0)
 
        la      k0, int_handler
        .set    noreorder
        jal     k0
        .set    reorder
        move    a0, sp
 
        RESTORE_ALL_AND_RET
END(except_vec3_generic_code)
 
        .align  5
NESTED(flush_cache_low, PT_SIZE, sp)
        .set    at
        .set    macro
        .set    noreorder
 
        move    t1, a0  # ISIZE
        move    t2, a1  # DSIZE
 
        mfc0    t3, CP0_STATUS       # Save the status register.
        mtc0    zero, CP0_STATUS     # Disable interrupts.
        la      v0, 1f
        or      v0, KSEG1            # Run uncached.
        j       v0
        nop
/*
 * Flush the instruction cache.
 */
1:
        li      v0, ST0_DE | ST0_CE
        mtc0    v0, CP0_STATUS       # Isolate and swap caches.
        li      t0, KSEG1
        subu    t0, t0, t1
        li      t1, KSEG1
        la      v0, 1f                          # Run cached
        j       v0
        nop
1:
        addu    t0, t0, 64
        sb      zero, -64(t0)
        sb      zero, -60(t0)
        sb      zero, -56(t0)
        sb      zero, -52(t0)
        sb      zero, -48(t0)
        sb      zero, -44(t0)
        sb      zero, -40(t0)
        sb      zero, -36(t0)
        sb      zero, -32(t0)
        sb      zero, -28(t0)
        sb      zero, -24(t0)
        sb      zero, -20(t0)
        sb      zero, -16(t0)
        sb      zero, -12(t0)
        sb      zero, -8(t0)
        bne     t0, t1, 1b
        sb      zero, -4(t0)
 
        la      v0, 1f
        or      v0, KSEG1
        j       v0                              # Run uncached
        nop
/*
 * Flush the data cache.
 */
1:
        li      v0, ST0_DE
        mtc0    v0, CP0_STATUS       # Isolate and swap back caches
        li      t0, KSEG1
        subu    t0, t0, t2
        la      v0, 1f
        j       v0                              # Back to cached mode
        nop
1:
        addu    t0, t0, 64
        sb      zero, -64(t0)
        sb      zero, -60(t0)
        sb      zero, -56(t0)
        sb      zero, -52(t0)
        sb      zero, -48(t0)
        sb      zero, -44(t0)
        sb      zero, -40(t0)
        sb      zero, -36(t0)
        sb      zero, -32(t0)
        sb      zero, -28(t0)
        sb      zero, -24(t0)
        sb      zero, -20(t0)
        sb      zero, -16(t0)
        sb      zero, -12(t0)
        sb      zero, -8(t0)
        bne     t0, t1, 1b
        sb      zero, -4(t0)
 
        nop                                     # Insure isolated stores
        nop                                     #   out of pipe.
        nop
        nop
        mtc0    t3, CP0_STATUS                 # Restore status reg.
        nop                                    # Insure cache unisolated.
        nop
        nop
        nop
        j       ra
        nop
END(flush_cache_low)
 
/* To satisfy macros only */
EXPORT(kernelsp)
        PTR     0x80001000

Line No.	Rev	Author	Line
1	1275	phoenix	`/*`
2			`* balo_supp.S: BAget Loader supplement`
3			`*`
4			`* Copyright (C) 1998 Gleb Raiko & Vladimir Roganov`
5			`*/`
6			`#include`
7			`#include`
8			`#include`
9			`#include`
10			`#include`
11
12			`.text`
13			`.set mips1`
14
15			`/* General exception vector. */`
16			`NESTED(except_vec3_generic, 0, sp)`
17			`.set noat`
18			`la k0, except_vec3_generic_code`
19			`jr k0`
20			`END(except_vec3_generic)`
21
22			`NESTED(except_vec3_generic_code, 0, sp)`
23			`SAVE_ALL`
24			`mfc0 k1, CP0_CAUSE`
25			`la k0, int_cause`
26			`sw k1, (k0)`
27
28			`mfc0 k1, CP0_EPC`
29			`la k0, epc`
30			`sw k1, (k0)`
31
32			`mfc0 k1, CP0_BADVADDR`
33			`la k0, badvaddr`
34			`sw k1, (k0)`
35
36			`la k0, int_handler`
37			`.set noreorder`
38			`jal k0`
39			`.set reorder`
40			`move a0, sp`
41
42			`RESTORE_ALL_AND_RET`
43			`END(except_vec3_generic_code)`
44
45			`.align 5`
46			`NESTED(flush_cache_low, PT_SIZE, sp)`
47			`.set at`
48			`.set macro`
49			`.set noreorder`
50
51			`move t1, a0 # ISIZE`
52			`move t2, a1 # DSIZE`
53
54			`mfc0 t3, CP0_STATUS # Save the status register.`
55			`mtc0 zero, CP0_STATUS # Disable interrupts.`
56			`la v0, 1f`
57			`or v0, KSEG1 # Run uncached.`
58			`j v0`
59			`nop`
60			`/*`
61			`* Flush the instruction cache.`
62			`*/`
63			`1:`
64			`li v0, ST0_DE \| ST0_CE`
65			`mtc0 v0, CP0_STATUS # Isolate and swap caches.`
66			`li t0, KSEG1`
67			`subu t0, t0, t1`
68			`li t1, KSEG1`
69			`la v0, 1f # Run cached`
70			`j v0`
71			`nop`
72			`1:`
73			`addu t0, t0, 64`
74			`sb zero, -64(t0)`
75			`sb zero, -60(t0)`
76			`sb zero, -56(t0)`
77			`sb zero, -52(t0)`
78			`sb zero, -48(t0)`
79			`sb zero, -44(t0)`
80			`sb zero, -40(t0)`
81			`sb zero, -36(t0)`
82			`sb zero, -32(t0)`
83			`sb zero, -28(t0)`
84			`sb zero, -24(t0)`
85			`sb zero, -20(t0)`
86			`sb zero, -16(t0)`
87			`sb zero, -12(t0)`
88			`sb zero, -8(t0)`
89			`bne t0, t1, 1b`
90			`sb zero, -4(t0)`
91
92			`la v0, 1f`
93			`or v0, KSEG1`
94			`j v0 # Run uncached`
95			`nop`
96			`/*`
97			`* Flush the data cache.`
98			`*/`
99			`1:`
100			`li v0, ST0_DE`
101			`mtc0 v0, CP0_STATUS # Isolate and swap back caches`
102			`li t0, KSEG1`
103			`subu t0, t0, t2`
104			`la v0, 1f`
105			`j v0 # Back to cached mode`
106			`nop`
107			`1:`
108			`addu t0, t0, 64`
109			`sb zero, -64(t0)`
110			`sb zero, -60(t0)`
111			`sb zero, -56(t0)`
112			`sb zero, -52(t0)`
113			`sb zero, -48(t0)`
114			`sb zero, -44(t0)`
115			`sb zero, -40(t0)`
116			`sb zero, -36(t0)`
117			`sb zero, -32(t0)`
118			`sb zero, -28(t0)`
119			`sb zero, -24(t0)`
120			`sb zero, -20(t0)`
121			`sb zero, -16(t0)`
122			`sb zero, -12(t0)`
123			`sb zero, -8(t0)`
124			`bne t0, t1, 1b`
125			`sb zero, -4(t0)`
126
127			`nop # Insure isolated stores`
128			`nop # out of pipe.`
129			`nop`
130			`nop`
131			`mtc0 t3, CP0_STATUS # Restore status reg.`
132			`nop # Insure cache unisolated.`
133			`nop`
134			`nop`
135			`nop`
136			`j ra`
137			`nop`
138			`END(flush_cache_low)`
139
140			`/* To satisfy macros only */`
141			`EXPORT(kernelsp)`
142			`PTR 0x80001000`

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [mips/] [baget/] [balo_supp.S] - Blame information for rev 1765