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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [mips/] [kernel/] [gdb-low.S] - Blame information for rev 1275

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/*
 * gdb-low.S contains the low-level trap handler for the GDB stub.
 *
 * Copyright (C) 1995 Andreas Busse
 */
#include 
#include 
 
#include 
#include 
#include 
#include 
#include 
#include 
 
/*
 * [jsun] We reserves about 2x GDB_FR_SIZE in stack.  The lower (addressed)
 * part is used to store registers and passed to exception handler.
 * The upper part is reserved for "call func" feature where gdb client
 * saves some of the regs, setups call frame and passes args.
 *
 * A trace shows about 200 bytes are used to store about half of all regs.
 * The rest should be big enough for frame setup and passing args.
 */
 
/*
 * The low level trap handler
 */
                .align  5
                NESTED(trap_low, GDB_FR_SIZE, sp)
                .set    noat
                .set    noreorder
 
                mfc0    k0,CP0_STATUS
                sll     k0,3                    /* extract cu0 bit */
                bltz    k0,1f
                move    k1,sp
 
                /*
                 * Called from user mode, go somewhere else.
                 */
                lui     k1,%hi(saved_vectors)
                mfc0    k0,CP0_CAUSE
                andi    k0,k0,0x7c
                add     k1,k1,k0
                lw      k0,%lo(saved_vectors)(k1)
                jr      k0
                nop
1:
                move    k0,sp
                subu    sp,k1,GDB_FR_SIZE*2     # see comment above
                sw      k0,GDB_FR_REG29(sp)
                sw      v0,GDB_FR_REG2(sp)
 
/*
 * First save the CP0 and special registers
 */
 
                mfc0    v0,CP0_STATUS
                sw      v0,GDB_FR_STATUS(sp)
                mfc0    v0,CP0_CAUSE
                sw      v0,GDB_FR_CAUSE(sp)
                mfc0    v0,CP0_EPC
                sw      v0,GDB_FR_EPC(sp)
                mfc0    v0,CP0_BADVADDR
                sw      v0,GDB_FR_BADVADDR(sp)
                mfhi    v0
                sw      v0,GDB_FR_HI(sp)
                mflo    v0
                sw      v0,GDB_FR_LO(sp)
 
/*
 * Now the integer registers
 */
 
                sw      zero,GDB_FR_REG0(sp)            /* I know... */
                sw      $1,GDB_FR_REG1(sp)
                /* v0 already saved */
                sw      v1,GDB_FR_REG3(sp)
                sw      a0,GDB_FR_REG4(sp)
                sw      a1,GDB_FR_REG5(sp)
                sw      a2,GDB_FR_REG6(sp)
                sw      a3,GDB_FR_REG7(sp)
                sw      t0,GDB_FR_REG8(sp)
                sw      t1,GDB_FR_REG9(sp)
                sw      t2,GDB_FR_REG10(sp)
                sw      t3,GDB_FR_REG11(sp)
                sw      t4,GDB_FR_REG12(sp)
                sw      t5,GDB_FR_REG13(sp)
                sw      t6,GDB_FR_REG14(sp)
                sw      t7,GDB_FR_REG15(sp)
                sw      s0,GDB_FR_REG16(sp)
                sw      s1,GDB_FR_REG17(sp)
                sw      s2,GDB_FR_REG18(sp)
                sw      s3,GDB_FR_REG19(sp)
                sw      s4,GDB_FR_REG20(sp)
                sw      s5,GDB_FR_REG21(sp)
                sw      s6,GDB_FR_REG22(sp)
                sw      s7,GDB_FR_REG23(sp)
                sw      t8,GDB_FR_REG24(sp)
                sw      t9,GDB_FR_REG25(sp)
                sw      k0,GDB_FR_REG26(sp)
                sw      k1,GDB_FR_REG27(sp)
                sw      gp,GDB_FR_REG28(sp)
                /* sp already saved */
                sw      fp,GDB_FR_REG30(sp)
                sw      ra,GDB_FR_REG31(sp)
 
                CLI                             /* disable interrupts */
 
/*
 * Followed by the floating point registers
 */
                mfc0    v0,CP0_STATUS           /* FPU enabled? */
                srl     v0,v0,16
                andi    v0,v0,(ST0_CU1 >> 16)
 
                beqz    v0,2f                   /* disabled, skip */
                 nop
 
                swc1    $0,GDB_FR_FPR0(sp)
                swc1    $1,GDB_FR_FPR1(sp)
                swc1    $2,GDB_FR_FPR2(sp)
                swc1    $3,GDB_FR_FPR3(sp)
                swc1    $4,GDB_FR_FPR4(sp)
                swc1    $5,GDB_FR_FPR5(sp)
                swc1    $6,GDB_FR_FPR6(sp)
                swc1    $7,GDB_FR_FPR7(sp)
                swc1    $8,GDB_FR_FPR8(sp)
                swc1    $9,GDB_FR_FPR9(sp)
                swc1    $10,GDB_FR_FPR10(sp)
                swc1    $11,GDB_FR_FPR11(sp)
                swc1    $12,GDB_FR_FPR12(sp)
                swc1    $13,GDB_FR_FPR13(sp)
                swc1    $14,GDB_FR_FPR14(sp)
                swc1    $15,GDB_FR_FPR15(sp)
                swc1    $16,GDB_FR_FPR16(sp)
                swc1    $17,GDB_FR_FPR17(sp)
                swc1    $18,GDB_FR_FPR18(sp)
                swc1    $19,GDB_FR_FPR19(sp)
                swc1    $20,GDB_FR_FPR20(sp)
                swc1    $21,GDB_FR_FPR21(sp)
                swc1    $22,GDB_FR_FPR22(sp)
                swc1    $23,GDB_FR_FPR23(sp)
                swc1    $24,GDB_FR_FPR24(sp)
                swc1    $25,GDB_FR_FPR25(sp)
                swc1    $26,GDB_FR_FPR26(sp)
                swc1    $27,GDB_FR_FPR27(sp)
                swc1    $28,GDB_FR_FPR28(sp)
                swc1    $29,GDB_FR_FPR29(sp)
                swc1    $30,GDB_FR_FPR30(sp)
                swc1    $31,GDB_FR_FPR31(sp)
 
/*
 * FPU control registers
 */
 
                cfc1    v0,CP1_STATUS
                sw      v0,GDB_FR_FSR(sp)
                cfc1    v0,CP1_REVISION
                sw      v0,GDB_FR_FIR(sp)
 
/*
 * Current stack frame ptr
 */
 
2:
                sw      sp,GDB_FR_FRP(sp)
 
/*
 * CP0 registers (R4000/R4400 unused registers skipped)
 */
 
                mfc0    v0,CP0_INDEX
                sw      v0,GDB_FR_CP0_INDEX(sp)
                mfc0    v0,CP0_RANDOM
                sw      v0,GDB_FR_CP0_RANDOM(sp)
                mfc0    v0,CP0_ENTRYLO0
                sw      v0,GDB_FR_CP0_ENTRYLO0(sp)
                mfc0    v0,CP0_ENTRYLO1
                sw      v0,GDB_FR_CP0_ENTRYLO1(sp)
                mfc0    v0,CP0_CONTEXT
                sw      v0,GDB_FR_CP0_CONTEXT(sp)
                mfc0    v0,CP0_PAGEMASK
                sw      v0,GDB_FR_CP0_PAGEMASK(sp)
                mfc0    v0,CP0_WIRED
                sw      v0,GDB_FR_CP0_WIRED(sp)
                mfc0    v0,CP0_ENTRYHI
                sw      v0,GDB_FR_CP0_ENTRYHI(sp)
                mfc0    v0,CP0_PRID
                sw      v0,GDB_FR_CP0_PRID(sp)
 
                .set    at
 
/*
 * Continue with the higher level handler
 */
 
                move    a0,sp
 
                jal     handle_exception
                 nop
 
/*
 * Restore all writable registers, in reverse order
 */
 
                .set    noat
 
                lw      v0,GDB_FR_CP0_ENTRYHI(sp)
                lw      v1,GDB_FR_CP0_WIRED(sp)
                mtc0    v0,CP0_ENTRYHI
                mtc0    v1,CP0_WIRED
                lw      v0,GDB_FR_CP0_PAGEMASK(sp)
                lw      v1,GDB_FR_CP0_ENTRYLO1(sp)
                mtc0    v0,CP0_PAGEMASK
                mtc0    v1,CP0_ENTRYLO1
                lw      v0,GDB_FR_CP0_ENTRYLO0(sp)
                lw      v1,GDB_FR_CP0_INDEX(sp)
                mtc0    v0,CP0_ENTRYLO0
                lw      v0,GDB_FR_CP0_CONTEXT(sp)
                mtc0    v1,CP0_INDEX
                mtc0    v0,CP0_CONTEXT
 
 
/*
 * Next, the floating point registers
 */
                mfc0    v0,CP0_STATUS           /* check if the FPU is enabled */
                srl     v0,v0,16
                andi    v0,v0,(ST0_CU1 >> 16)
 
                beqz    v0,3f                   /* disabled, skip */
                 nop
 
                lwc1    $31,GDB_FR_FPR31(sp)
                lwc1    $30,GDB_FR_FPR30(sp)
                lwc1    $29,GDB_FR_FPR29(sp)
                lwc1    $28,GDB_FR_FPR28(sp)
                lwc1    $27,GDB_FR_FPR27(sp)
                lwc1    $26,GDB_FR_FPR26(sp)
                lwc1    $25,GDB_FR_FPR25(sp)
                lwc1    $24,GDB_FR_FPR24(sp)
                lwc1    $23,GDB_FR_FPR23(sp)
                lwc1    $22,GDB_FR_FPR22(sp)
                lwc1    $21,GDB_FR_FPR21(sp)
                lwc1    $20,GDB_FR_FPR20(sp)
                lwc1    $19,GDB_FR_FPR19(sp)
                lwc1    $18,GDB_FR_FPR18(sp)
                lwc1    $17,GDB_FR_FPR17(sp)
                lwc1    $16,GDB_FR_FPR16(sp)
                lwc1    $15,GDB_FR_FPR15(sp)
                lwc1    $14,GDB_FR_FPR14(sp)
                lwc1    $13,GDB_FR_FPR13(sp)
                lwc1    $12,GDB_FR_FPR12(sp)
                lwc1    $11,GDB_FR_FPR11(sp)
                lwc1    $10,GDB_FR_FPR10(sp)
                lwc1    $9,GDB_FR_FPR9(sp)
                lwc1    $8,GDB_FR_FPR8(sp)
                lwc1    $7,GDB_FR_FPR7(sp)
                lwc1    $6,GDB_FR_FPR6(sp)
                lwc1    $5,GDB_FR_FPR5(sp)
                lwc1    $4,GDB_FR_FPR4(sp)
                lwc1    $3,GDB_FR_FPR3(sp)
                lwc1    $2,GDB_FR_FPR2(sp)
                lwc1    $1,GDB_FR_FPR1(sp)
                lwc1    $0,GDB_FR_FPR0(sp)
 
/*
 * Now the CP0 and integer registers
 */
 
3:
                mfc0    t0,CP0_STATUS
                ori     t0,0x1f
                xori    t0,0x1f
                mtc0    t0,CP0_STATUS
 
                lw      v0,GDB_FR_STATUS(sp)
                lw      v1,GDB_FR_EPC(sp)
                mtc0    v0,CP0_STATUS
                mtc0    v1,CP0_EPC
                lw      v0,GDB_FR_HI(sp)
                lw      v1,GDB_FR_LO(sp)
                mthi    v0
                mtlo    v0
                lw      ra,GDB_FR_REG31(sp)
                lw      fp,GDB_FR_REG30(sp)
                lw      gp,GDB_FR_REG28(sp)
                lw      k1,GDB_FR_REG27(sp)
                lw      k0,GDB_FR_REG26(sp)
                lw      t9,GDB_FR_REG25(sp)
                lw      t8,GDB_FR_REG24(sp)
                lw      s7,GDB_FR_REG23(sp)
                lw      s6,GDB_FR_REG22(sp)
                lw      s5,GDB_FR_REG21(sp)
                lw      s4,GDB_FR_REG20(sp)
                lw      s3,GDB_FR_REG19(sp)
                lw      s2,GDB_FR_REG18(sp)
                lw      s1,GDB_FR_REG17(sp)
                lw      s0,GDB_FR_REG16(sp)
                lw      t7,GDB_FR_REG15(sp)
                lw      t6,GDB_FR_REG14(sp)
                lw      t5,GDB_FR_REG13(sp)
                lw      t4,GDB_FR_REG12(sp)
                lw      t3,GDB_FR_REG11(sp)
                lw      t2,GDB_FR_REG10(sp)
                lw      t1,GDB_FR_REG9(sp)
                lw      t0,GDB_FR_REG8(sp)
                lw      a3,GDB_FR_REG7(sp)
                lw      a2,GDB_FR_REG6(sp)
                lw      a1,GDB_FR_REG5(sp)
                lw      a0,GDB_FR_REG4(sp)
                lw      v1,GDB_FR_REG3(sp)
                lw      v0,GDB_FR_REG2(sp)
                lw      $1,GDB_FR_REG1(sp)
#if defined(CONFIG_CPU_R3000) || defined(CONFIG_CPU_TX39XX)
                lw      k0, GDB_FR_EPC(sp)
                lw      sp, GDB_FR_REG29(sp)            /* Deallocate stack */
                jr      k0
                rfe
#else
                lw      sp, GDB_FR_REG29(sp)            /* Deallocate stack */
 
                .set    mips3
                eret
                .set    mips0
#endif
                .set    at
                .set    reorder
                END(trap_low)
 
LEAF(kgdb_read_byte)
4:              lb      t0, (a0)
                sb      t0, (a1)
                li      v0, 0
                jr      ra
                .section __ex_table,"a"
                PTR     4b, kgdbfault
                .previous
                END(kgdb_read_byte)
 
LEAF(kgdb_write_byte)
5:              sb      a0, (a1)
                li      v0, 0
                jr      ra
                .section __ex_table,"a"
                PTR     5b, kgdbfault
                .previous
                END(kgdb_write_byte)
 
                .type   kgdbfault@function
                .ent    kgdbfault
 
kgdbfault:      li      v0, -EFAULT
                jr      ra
                .end    kgdbfault

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [mips/] [kernel/] [gdb-low.S] - Blame information for rev 1275

Line No.	Rev	Author	Line
1	1275	phoenix	`/*`
2			`* gdb-low.S contains the low-level trap handler for the GDB stub.`
3			`*`
4			`* Copyright (C) 1995 Andreas Busse`
5			`*/`
6			`#include`
7			`#include`
8
9			`#include`
10			`#include`
11			`#include`
12			`#include`
13			`#include`
14			`#include`
15
16			`/*`
17			`* [jsun] We reserves about 2x GDB_FR_SIZE in stack. The lower (addressed)`
18			`* part is used to store registers and passed to exception handler.`
19			`* The upper part is reserved for "call func" feature where gdb client`
20			`* saves some of the regs, setups call frame and passes args.`
21			`*`
22			`* A trace shows about 200 bytes are used to store about half of all regs.`
23			`* The rest should be big enough for frame setup and passing args.`
24			`*/`
25
26			`/*`
27			`* The low level trap handler`
28			`*/`
29			`.align 5`
30			`NESTED(trap_low, GDB_FR_SIZE, sp)`
31			`.set noat`
32			`.set noreorder`
33
34			`mfc0 k0,CP0_STATUS`
35			`sll k0,3 /* extract cu0 bit */`
36			`bltz k0,1f`
37			`move k1,sp`
38
39			`/*`
40			`* Called from user mode, go somewhere else.`
41			`*/`
42			`lui k1,%hi(saved_vectors)`
43			`mfc0 k0,CP0_CAUSE`
44			`andi k0,k0,0x7c`
45			`add k1,k1,k0`
46			`lw k0,%lo(saved_vectors)(k1)`
47			`jr k0`
48			`nop`
49			`1:`
50			`move k0,sp`
51			`subu sp,k1,GDB_FR_SIZE*2 # see comment above`
52			`sw k0,GDB_FR_REG29(sp)`
53			`sw v0,GDB_FR_REG2(sp)`
54
55			`/*`
56			`* First save the CP0 and special registers`
57			`*/`
58
59			`mfc0 v0,CP0_STATUS`
60			`sw v0,GDB_FR_STATUS(sp)`
61			`mfc0 v0,CP0_CAUSE`
62			`sw v0,GDB_FR_CAUSE(sp)`
63			`mfc0 v0,CP0_EPC`
64			`sw v0,GDB_FR_EPC(sp)`
65			`mfc0 v0,CP0_BADVADDR`
66			`sw v0,GDB_FR_BADVADDR(sp)`
67			`mfhi v0`
68			`sw v0,GDB_FR_HI(sp)`
69			`mflo v0`
70			`sw v0,GDB_FR_LO(sp)`
71
72			`/*`
73			`* Now the integer registers`
74			`*/`
75
76			`sw zero,GDB_FR_REG0(sp) /* I know... */`
77			`sw $1,GDB_FR_REG1(sp)`
78			`/* v0 already saved */`
79			`sw v1,GDB_FR_REG3(sp)`
80			`sw a0,GDB_FR_REG4(sp)`
81			`sw a1,GDB_FR_REG5(sp)`
82			`sw a2,GDB_FR_REG6(sp)`
83			`sw a3,GDB_FR_REG7(sp)`
84			`sw t0,GDB_FR_REG8(sp)`
85			`sw t1,GDB_FR_REG9(sp)`
86			`sw t2,GDB_FR_REG10(sp)`
87			`sw t3,GDB_FR_REG11(sp)`
88			`sw t4,GDB_FR_REG12(sp)`
89			`sw t5,GDB_FR_REG13(sp)`
90			`sw t6,GDB_FR_REG14(sp)`
91			`sw t7,GDB_FR_REG15(sp)`
92			`sw s0,GDB_FR_REG16(sp)`
93			`sw s1,GDB_FR_REG17(sp)`
94			`sw s2,GDB_FR_REG18(sp)`
95			`sw s3,GDB_FR_REG19(sp)`
96			`sw s4,GDB_FR_REG20(sp)`
97			`sw s5,GDB_FR_REG21(sp)`
98			`sw s6,GDB_FR_REG22(sp)`
99			`sw s7,GDB_FR_REG23(sp)`
100			`sw t8,GDB_FR_REG24(sp)`
101			`sw t9,GDB_FR_REG25(sp)`
102			`sw k0,GDB_FR_REG26(sp)`
103			`sw k1,GDB_FR_REG27(sp)`
104			`sw gp,GDB_FR_REG28(sp)`
105			`/* sp already saved */`
106			`sw fp,GDB_FR_REG30(sp)`
107			`sw ra,GDB_FR_REG31(sp)`
108
109			`CLI /* disable interrupts */`
110
111			`/*`
112			`* Followed by the floating point registers`
113			`*/`
114			`mfc0 v0,CP0_STATUS /* FPU enabled? */`
115			`srl v0,v0,16`
116			`andi v0,v0,(ST0_CU1 >> 16)`
117
118			`beqz v0,2f /* disabled, skip */`
119			`nop`
120
121			`swc1 $0,GDB_FR_FPR0(sp)`
122			`swc1 $1,GDB_FR_FPR1(sp)`
123			`swc1 $2,GDB_FR_FPR2(sp)`
124			`swc1 $3,GDB_FR_FPR3(sp)`
125			`swc1 $4,GDB_FR_FPR4(sp)`
126			`swc1 $5,GDB_FR_FPR5(sp)`
127			`swc1 $6,GDB_FR_FPR6(sp)`
128			`swc1 $7,GDB_FR_FPR7(sp)`
129			`swc1 $8,GDB_FR_FPR8(sp)`
130			`swc1 $9,GDB_FR_FPR9(sp)`
131			`swc1 $10,GDB_FR_FPR10(sp)`
132			`swc1 $11,GDB_FR_FPR11(sp)`
133			`swc1 $12,GDB_FR_FPR12(sp)`
134			`swc1 $13,GDB_FR_FPR13(sp)`
135			`swc1 $14,GDB_FR_FPR14(sp)`
136			`swc1 $15,GDB_FR_FPR15(sp)`
137			`swc1 $16,GDB_FR_FPR16(sp)`
138			`swc1 $17,GDB_FR_FPR17(sp)`
139			`swc1 $18,GDB_FR_FPR18(sp)`
140			`swc1 $19,GDB_FR_FPR19(sp)`
141			`swc1 $20,GDB_FR_FPR20(sp)`
142			`swc1 $21,GDB_FR_FPR21(sp)`
143			`swc1 $22,GDB_FR_FPR22(sp)`
144			`swc1 $23,GDB_FR_FPR23(sp)`
145			`swc1 $24,GDB_FR_FPR24(sp)`
146			`swc1 $25,GDB_FR_FPR25(sp)`
147			`swc1 $26,GDB_FR_FPR26(sp)`
148			`swc1 $27,GDB_FR_FPR27(sp)`
149			`swc1 $28,GDB_FR_FPR28(sp)`
150			`swc1 $29,GDB_FR_FPR29(sp)`
151			`swc1 $30,GDB_FR_FPR30(sp)`
152			`swc1 $31,GDB_FR_FPR31(sp)`
153
154			`/*`
155			`* FPU control registers`
156			`*/`
157
158			`cfc1 v0,CP1_STATUS`
159			`sw v0,GDB_FR_FSR(sp)`
160			`cfc1 v0,CP1_REVISION`
161			`sw v0,GDB_FR_FIR(sp)`
162
163			`/*`
164			`* Current stack frame ptr`
165			`*/`
166
167			`2:`
168			`sw sp,GDB_FR_FRP(sp)`
169
170			`/*`
171			`* CP0 registers (R4000/R4400 unused registers skipped)`
172			`*/`
173
174			`mfc0 v0,CP0_INDEX`
175			`sw v0,GDB_FR_CP0_INDEX(sp)`
176			`mfc0 v0,CP0_RANDOM`
177			`sw v0,GDB_FR_CP0_RANDOM(sp)`
178			`mfc0 v0,CP0_ENTRYLO0`
179			`sw v0,GDB_FR_CP0_ENTRYLO0(sp)`
180			`mfc0 v0,CP0_ENTRYLO1`
181			`sw v0,GDB_FR_CP0_ENTRYLO1(sp)`
182			`mfc0 v0,CP0_CONTEXT`
183			`sw v0,GDB_FR_CP0_CONTEXT(sp)`
184			`mfc0 v0,CP0_PAGEMASK`
185			`sw v0,GDB_FR_CP0_PAGEMASK(sp)`
186			`mfc0 v0,CP0_WIRED`
187			`sw v0,GDB_FR_CP0_WIRED(sp)`
188			`mfc0 v0,CP0_ENTRYHI`
189			`sw v0,GDB_FR_CP0_ENTRYHI(sp)`
190			`mfc0 v0,CP0_PRID`
191			`sw v0,GDB_FR_CP0_PRID(sp)`
192
193			`.set at`
194
195			`/*`
196			`* Continue with the higher level handler`
197			`*/`
198
199			`move a0,sp`
200
201			`jal handle_exception`
202			`nop`
203
204			`/*`
205			`* Restore all writable registers, in reverse order`
206			`*/`
207
208			`.set noat`
209
210			`lw v0,GDB_FR_CP0_ENTRYHI(sp)`
211			`lw v1,GDB_FR_CP0_WIRED(sp)`
212			`mtc0 v0,CP0_ENTRYHI`
213			`mtc0 v1,CP0_WIRED`
214			`lw v0,GDB_FR_CP0_PAGEMASK(sp)`
215			`lw v1,GDB_FR_CP0_ENTRYLO1(sp)`
216			`mtc0 v0,CP0_PAGEMASK`
217			`mtc0 v1,CP0_ENTRYLO1`
218			`lw v0,GDB_FR_CP0_ENTRYLO0(sp)`
219			`lw v1,GDB_FR_CP0_INDEX(sp)`
220			`mtc0 v0,CP0_ENTRYLO0`
221			`lw v0,GDB_FR_CP0_CONTEXT(sp)`
222			`mtc0 v1,CP0_INDEX`
223			`mtc0 v0,CP0_CONTEXT`
224
225
226			`/*`
227			`* Next, the floating point registers`
228			`*/`
229			`mfc0 v0,CP0_STATUS /* check if the FPU is enabled */`
230			`srl v0,v0,16`
231			`andi v0,v0,(ST0_CU1 >> 16)`
232
233			`beqz v0,3f /* disabled, skip */`
234			`nop`
235
236			`lwc1 $31,GDB_FR_FPR31(sp)`
237			`lwc1 $30,GDB_FR_FPR30(sp)`
238			`lwc1 $29,GDB_FR_FPR29(sp)`
239			`lwc1 $28,GDB_FR_FPR28(sp)`
240			`lwc1 $27,GDB_FR_FPR27(sp)`
241			`lwc1 $26,GDB_FR_FPR26(sp)`
242			`lwc1 $25,GDB_FR_FPR25(sp)`
243			`lwc1 $24,GDB_FR_FPR24(sp)`
244			`lwc1 $23,GDB_FR_FPR23(sp)`
245			`lwc1 $22,GDB_FR_FPR22(sp)`
246			`lwc1 $21,GDB_FR_FPR21(sp)`
247			`lwc1 $20,GDB_FR_FPR20(sp)`
248			`lwc1 $19,GDB_FR_FPR19(sp)`
249			`lwc1 $18,GDB_FR_FPR18(sp)`
250			`lwc1 $17,GDB_FR_FPR17(sp)`
251			`lwc1 $16,GDB_FR_FPR16(sp)`
252			`lwc1 $15,GDB_FR_FPR15(sp)`
253			`lwc1 $14,GDB_FR_FPR14(sp)`
254			`lwc1 $13,GDB_FR_FPR13(sp)`
255			`lwc1 $12,GDB_FR_FPR12(sp)`
256			`lwc1 $11,GDB_FR_FPR11(sp)`
257			`lwc1 $10,GDB_FR_FPR10(sp)`
258			`lwc1 $9,GDB_FR_FPR9(sp)`
259			`lwc1 $8,GDB_FR_FPR8(sp)`
260			`lwc1 $7,GDB_FR_FPR7(sp)`
261			`lwc1 $6,GDB_FR_FPR6(sp)`
262			`lwc1 $5,GDB_FR_FPR5(sp)`
263			`lwc1 $4,GDB_FR_FPR4(sp)`
264			`lwc1 $3,GDB_FR_FPR3(sp)`
265			`lwc1 $2,GDB_FR_FPR2(sp)`
266			`lwc1 $1,GDB_FR_FPR1(sp)`
267			`lwc1 $0,GDB_FR_FPR0(sp)`
268
269			`/*`
270			`* Now the CP0 and integer registers`
271			`*/`
272
273			`3:`
274			`mfc0 t0,CP0_STATUS`
275			`ori t0,0x1f`
276			`xori t0,0x1f`
277			`mtc0 t0,CP0_STATUS`
278
279			`lw v0,GDB_FR_STATUS(sp)`
280			`lw v1,GDB_FR_EPC(sp)`
281			`mtc0 v0,CP0_STATUS`
282			`mtc0 v1,CP0_EPC`
283			`lw v0,GDB_FR_HI(sp)`
284			`lw v1,GDB_FR_LO(sp)`
285			`mthi v0`
286			`mtlo v0`
287			`lw ra,GDB_FR_REG31(sp)`
288			`lw fp,GDB_FR_REG30(sp)`
289			`lw gp,GDB_FR_REG28(sp)`
290			`lw k1,GDB_FR_REG27(sp)`
291			`lw k0,GDB_FR_REG26(sp)`
292			`lw t9,GDB_FR_REG25(sp)`
293			`lw t8,GDB_FR_REG24(sp)`
294			`lw s7,GDB_FR_REG23(sp)`
295			`lw s6,GDB_FR_REG22(sp)`
296			`lw s5,GDB_FR_REG21(sp)`
297			`lw s4,GDB_FR_REG20(sp)`
298			`lw s3,GDB_FR_REG19(sp)`
299			`lw s2,GDB_FR_REG18(sp)`
300			`lw s1,GDB_FR_REG17(sp)`
301			`lw s0,GDB_FR_REG16(sp)`
302			`lw t7,GDB_FR_REG15(sp)`
303			`lw t6,GDB_FR_REG14(sp)`
304			`lw t5,GDB_FR_REG13(sp)`
305			`lw t4,GDB_FR_REG12(sp)`
306			`lw t3,GDB_FR_REG11(sp)`
307			`lw t2,GDB_FR_REG10(sp)`
308			`lw t1,GDB_FR_REG9(sp)`
309			`lw t0,GDB_FR_REG8(sp)`
310			`lw a3,GDB_FR_REG7(sp)`
311			`lw a2,GDB_FR_REG6(sp)`
312			`lw a1,GDB_FR_REG5(sp)`
313			`lw a0,GDB_FR_REG4(sp)`
314			`lw v1,GDB_FR_REG3(sp)`
315			`lw v0,GDB_FR_REG2(sp)`
316			`lw $1,GDB_FR_REG1(sp)`
317			`#if defined(CONFIG_CPU_R3000) \|\| defined(CONFIG_CPU_TX39XX)`
318			`lw k0, GDB_FR_EPC(sp)`
319			`lw sp, GDB_FR_REG29(sp) /* Deallocate stack */`
320			`jr k0`
321			`rfe`
322			`#else`
323			`lw sp, GDB_FR_REG29(sp) /* Deallocate stack */`
324
325			`.set mips3`
326			`eret`
327			`.set mips0`
328			`#endif`
329			`.set at`
330			`.set reorder`
331			`END(trap_low)`
332
333			`LEAF(kgdb_read_byte)`
334			`4: lb t0, (a0)`
335			`sb t0, (a1)`
336			`li v0, 0`
337			`jr ra`
338			`.section __ex_table,"a"`
339			`PTR 4b, kgdbfault`
340			`.previous`
341			`END(kgdb_read_byte)`
342
343			`LEAF(kgdb_write_byte)`
344			`5: sb a0, (a1)`
345			`li v0, 0`
346			`jr ra`
347			`.section __ex_table,"a"`
348			`PTR 5b, kgdbfault`
349			`.previous`
350			`END(kgdb_write_byte)`
351
352			`.type kgdbfault@function`
353			`.ent kgdbfault`
354
355			`kgdbfault: li v0, -EFAULT`
356			`jr ra`
357			`.end kgdbfault`