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1275 |
phoenix |
/*
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* Copyright 2001 MontaVista Software Inc.
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* Author: Jun Sun, jsun@mvista.com or jsun@junsun.net
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*
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* This file define the irq handler for MIPS CPU interrupts.
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* Almost all MIPS CPUs define 8 interrupt sources. They are typically
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* level triggered (i.e., cannot be cleared from CPU; must be cleared from
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* device). The first two are software interrupts. The last one is
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* usually the CPU timer interrupt if counter register is present or, for
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* CPUs with an external FPU, by convention it's the FPU exception interrupt.
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*
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* This file exports one global function:
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* void mips_cpu_irq_init(int irq_base);
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*/
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#include <linux/init.h>
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#include <linux/interrupt.h>
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#include <linux/kernel.h>
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#include <asm/irq_cpu.h>
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#include <asm/mipsregs.h>
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static int mips_cpu_irq_base = -1;
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static void mips_cpu_irq_enable(unsigned int irq)
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{
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clear_c0_cause( 1 << (irq - mips_cpu_irq_base + 8));
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set_c0_status(1 << (irq - mips_cpu_irq_base + 8));
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}
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static void mips_cpu_irq_disable(unsigned int irq)
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{
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clear_c0_status(1 << (irq - mips_cpu_irq_base + 8));
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}
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static unsigned int mips_cpu_irq_startup(unsigned int irq)
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{
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mips_cpu_irq_enable(irq);
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return 0;
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}
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#define mips_cpu_irq_shutdown mips_cpu_irq_disable
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static void mips_cpu_irq_ack(unsigned int irq)
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{
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/* although we attempt to clear the IP bit in cause register, I think
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* usually it is cleared by device (irq source)
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*/
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clear_c0_cause(1 << (irq - mips_cpu_irq_base + 8));
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/* disable this interrupt - so that we safe proceed to the handler */
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mips_cpu_irq_disable(irq);
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}
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static void mips_cpu_irq_end(unsigned int irq)
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{
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if (!(irq_desc[irq].status & (IRQ_DISABLED | IRQ_INPROGRESS)))
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mips_cpu_irq_enable(irq);
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}
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static hw_irq_controller mips_cpu_irq_controller = {
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"MIPS",
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mips_cpu_irq_startup,
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mips_cpu_irq_shutdown,
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mips_cpu_irq_enable,
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mips_cpu_irq_disable,
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mips_cpu_irq_ack,
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mips_cpu_irq_end,
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NULL /* no affinity stuff for UP */
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};
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void __init mips_cpu_irq_init(int irq_base)
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{
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int i;
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for (i = irq_base; i < irq_base + 8; i++) {
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irq_desc[i].status = IRQ_DISABLED;
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irq_desc[i].action = NULL;
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irq_desc[i].depth = 1;
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irq_desc[i].handler = &mips_cpu_irq_controller;
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}
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mips_cpu_irq_base = irq_base;
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}
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