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1275 |
phoenix |
/*
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* PCI autoconfiguration library
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*
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* Author: Matt Porter <mporter@mvista.com>
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*
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* Copyright 2000, 2001, 2002, 2003 MontaVista Software Inc.
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* Copyright 2001 Bradley D. LaRonde <brad@ltc.com>
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*
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* This program is free software; you can redistribute it and/or modify it
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* under the terms of the GNU General Public License as published by the
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* Free Software Foundation; either version 2 of the License, or (at your
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* option) any later version.
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*/
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/*
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* Modified for MIPS by Jun Sun, jsun@mvista.com
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*
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* . Simplify the interface between pci_auto and the rest: a single function.
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* . Assign resources from low address to upper address.
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* . change most int to u32.
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*
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* Further modified to include it as mips generic code, ppopov@mvista.com.
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*
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* 2001-10-26 Bradley D. LaRonde <brad@ltc.com>
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* - Add a top_bus argument to the "early config" functions so that
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* they can set a fake parent bus pointer to convince the underlying
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* pci ops to use type 1 configuration for sub busses.
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* - Set bridge base and limit registers correctly.
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* - Align io and memory base properly before and after bridge setup.
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* - Don't fall through to pci_setup_bars for bridge.
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* - Reformat the debug output to look more like lspci's output.
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*
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* 2003-04-09 Yoichi Yuasa, Alice Hennessy, Jun Sun
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* - Add cardbus bridge support, mostly copied from PPC
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*/
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#include <linux/kernel.h>
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#include <linux/init.h>
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#include <linux/types.h>
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#include <linux/pci.h>
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#include <asm/pci_channel.h>
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| 44 |
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#define DEBUG
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#ifdef DEBUG
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#define DBG(x...) printk(x)
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#else
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| 48 |
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#define DBG(x...)
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#endif
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/*
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* These functions are used early on before PCI scanning is done
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* and all of the pci_dev and pci_bus structures have been created.
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*/
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static struct pci_dev *fake_pci_dev(struct pci_channel *hose,
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int top_bus, int busnr, int devfn)
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{
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static struct pci_dev dev;
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static struct pci_bus bus;
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| 61 |
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dev.bus = &bus;
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dev.sysdata = hose;
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dev.devfn = devfn;
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bus.number = busnr;
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bus.ops = hose->pci_ops;
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if(busnr != top_bus)
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/* Fake a parent bus structure. */
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bus.parent = &bus;
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| 70 |
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else
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bus.parent = NULL;
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return &dev;
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}
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#define EARLY_PCI_OP(rw, size, type) \
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int early_##rw##_config_##size(struct pci_channel *hose, \
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int top_bus, int bus, int devfn, int offset, type value) \
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{ \
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return pci_##rw##_config_##size( \
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fake_pci_dev(hose, top_bus, bus, devfn), \
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offset, value); \
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}
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EARLY_PCI_OP(read, byte, u8 *)
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EARLY_PCI_OP(read, word, u16 *)
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EARLY_PCI_OP(read, dword, u32 *)
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EARLY_PCI_OP(write, byte, u8)
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EARLY_PCI_OP(write, word, u16)
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EARLY_PCI_OP(write, dword, u32)
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| 92 |
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static struct resource *io_resource_inuse;
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static struct resource *mem_resource_inuse;
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| 94 |
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| 95 |
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static u32 pciauto_lower_iospc;
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| 96 |
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static u32 pciauto_upper_iospc;
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| 98 |
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static u32 pciauto_lower_memspc;
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static u32 pciauto_upper_memspc;
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| 101 |
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void __init
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| 102 |
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pciauto_setup_bars(struct pci_channel *hose,
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int top_bus,
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int current_bus,
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int pci_devfn,
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int bar_limit)
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{
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u32 bar_response, bar_size, bar_value;
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u32 bar, addr_mask, bar_nr = 0;
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u32 * upper_limit;
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u32 * lower_limit;
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int found_mem64 = 0;
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for (bar = PCI_BASE_ADDRESS_0; bar <= bar_limit; bar+=4) {
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/* Tickle the BAR and get the response */
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early_write_config_dword(hose, top_bus,
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current_bus,
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pci_devfn,
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bar,
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0xffffffff);
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early_read_config_dword(hose, top_bus,
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current_bus,
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pci_devfn,
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bar,
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&bar_response);
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/* If BAR is not implemented go to the next BAR */
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if (!bar_response)
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continue;
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| 131 |
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/*
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* Workaround for a BAR that doesn't use its upper word,
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* like the ALi 1535D+ PCI DC-97 Controller Modem (M5457).
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* bdl <brad@ltc.com>
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| 135 |
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*/
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if (!(bar_response & 0xffff0000))
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bar_response |= 0xffff0000;
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| 139 |
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retry:
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/* Check the BAR type and set our address mask */
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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addr_mask = PCI_BASE_ADDRESS_IO_MASK;
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upper_limit = &pciauto_upper_iospc;
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lower_limit = &pciauto_lower_iospc;
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DBG(" I/O");
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} else {
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if ((bar_response & PCI_BASE_ADDRESS_MEM_TYPE_MASK) ==
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PCI_BASE_ADDRESS_MEM_TYPE_64)
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found_mem64 = 1;
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addr_mask = PCI_BASE_ADDRESS_MEM_MASK;
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upper_limit = &pciauto_upper_memspc;
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lower_limit = &pciauto_lower_memspc;
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DBG(" Mem");
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}
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| 157 |
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| 158 |
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/* Calculate requested size */
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bar_size = ~(bar_response & addr_mask) + 1;
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/* Allocate a base address */
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bar_value = ((*lower_limit - 1) & ~(bar_size - 1)) + bar_size;
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if ((bar_value + bar_size) > *upper_limit) {
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if (bar_response & PCI_BASE_ADDRESS_SPACE) {
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if (io_resource_inuse->child) {
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io_resource_inuse =
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io_resource_inuse->child;
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pciauto_lower_iospc =
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io_resource_inuse->start;
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pciauto_upper_iospc =
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io_resource_inuse->end + 1;
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goto retry;
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}
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| 176 |
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} else {
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if (mem_resource_inuse->child) {
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mem_resource_inuse =
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mem_resource_inuse->child;
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pciauto_lower_memspc =
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mem_resource_inuse->start;
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pciauto_upper_memspc =
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mem_resource_inuse->end + 1;
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goto retry;
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}
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}
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DBG(" unavailable -- skipping\n");
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continue;
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| 189 |
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}
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| 190 |
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| 191 |
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/* Write it out and update our limit */
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| 192 |
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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| 193 |
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bar, bar_value);
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| 194 |
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| 195 |
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*lower_limit = bar_value + bar_size;
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| 196 |
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| 197 |
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/*
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| 198 |
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* If we are a 64-bit decoder then increment to the
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| 199 |
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* upper 32 bits of the bar and force it to locate
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| 200 |
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* in the lower 4GB of memory.
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| 201 |
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*/
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| 202 |
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if (found_mem64) {
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| 203 |
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bar += 4;
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| 204 |
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early_write_config_dword(hose, top_bus,
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| 205 |
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current_bus,
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| 206 |
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pci_devfn,
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| 207 |
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bar,
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| 208 |
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0x00000000);
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| 209 |
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}
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| 210 |
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| 211 |
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DBG(" at 0x%.8x [size=0x%x]\n", bar_value, bar_size);
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| 212 |
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| 213 |
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bar_nr++;
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| 214 |
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}
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| 215 |
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| 216 |
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}
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| 217 |
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| 218 |
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void __init
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| 219 |
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pciauto_prescan_setup_bridge(struct pci_channel *hose,
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| 220 |
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int top_bus,
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| 221 |
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int current_bus,
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| 222 |
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int pci_devfn,
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| 223 |
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int sub_bus)
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| 224 |
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{
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| 225 |
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/* Configure bus number registers */
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| 226 |
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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| 227 |
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PCI_PRIMARY_BUS, current_bus);
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| 228 |
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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| 229 |
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PCI_SECONDARY_BUS, sub_bus + 1);
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| 230 |
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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| 231 |
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PCI_SUBORDINATE_BUS, 0xff);
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| 232 |
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|
| 233 |
|
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/* Align memory and I/O to 1MB and 4KB boundaries. */
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| 234 |
|
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pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
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| 235 |
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& ~(0x100000 - 1);
|
| 236 |
|
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pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
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| 237 |
|
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& ~(0x1000 - 1);
|
| 238 |
|
|
|
| 239 |
|
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/* Set base (lower limit) of address range behind bridge. */
|
| 240 |
|
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
|
| 241 |
|
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PCI_MEMORY_BASE, pciauto_lower_memspc >> 16);
|
| 242 |
|
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
|
| 243 |
|
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PCI_IO_BASE, (pciauto_lower_iospc & 0x0000f000) >> 8);
|
| 244 |
|
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
|
| 245 |
|
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PCI_IO_BASE_UPPER16, pciauto_lower_iospc >> 16);
|
| 246 |
|
|
|
| 247 |
|
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/* We don't support prefetchable memory for now, so disable */
|
| 248 |
|
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
|
| 249 |
|
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PCI_PREF_MEMORY_BASE, 0);
|
| 250 |
|
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
|
| 251 |
|
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PCI_PREF_MEMORY_LIMIT, 0);
|
| 252 |
|
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}
|
| 253 |
|
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|
| 254 |
|
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void __init
|
| 255 |
|
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pciauto_postscan_setup_bridge(struct pci_channel *hose,
|
| 256 |
|
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int top_bus,
|
| 257 |
|
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int current_bus,
|
| 258 |
|
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int pci_devfn,
|
| 259 |
|
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int sub_bus)
|
| 260 |
|
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{
|
| 261 |
|
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u32 temp;
|
| 262 |
|
|
|
| 263 |
|
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/*
|
| 264 |
|
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* [jsun] we always bump up baselines a little, so that if there
|
| 265 |
|
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* nothing behind P2P bridge, we don't wind up overlapping IO/MEM
|
| 266 |
|
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* spaces.
|
| 267 |
|
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*/
|
| 268 |
|
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pciauto_lower_memspc += 1;
|
| 269 |
|
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pciauto_lower_iospc += 1;
|
| 270 |
|
|
|
| 271 |
|
|
/* Configure bus number registers */
|
| 272 |
|
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
|
| 273 |
|
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PCI_SUBORDINATE_BUS, sub_bus);
|
| 274 |
|
|
|
| 275 |
|
|
/* Set upper limit of address range behind bridge. */
|
| 276 |
|
|
early_write_config_word(hose, top_bus, current_bus, pci_devfn,
|
| 277 |
|
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PCI_MEMORY_LIMIT, pciauto_lower_memspc >> 16);
|
| 278 |
|
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
|
| 279 |
|
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PCI_IO_LIMIT, (pciauto_lower_iospc & 0x0000f000) >> 8);
|
| 280 |
|
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early_write_config_word(hose, top_bus, current_bus, pci_devfn,
|
| 281 |
|
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PCI_IO_LIMIT_UPPER16, pciauto_lower_iospc >> 16);
|
| 282 |
|
|
|
| 283 |
|
|
/* Align memory and I/O to 1MB and 4KB boundaries. */
|
| 284 |
|
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pciauto_lower_memspc = (pciauto_lower_memspc + (0x100000 - 1))
|
| 285 |
|
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& ~(0x100000 - 1);
|
| 286 |
|
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pciauto_lower_iospc = (pciauto_lower_iospc + (0x1000 - 1))
|
| 287 |
|
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& ~(0x1000 - 1);
|
| 288 |
|
|
|
| 289 |
|
|
/* Enable memory and I/O accesses, enable bus master */
|
| 290 |
|
|
early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
|
| 291 |
|
|
PCI_COMMAND, &temp);
|
| 292 |
|
|
early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
|
| 293 |
|
|
PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
|
| 294 |
|
|
| PCI_COMMAND_MASTER);
|
| 295 |
|
|
}
|
| 296 |
|
|
|
| 297 |
|
|
void __init
|
| 298 |
|
|
pciauto_prescan_setup_cardbus_bridge(struct pci_channel *hose,
|
| 299 |
|
|
int top_bus,
|
| 300 |
|
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int current_bus,
|
| 301 |
|
|
int pci_devfn,
|
| 302 |
|
|
int sub_bus)
|
| 303 |
|
|
{
|
| 304 |
|
|
/* Configure bus number registers */
|
| 305 |
|
|
early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
|
| 306 |
|
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PCI_PRIMARY_BUS, current_bus);
|
| 307 |
|
|
early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
|
| 308 |
|
|
PCI_SECONDARY_BUS, sub_bus + 1);
|
| 309 |
|
|
early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
|
| 310 |
|
|
PCI_SUBORDINATE_BUS, 0xff);
|
| 311 |
|
|
|
| 312 |
|
|
/* Align memory and I/O to 4KB and 4 byte boundaries. */
|
| 313 |
|
|
pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
|
| 314 |
|
|
& ~(0x1000 - 1);
|
| 315 |
|
|
pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
|
| 316 |
|
|
& ~(0x4 - 1);
|
| 317 |
|
|
|
| 318 |
|
|
early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
|
| 319 |
|
|
PCI_CB_MEMORY_BASE_0, pciauto_lower_memspc);
|
| 320 |
|
|
early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
|
| 321 |
|
|
PCI_CB_IO_BASE_0, pciauto_lower_iospc);
|
| 322 |
|
|
}
|
| 323 |
|
|
|
| 324 |
|
|
void __init
|
| 325 |
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pciauto_postscan_setup_cardbus_bridge(struct pci_channel *hose,
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| 326 |
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int top_bus,
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| 327 |
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int current_bus,
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| 328 |
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int pci_devfn,
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| 329 |
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int sub_bus)
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| 330 |
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{
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| 331 |
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u32 temp;
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| 332 |
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| 333 |
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/*
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| 334 |
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* Configure subordinate bus number. The PCI subsystem
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| 335 |
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* bus scan will renumber buses (reserving three additional
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| 336 |
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* for this PCI<->CardBus bridge for the case where a CardBus
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| 337 |
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* adapter contains a P2P or CB2CB bridge.
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| 338 |
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*/
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| 339 |
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| 340 |
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early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
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| 341 |
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PCI_SUBORDINATE_BUS, sub_bus);
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| 342 |
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| 343 |
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/*
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| 344 |
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* Reserve an additional 4MB for mem space and 16KB for
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| 345 |
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* I/O space. This should cover any additional space
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| 346 |
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* requirement of unusual CardBus devices with
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| 347 |
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* additional bridges that can consume more address space.
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| 348 |
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*
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| 349 |
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* Although pcmcia-cs currently will reprogram bridge
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| 350 |
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* windows, the goal is to add an option to leave them
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| 351 |
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* alone and use the bridge window ranges as the regions
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| 352 |
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* that are searched for free resources upon hot-insertion
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| 353 |
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* of a device. This will allow a PCI<->CardBus bridge
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| 354 |
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* configured by this routine to happily live behind a
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| 355 |
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* P2P bridge in a system.
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| 356 |
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*/
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| 357 |
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pciauto_lower_memspc += 0x00400000;
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| 358 |
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pciauto_lower_iospc += 0x00004000;
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| 359 |
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| 360 |
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/* Align memory and I/O to 4KB and 4 byte boundaries. */
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| 361 |
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pciauto_lower_memspc = (pciauto_lower_memspc + (0x1000 - 1))
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| 362 |
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& ~(0x1000 - 1);
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| 363 |
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pciauto_lower_iospc = (pciauto_lower_iospc + (0x4 - 1))
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| 364 |
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& ~(0x4 - 1);
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| 365 |
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/* Set up memory and I/O filter limits, assume 32-bit I/O space */
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| 366 |
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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| 367 |
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PCI_CB_MEMORY_LIMIT_0, pciauto_lower_memspc - 1);
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| 368 |
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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| 369 |
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PCI_CB_IO_LIMIT_0, pciauto_lower_iospc - 1);
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| 370 |
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| 371 |
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/* Enable memory and I/O accesses, enable bus master */
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| 372 |
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early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
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| 373 |
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PCI_COMMAND, &temp);
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| 374 |
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early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
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| 375 |
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PCI_COMMAND, temp | PCI_COMMAND_IO | PCI_COMMAND_MEMORY
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| 376 |
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| PCI_COMMAND_MASTER);
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| 377 |
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}
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| 378 |
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| 379 |
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#define PCIAUTO_IDE_MODE_MASK 0x05
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| 380 |
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| 381 |
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int __init
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| 382 |
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pciauto_bus_scan(struct pci_channel *hose, int top_bus, int current_bus)
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| 383 |
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{
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| 384 |
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int sub_bus;
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| 385 |
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u32 pci_devfn, pci_class, cmdstat, found_multi=0;
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| 386 |
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unsigned short vid, did;
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| 387 |
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unsigned char header_type;
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| 388 |
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int devfn_start = 0;
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| 389 |
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int devfn_stop = 0xff;
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| 390 |
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| 391 |
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sub_bus = current_bus;
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| 392 |
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| 393 |
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if (hose->first_devfn)
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| 394 |
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devfn_start = hose->first_devfn;
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| 395 |
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if (hose->last_devfn)
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| 396 |
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devfn_stop = hose->last_devfn;
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| 397 |
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| 398 |
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for (pci_devfn=devfn_start; pci_devfn<devfn_stop; pci_devfn++) {
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| 399 |
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| 400 |
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if (PCI_FUNC(pci_devfn) && !found_multi)
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| 401 |
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continue;
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| 402 |
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| 403 |
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early_read_config_word(hose, top_bus, current_bus, pci_devfn,
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| 404 |
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PCI_VENDOR_ID, &vid);
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| 405 |
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| 406 |
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if (vid == 0xffff) continue;
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| 407 |
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| 408 |
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early_read_config_byte(hose, top_bus, current_bus, pci_devfn,
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| 409 |
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PCI_HEADER_TYPE, &header_type);
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| 410 |
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| 411 |
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if (!PCI_FUNC(pci_devfn))
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| 412 |
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found_multi = header_type & 0x80;
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| 413 |
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| 414 |
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early_read_config_word(hose, top_bus, current_bus, pci_devfn,
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| 415 |
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PCI_DEVICE_ID, &did);
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| 416 |
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| 417 |
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early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
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| 418 |
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PCI_CLASS_REVISION, &pci_class);
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| 419 |
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| 420 |
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DBG("%.2x:%.2x.%x Class %.4x: %.4x:%.4x",
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| 421 |
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current_bus, PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn),
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| 422 |
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pci_class >> 16, vid, did);
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| 423 |
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if (pci_class & 0xff)
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| 424 |
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DBG(" (rev %.2x)", pci_class & 0xff);
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| 425 |
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DBG("\n");
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| 426 |
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| 427 |
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if ((pci_class >> 16) == PCI_CLASS_BRIDGE_PCI) {
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| 428 |
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DBG(" Bridge: primary=%.2x, secondary=%.2x\n",
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| 429 |
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current_bus, sub_bus + 1);
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| 430 |
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pciauto_setup_bars(hose, top_bus, current_bus,
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| 431 |
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pci_devfn, PCI_BASE_ADDRESS_1);
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| 432 |
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pciauto_prescan_setup_bridge(hose, top_bus, current_bus,
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| 433 |
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pci_devfn, sub_bus);
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| 434 |
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DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
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| 435 |
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sub_bus + 1,
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| 436 |
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pciauto_lower_iospc, pciauto_lower_memspc);
|
| 437 |
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sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
|
| 438 |
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DBG("Back to bus %.2x\n", current_bus);
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| 439 |
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pciauto_postscan_setup_bridge(hose, top_bus, current_bus,
|
| 440 |
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pci_devfn, sub_bus);
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| 441 |
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continue;
|
| 442 |
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} else if ((pci_class >> 16) == PCI_CLASS_BRIDGE_CARDBUS) {
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| 443 |
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DBG(" CARDBUS Bridge: primary=%.2x, secondary=%.2x\n",
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| 444 |
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current_bus, sub_bus + 1);
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| 445 |
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DBG("PCI Autoconfig: Found CardBus bridge, device %d function %d\n", PCI_SLOT(pci_devfn), PCI_FUNC(pci_devfn));
|
| 446 |
|
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/* Place CardBus Socket/ExCA registers */
|
| 447 |
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pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_0);
|
| 448 |
|
|
|
| 449 |
|
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pciauto_prescan_setup_cardbus_bridge(hose, top_bus,
|
| 450 |
|
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current_bus, pci_devfn, sub_bus);
|
| 451 |
|
|
|
| 452 |
|
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DBG("Scanning sub bus %.2x, I/O 0x%.8x, Mem 0x%.8x\n",
|
| 453 |
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sub_bus + 1,
|
| 454 |
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pciauto_lower_iospc, pciauto_lower_memspc);
|
| 455 |
|
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sub_bus = pciauto_bus_scan(hose, top_bus, sub_bus+1);
|
| 456 |
|
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DBG("Back to bus %.2x, sub_bus is %x\n", current_bus, sub_bus);
|
| 457 |
|
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pciauto_postscan_setup_cardbus_bridge(hose, top_bus,
|
| 458 |
|
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current_bus, pci_devfn, sub_bus);
|
| 459 |
|
|
continue;
|
| 460 |
|
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} else if ((pci_class >> 16) == PCI_CLASS_STORAGE_IDE) {
|
| 461 |
|
|
|
| 462 |
|
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unsigned char prg_iface;
|
| 463 |
|
|
|
| 464 |
|
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early_read_config_byte(hose, top_bus, current_bus,
|
| 465 |
|
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pci_devfn, PCI_CLASS_PROG, &prg_iface);
|
| 466 |
|
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if (!(prg_iface & PCIAUTO_IDE_MODE_MASK)) {
|
| 467 |
|
|
DBG("Skipping legacy mode IDE controller\n");
|
| 468 |
|
|
continue;
|
| 469 |
|
|
}
|
| 470 |
|
|
}
|
| 471 |
|
|
|
| 472 |
|
|
/*
|
| 473 |
|
|
* Found a peripheral, enable some standard
|
| 474 |
|
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* settings
|
| 475 |
|
|
*/
|
| 476 |
|
|
early_read_config_dword(hose, top_bus, current_bus, pci_devfn,
|
| 477 |
|
|
PCI_COMMAND, &cmdstat);
|
| 478 |
|
|
early_write_config_dword(hose, top_bus, current_bus, pci_devfn,
|
| 479 |
|
|
PCI_COMMAND, cmdstat | PCI_COMMAND_IO |
|
| 480 |
|
|
PCI_COMMAND_MEMORY |
|
| 481 |
|
|
PCI_COMMAND_MASTER);
|
| 482 |
|
|
early_write_config_byte(hose, top_bus, current_bus, pci_devfn,
|
| 483 |
|
|
PCI_LATENCY_TIMER, 0x80);
|
| 484 |
|
|
|
| 485 |
|
|
/* Allocate PCI I/O and/or memory space */
|
| 486 |
|
|
pciauto_setup_bars(hose, top_bus, current_bus, pci_devfn, PCI_BASE_ADDRESS_5);
|
| 487 |
|
|
}
|
| 488 |
|
|
return sub_bus;
|
| 489 |
|
|
}
|
| 490 |
|
|
|
| 491 |
|
|
int __init
|
| 492 |
|
|
pciauto_assign_resources(int busno, struct pci_channel *hose)
|
| 493 |
|
|
{
|
| 494 |
|
|
/* setup resource limits */
|
| 495 |
|
|
io_resource_inuse = hose->io_resource;
|
| 496 |
|
|
mem_resource_inuse = hose->mem_resource;
|
| 497 |
|
|
|
| 498 |
|
|
pciauto_lower_iospc = io_resource_inuse->start;
|
| 499 |
|
|
pciauto_upper_iospc = io_resource_inuse->end + 1;
|
| 500 |
|
|
pciauto_lower_memspc = mem_resource_inuse->start;
|
| 501 |
|
|
pciauto_upper_memspc = mem_resource_inuse->end + 1;
|
| 502 |
|
|
DBG("Autoconfig PCI channel 0x%p\n", hose);
|
| 503 |
|
|
DBG("Scanning bus %.2x, I/O 0x%.8x:0x%.8x, Mem 0x%.8x:0x%.8x\n",
|
| 504 |
|
|
busno, pciauto_lower_iospc, pciauto_upper_iospc,
|
| 505 |
|
|
pciauto_lower_memspc, pciauto_upper_memspc);
|
| 506 |
|
|
|
| 507 |
|
|
return pciauto_bus_scan(hose, busno, busno);
|
| 508 |
|
|
}
|
