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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [mips/] [sni/] [int-handler.S] - Blame information for rev 1275

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1 1275 phoenix 
/*
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 * SNI RM200 PCI specific interrupt handler code.
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 *
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 * Copyright (C) 1994, 95, 96, 97, 98, 1999, 2000, 01 by Ralf Baechle
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 */
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#include
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#include
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#include
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#include
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#include
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/*
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 * The PCI ASIC has the nasty property that it may delay writes if it is busy.
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 * As a consequence from writes that have not graduated when we exit from the
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 * interrupt handler we might catch a spurious interrupt.  To avoid this we
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 * force the PCI ASIC to graduate all writes by executing a read from the
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 * PCI bus.
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 */
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                .set    noreorder
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                .set    noat
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                .align  5
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                NESTED(sni_rm200_pci_handle_int, PT_SIZE, sp)
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                SAVE_ALL
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                CLI
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                .set    at
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                /* Blinken light ...  */
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                lb      t0, led_cache
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                addiu   t0, 1
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                sb      t0, led_cache
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                sb      t0, PCIMT_CSLED                 # write only register
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                .data
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led_cache:      .byte   0
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                .text
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                mfc0    t0, CP0_STATUS
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                mfc0    t1, CP0_CAUSE
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                and     t0, t1
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                 andi   t1, t0, 0x4a00                  # hardware interrupt 1
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                bnez    t1, _hwint134
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                 andi   t1, t0, 0x1000                  # hardware interrupt 2
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                bnez    t1, _hwint2
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                 andi   t1, t0, 0x8000                  # hardware interrupt 5
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                bnez    t1, _hwint5
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                 andi   t1, t0, 0x0400                  # hardware interrupt 0
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                bnez    t1, _hwint0
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                 nop
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                j       ret_from_irq                    # spurious interrupt
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                 nop
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 ##############################################################################
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/* hwint0 should deal with MP agent, ASIC PCI, EISA NMI and debug
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   button interrupts.  */
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_hwint0:        jal     pciasic_hwint0
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                 move   a1, sp
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/*
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 * hwint 1 deals with EISA and SCSI interrupts,
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 * hwint 3 should deal with the PCI A - D interrupts,
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 * hwint 4 is used for only the onboard PCnet 32.
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 */
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_hwint134:      jal     pciasic_hwint134
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/* This interrupt was used for the com1 console on the first prototypes.  */
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_hwint2:        jal     pciasic_hwint2
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/* hwint5 is the r4k count / compare interrupt  */
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_hwint5:        jal     pciasic_hwint5
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                END(sni_rm200_pci_handle_int)

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