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1275 |
phoenix |
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 1994 - 1999 by Ralf Baechle
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* Copyright (C) 1999 Silicon Graphics
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* Copyright (C) 2002 Maciej W. Rozycki
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*
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* Low level exception handling
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*/
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#include
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#include
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#include
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#include
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#include
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#include
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#include
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#include
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#include
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BUILD_HANDLER adel ade ade silent /* #4 */
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BUILD_HANDLER ades ade ade silent /* #5 */
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BUILD_HANDLER ibe be cli silent /* #6 */
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BUILD_HANDLER dbe be cli silent /* #7 */
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BUILD_HANDLER bp bp sti silent /* #9 */
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BUILD_HANDLER ri ri sti silent /* #10 */
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BUILD_HANDLER cpu cpu sti silent /* #11 */
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BUILD_HANDLER ov ov sti silent /* #12 */
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BUILD_HANDLER tr tr sti silent /* #13 */
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BUILD_HANDLER fpe fpe fpe silent /* #15 */
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BUILD_HANDLER mdmx mdmx sti silent /* #22 */
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BUILD_HANDLER watch watch sti verbose /* #23 */
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BUILD_HANDLER mcheck mcheck cli verbose /* #24 */
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BUILD_HANDLER reserved reserved sti verbose /* others */
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__INIT
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/* A temporary overflow handler used by check_daddi(). */
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BUILD_HANDLER daddi_ov daddi_ov none silent /* #12 */
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/* General exception handler for CPUs with virtual coherency exception.
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*
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* Be careful when changing this, it has to be at most 256 (as a special
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* exception) bytes to fit into space reserved for the exception handler.
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*/
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.set push
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.set noat
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NESTED(except_vec3_r4000, 0, sp)
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mfc0 k1, CP0_CAUSE
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li k0, 31<<2
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andi k1, k1, 0x7c
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.set push
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.set noreorder
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.set nomacro
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beq k1, k0, handle_vced
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li k0, 14<<2
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beq k1, k0, handle_vcei
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dsll k1, k1, 1
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.set pop
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ld k0, exception_handlers(k1)
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jr k0
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/*
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* Big shit, we now may have two dirty primary cache lines for the same
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* physical address. We can savely invalidate the line pointed to by
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* c0_badvaddr because after return from this exception handler the load /
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* store will be re-executed.
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*/
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handle_vced:
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dmfc0 k0, CP0_BADVADDR
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li k1, -4 # Is this ...
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and k0, k1 # ... really needed?
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mtc0 zero, CP0_TAGLO
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cache Index_Store_Tag_D,(k0)
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cache Hit_Writeback_Inv_SD,(k0)
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dla k0, vced_count
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lw k1, (k0)
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addiu k1, 1
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sw k1, (k0)
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eret
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handle_vcei:
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dmfc0 k0, CP0_BADVADDR
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cache Hit_Writeback_Inv_SD,(k0) # also cleans pi
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dla k0, vcei_count
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lw k1, (k0)
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addiu k1, 1
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sw k1, (k0)
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eret
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END(except_vec3_r4000)
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.set pop
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/* General exception vector for all other CPUs.
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*
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* Be careful when changing this, it has to be at most 128 bytes
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* to fit into space reserved for the exception handler.
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*/
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.set push
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.set noat
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NESTED(except_vec3_generic, 0, sp)
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#if R5432_CP0_INTERRUPT_WAR
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mfc0 k0, CP0_INDEX
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#endif
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mfc0 k1, CP0_CAUSE
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andi k1, k1, 0x7c
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dsll k1, k1, 1
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ld k0, exception_handlers(k1)
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jr k0
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END(except_vec3_generic)
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.set pop
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/*
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* Special interrupt vector for MIPS64 ISA & embedded MIPS processors.
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* This is a dedicated interrupt exception vector which reduces the
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* interrupt processing overhead. The jump instruction will be replaced
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* at the initialization time.
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*
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* Be careful when changing this, it has to be at most 128 bytes
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* to fit into space reserved for the exception handler.
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*/
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NESTED(except_vec4, 0, sp)
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1: j 1b /* Dummy, will be replaced */
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END(except_vec4)
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__FINIT
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