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/*
 * This file is subject to the terms and conditions of the GNU General Public
 * License.  See the file "COPYING" in the main directory of this archive
 * for more details.
 *
 * Copyright (C) 1994, 1995, 1996, 1998, 1999 by Ralf Baechle
 * Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)
 * Copyright (C) 1994, 1995, 1996, by Andreas Busse
 * Copyright (C) 1999 Silicon Graphics, Inc.
 */
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
#include 
 
#include 
 
        .set    mips3
 
#define PF_USEDFPU      0x00100000      /* task used FPU this quantum (SMP) */
#define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS)
 
/*
 * [jsun] FPU context is saved if and only if the process has used FPU in
 * the current run (PF_USEDFPU).  In any case, the CU1 bit for user space
 * STATUS register should be 0, so that a process *always* starts its
 * userland with FPU disabled after each context switch.
 *
 * FPU will be enabled as soon as the process accesses FPU again, through
 * do_cpu() trap.
 */
 
/*
 * task_struct *resume(task_struct *prev, task_struct *next)
 */
        .set    noreorder
        .align  5
        LEAF(resume)
        mfc0    t1, CP0_STATUS
        sd      t1, THREAD_STATUS(a0)
        cpu_save_nonscratch a0
        sd      ra, THREAD_REG31(a0)
 
        /*
         * check if we need to save FPU registers
         */
        ld      t0, TASK_FLAGS(a0)
        li      t1, PF_USEDFPU
        and     t2, t0, t1
        beqz    t2, 1f
        nor     t1, zero, t1
 
        /*
         * clear PF_USEDFPU bit in task flags
         */
        and     t0, t0, t1
        sd      t0, TASK_FLAGS(a0)
 
        /*
         * clear saved user stack CU1 bit
         */
        ld      t0, ST_OFF(a0)
        li      t1, ~ST0_CU1
        and     t0, t0, t1
        sd      t0, ST_OFF(a0)
 
 
        sll     t2, t0, 5
        bgez    t2, 2f
        sdc1    $f0, (THREAD_FPU + 0x00)(a0)
        fpu_save_16odd a0
2:
        fpu_save_16even a0 t1                   # clobbers t1
1:
 
        /*
         * The order of restoring the registers takes care of the race
         * updating $28, $29 and kernelsp without disabling ints.
         */
        move    $28, a1
        cpu_restore_nonscratch $28
 
        daddiu  a1, $28, KERNEL_STACK_SIZE-32
        set_saved_sp    a1, t0, t1
 
        mfc0    t1, CP0_STATUS          /* Do we really need this? */
        li      a3, 0xff00
        and     t1, a3
        ld      a2, THREAD_STATUS($28)
        nor     a3, $0, a3
        and     a2, a3
        or      a2, t1
        mtc0    a2, CP0_STATUS
        jr      ra
         move   v0, a0
        END(resume)
 
/*
 * Save a thread's fp context.
 */
        .set    noreorder
LEAF(_save_fp)
        mfc0    t0, CP0_STATUS
        sll     t1, t0, 5
        bgez    t1, 1f                          # 16 register mode?
         nop
        fpu_save_16odd a0
1:
        fpu_save_16even a0 t1                   # clobbers t1
        jr      ra
         sdc1   $f0, (THREAD_FPU + 0x00)(a0)
        END(_save_fp)
 
/*
 * Restore a thread's fp context.
 */
LEAF(_restore_fp)
        mfc0    t0, CP0_STATUS
        sll     t1, t0, 5
        bgez    t1, 1f                          # 16 register mode?
         nop
 
        fpu_restore_16odd a0
1:
        fpu_restore_16even a0, t0               # clobbers t0
 
        jr      ra
         ldc1   $f0, (THREAD_FPU + 0x00)(a0)
        END(_restore_fp)
 
/*
 * Load the FPU with signalling NANS.  This bit pattern we're using has
 * the property that no matter whether considered as single or as double
 * precision represents signaling NANS.
 *
 * We initialize fcr31 to rounding to nearest, no exceptions.
 */
 
#define FPU_DEFAULT  0x00000000
 
LEAF(_init_fpu)
        mfc0    t0, CP0_STATUS
        li      t1, ST0_CU1
        or      t0, t1
        mtc0    t0, CP0_STATUS
        FPU_ENABLE_HAZARD
        sll     t0, t0, 5
 
        li      t1, FPU_DEFAULT
        ctc1    t1, fcr31
 
        bgez    t0, 1f                          # 16 / 32 register mode?
         li     t0, -1
 
        dmtc1   t0, $f1
        dmtc1   t0, $f3
        dmtc1   t0, $f5
        dmtc1   t0, $f7
        dmtc1   t0, $f9
        dmtc1   t0, $f11
        dmtc1   t0, $f13
        dmtc1   t0, $f15
        dmtc1   t0, $f17
        dmtc1   t0, $f19
        dmtc1   t0, $f21
        dmtc1   t0, $f23
        dmtc1   t0, $f25
        dmtc1   t0, $f27
        dmtc1   t0, $f29
        dmtc1   t0, $f31
 
1:      dmtc1   t0, $f0
        dmtc1   t0, $f2
        dmtc1   t0, $f4
        dmtc1   t0, $f6
        dmtc1   t0, $f8
        dmtc1   t0, $f10
        dmtc1   t0, $f12
        dmtc1   t0, $f14
        dmtc1   t0, $f16
        dmtc1   t0, $f18
        dmtc1   t0, $f20
        dmtc1   t0, $f22
        dmtc1   t0, $f24
        dmtc1   t0, $f26
        dmtc1   t0, $f28
        jr      ra
         dmtc1  t0, $f30
        END(_init_fpu)

Line No.	Rev	Author	Line
1	1275	phoenix	`/*`
2			`* This file is subject to the terms and conditions of the GNU General Public`
3			`* License. See the file "COPYING" in the main directory of this archive`
4			`* for more details.`
5			`*`
6			`* Copyright (C) 1994, 1995, 1996, 1998, 1999 by Ralf Baechle`
7			`* Copyright (C) 1996 David S. Miller (dm@engr.sgi.com)`
8			`* Copyright (C) 1994, 1995, 1996, by Andreas Busse`
9			`* Copyright (C) 1999 Silicon Graphics, Inc.`
10			`*/`
11			`#include`
12			`#include`
13			`#include`
14			`#include`
15			`#include`
16			`#include`
17			`#include`
18			`#include`
19			`#include`
20			`#include`
21
22			`#include`
23
24			`.set mips3`
25
26			`#define PF_USEDFPU 0x00100000 /* task used FPU this quantum (SMP) */`
27			`#define ST_OFF (KERNEL_STACK_SIZE - 32 - PT_SIZE + PT_STATUS)`
28
29			`/*`
30			`* [jsun] FPU context is saved if and only if the process has used FPU in`
31			`* the current run (PF_USEDFPU). In any case, the CU1 bit for user space`
32			`* STATUS register should be 0, so that a process always starts its`
33			`* userland with FPU disabled after each context switch.`
34			`*`
35			`* FPU will be enabled as soon as the process accesses FPU again, through`
36			`* do_cpu() trap.`
37			`*/`
38
39			`/*`
40			`* task_struct resume(task_struct prev, task_struct *next)`
41			`*/`
42			`.set noreorder`
43			`.align 5`
44			`LEAF(resume)`
45			`mfc0 t1, CP0_STATUS`
46			`sd t1, THREAD_STATUS(a0)`
47			`cpu_save_nonscratch a0`
48			`sd ra, THREAD_REG31(a0)`
49
50			`/*`
51			`* check if we need to save FPU registers`
52			`*/`
53			`ld t0, TASK_FLAGS(a0)`
54			`li t1, PF_USEDFPU`
55			`and t2, t0, t1`
56			`beqz t2, 1f`
57			`nor t1, zero, t1`
58
59			`/*`
60			`* clear PF_USEDFPU bit in task flags`
61			`*/`
62			`and t0, t0, t1`
63			`sd t0, TASK_FLAGS(a0)`
64
65			`/*`
66			`* clear saved user stack CU1 bit`
67			`*/`
68			`ld t0, ST_OFF(a0)`
69			`li t1, ~ST0_CU1`
70			`and t0, t0, t1`
71			`sd t0, ST_OFF(a0)`
72
73
74			`sll t2, t0, 5`
75			`bgez t2, 2f`
76			`sdc1 $f0, (THREAD_FPU + 0x00)(a0)`
77			`fpu_save_16odd a0`
78			`2:`
79			`fpu_save_16even a0 t1 # clobbers t1`
80			`1:`
81
82			`/*`
83			`* The order of restoring the registers takes care of the race`
84			`* updating $28, $29 and kernelsp without disabling ints.`
85			`*/`
86			`move $28, a1`
87			`cpu_restore_nonscratch $28`
88
89			`daddiu a1, $28, KERNEL_STACK_SIZE-32`
90			`set_saved_sp a1, t0, t1`
91
92			`mfc0 t1, CP0_STATUS /* Do we really need this? */`
93			`li a3, 0xff00`
94			`and t1, a3`
95			`ld a2, THREAD_STATUS($28)`
96			`nor a3, $0, a3`
97			`and a2, a3`
98			`or a2, t1`
99			`mtc0 a2, CP0_STATUS`
100			`jr ra`
101			`move v0, a0`
102			`END(resume)`
103
104			`/*`
105			`* Save a thread's fp context.`
106			`*/`
107			`.set noreorder`
108			`LEAF(_save_fp)`
109			`mfc0 t0, CP0_STATUS`
110			`sll t1, t0, 5`
111			`bgez t1, 1f # 16 register mode?`
112			`nop`
113			`fpu_save_16odd a0`
114			`1:`
115			`fpu_save_16even a0 t1 # clobbers t1`
116			`jr ra`
117			`sdc1 $f0, (THREAD_FPU + 0x00)(a0)`
118			`END(_save_fp)`
119
120			`/*`
121			`* Restore a thread's fp context.`
122			`*/`
123			`LEAF(_restore_fp)`
124			`mfc0 t0, CP0_STATUS`
125			`sll t1, t0, 5`
126			`bgez t1, 1f # 16 register mode?`
127			`nop`
128
129			`fpu_restore_16odd a0`
130			`1:`
131			`fpu_restore_16even a0, t0 # clobbers t0`
132
133			`jr ra`
134			`ldc1 $f0, (THREAD_FPU + 0x00)(a0)`
135			`END(_restore_fp)`
136
137			`/*`
138			`* Load the FPU with signalling NANS. This bit pattern we're using has`
139			`* the property that no matter whether considered as single or as double`
140			`* precision represents signaling NANS.`
141			`*`
142			`* We initialize fcr31 to rounding to nearest, no exceptions.`
143			`*/`
144
145			`#define FPU_DEFAULT 0x00000000`
146
147			`LEAF(_init_fpu)`
148			`mfc0 t0, CP0_STATUS`
149			`li t1, ST0_CU1`
150			`or t0, t1`
151			`mtc0 t0, CP0_STATUS`
152			`FPU_ENABLE_HAZARD`
153			`sll t0, t0, 5`
154
155			`li t1, FPU_DEFAULT`
156			`ctc1 t1, fcr31`
157
158			`bgez t0, 1f # 16 / 32 register mode?`
159			`li t0, -1`
160
161			`dmtc1 t0, $f1`
162			`dmtc1 t0, $f3`
163			`dmtc1 t0, $f5`
164			`dmtc1 t0, $f7`
165			`dmtc1 t0, $f9`
166			`dmtc1 t0, $f11`
167			`dmtc1 t0, $f13`
168			`dmtc1 t0, $f15`
169			`dmtc1 t0, $f17`
170			`dmtc1 t0, $f19`
171			`dmtc1 t0, $f21`
172			`dmtc1 t0, $f23`
173			`dmtc1 t0, $f25`
174			`dmtc1 t0, $f27`
175			`dmtc1 t0, $f29`
176			`dmtc1 t0, $f31`
177
178			`1: dmtc1 t0, $f0`
179			`dmtc1 t0, $f2`
180			`dmtc1 t0, $f4`
181			`dmtc1 t0, $f6`
182			`dmtc1 t0, $f8`
183			`dmtc1 t0, $f10`
184			`dmtc1 t0, $f12`
185			`dmtc1 t0, $f14`
186			`dmtc1 t0, $f16`
187			`dmtc1 t0, $f18`
188			`dmtc1 t0, $f20`
189			`dmtc1 t0, $f22`
190			`dmtc1 t0, $f24`
191			`dmtc1 t0, $f26`
192			`dmtc1 t0, $f28`
193			`jr ra`
194			`dmtc1 t0, $f30`
195			`END(_init_fpu)`

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [mips64/] [kernel/] [r4k_switch.S] - Blame information for rev 1765