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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [mips64/] [lib/] [memset.S] - Blame information for rev 1765

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Line No. Rev Author Line
1 1275 phoenix
/*
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 * This file is subject to the terms and conditions of the GNU General Public
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 * License.  See the file "COPYING" in the main directory of this archive
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 * for more details.
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 *
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 * Copyright (C) 1998, 1999, 2000 by Ralf Baechle
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 * Copyright (C) 1999, 2000 Silicon Graphics, Inc.
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 */
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#include 
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#include 
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#include 
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#include 
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#include 
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#define EX(insn,reg,addr,handler)                       \
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9:      insn    reg, addr;                              \
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        .section __ex_table,"a";                        \
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        PTR     9b, handler;                            \
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        .previous
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#define F_FILL64(dst, offset, val, fixup)               \
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        EX(sd, val, (offset + 0x00)(dst), fixup);       \
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        EX(sd, val, (offset + 0x08)(dst), fixup);       \
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        EX(sd, val, (offset + 0x10)(dst), fixup);       \
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        EX(sd, val, (offset + 0x18)(dst), fixup);       \
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        EX(sd, val, (offset + 0x20)(dst), fixup);       \
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        EX(sd, val, (offset + 0x28)(dst), fixup);       \
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        EX(sd, val, (offset + 0x30)(dst), fixup);       \
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        EX(sd, val, (offset + 0x38)(dst), fixup)
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/*
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 * memset(void *s, int c, size_t n)
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 *
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 * a0: start of area to clear
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 * a1: char to fill with
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 * a2: size of area to clear
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 */
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        .set    noreorder
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        .align  5
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LEAF(memset)
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        beqz    a1, 1f
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         move   v0, a0                          /* result */
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        andi    a1, 0xff                        /* spread fillword */
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        dsll    t1, a1, 8
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        or      a1, t1
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        dsll    t1, a1, 16
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        or      a1, t1
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        dsll    t1, a1, 32
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        or      a1, t1
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1:
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FEXPORT(__bzero)
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        sltiu   t0, a2, 8                       /* very small region? */
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        bnez    t0, small_memset
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         andi   t0, a0, 7                       /* aligned? */
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        beqz    t0, 1f
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         dsubu  t0, 8                           /* alignment in bytes */
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#ifdef __MIPSEB__
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        EX(sdl, a1, (a0), first_fixup)          /* make dword aligned */
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#endif
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#ifdef __MIPSEL__
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        EX(sdr, a1, (a0), first_fixup)          /* make dword aligned */
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#endif
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        dsubu   a0, t0                          /* dword align ptr */
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        daddu   a2, t0                          /* correct size */
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1:      ori     t1, a2, 0x3f                    /* # of full blocks */
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        xori    t1, 0x3f
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        beqz    t1, memset_partial              /* no block to fill */
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         andi   t0, a2, 0x38
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        daddu   t1, a0                          /* end address */
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        .set    reorder
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1:      daddiu  a0, 64
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        F_FILL64(a0, -64, a1, fwd_fixup)
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        bne     t1, a0, 1b
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        .set    noreorder
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memset_partial:
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        PTR_LA  t1, 2f                          /* where to start */
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        .set    noat
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        dsrl    AT, t0, 1
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        dsubu   t1, AT
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        .set    noat
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        jr      t1
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         daddu  a0, t0                          /* dest ptr */
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        .set    push
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        .set    noreorder
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        .set    nomacro
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        F_FILL64(a0, -64, a1, partial_fixup)    /* ... but first do dwds ... */
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2:      .set    pop
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        andi    a2, 7                           /* 0 <= n <= 7 to go */
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        beqz    a2, 1f
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         daddu  a0, a2                          /* What's left */
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#ifdef __MIPSEB__
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        EX(sdr, a1, -1(a0), last_fixup)
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#endif
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#ifdef __MIPSEL__
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        EX(sdl, a1, -1(a0), last_fixup)
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#endif
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1:      jr      ra
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         move   a2, zero
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small_memset:
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        beqz    a2, 2f
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         daddu  t1, a0, a2
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1:      daddiu  a0, 1                           /* fill bytewise */
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        bne     t1, a0, 1b
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         sb     a1, -1(a0)
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2:      jr      ra                              /* done */
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         move   a2, zero
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        END(memset)
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first_fixup:
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        jr      ra
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         nop
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fwd_fixup:
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        ld      t0, THREAD_BUADDR($28)
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        andi    a2, 0x3f
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        daddu   a2, t1
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        jr      ra
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         dsubu  a2, t0
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partial_fixup:
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        ld      t0, THREAD_BUADDR($28)
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        andi    a2, 7
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        daddu   a2, t1
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        jr      ra
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         dsubu  a2, t0
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last_fixup:
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        jr      ra
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         andi   v1, a2, 7

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