| 1 |
1275 |
phoenix |
/*
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* This file is subject to the terms and conditions of the GNU General Public
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* License. See the file "COPYING" in the main directory of this archive
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* for more details.
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*
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* Copyright (C) 2003 Ralf Baechle (ralf@linux-mips.org)
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*/
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#include <linux/config.h>
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#include <linux/init.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/mm.h>
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#include <linux/module.h>
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#include <asm/cacheops.h>
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#include <asm/inst.h>
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#include <asm/io.h>
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#include <asm/page.h>
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#include <asm/pgtable.h>
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#include <asm/prefetch.h>
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#include <asm/system.h>
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#include <asm/bootinfo.h>
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#include <asm/mipsregs.h>
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#include <asm/mmu_context.h>
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#include <asm/cpu.h>
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#include <asm/war.h>
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/*
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* Maximum sizes:
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*
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* R4000 16 bytes D-cache, 128 bytes S-cache: 0x78 bytes
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* R4600 v1.7: 0x5c bytes
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* R4600 v2.0: 0x60 bytes
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* With prefetching, 16 byte strides 0xa0 bytes
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*/
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static unsigned int clear_page_array[0xa0 / 4];
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void clear_page(void * page) __attribute__((alias("clear_page_array")));
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/*
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* Maximum sizes:
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*
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* R4000 16 bytes D-cache, 128 bytes S-cache: 0xbc bytes
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* R4600 v1.7: 0x80 bytes
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* R4600 v2.0: 0x84 bytes
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* With prefetching, 16 byte strides 0xb8 bytes
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*/
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static unsigned int copy_page_array[0xb8 / 4];
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void copy_page(void *to, void *from) __attribute__((alias("copy_page_array")));
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/*
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* An address fits into a single register so it's safe to use 64-bit registers
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* if we have 64-bit adresses.
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*/
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#define cpu_has_64bit_registers cpu_has_64bit_addresses
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/*
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* This is suboptimal for 32-bit kernels; we assume that R10000 is only used
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* with 64-bit kernels. The prefetch offsets have been experimentally tuned
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* an Origin 200.
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*/
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static int pref_offset_clear __initdata = 512;
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static int pref_offset_copy __initdata = 256;
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static unsigned int pref_src_mode __initdata;
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static unsigned int pref_dst_mode __initdata;
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static int has_scache __initdata = 0;
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static int load_offset __initdata = 0;
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static int store_offset __initdata = 0;
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static unsigned int __initdata *dest, *epc;
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static inline void build_src_pref(int advance)
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{
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if (!(load_offset & (cpu_dcache_line_size() - 1))) {
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union mips_instruction mi;
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mi.i_format.opcode = pref_op;
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mi.i_format.rs = 5; /* $a1 */
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mi.i_format.rt = pref_src_mode;
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mi.i_format.simmediate = load_offset + advance;
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*epc++ = mi.word;
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}
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}
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| 90 |
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static inline void __build_load_reg(int reg)
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{
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union mips_instruction mi;
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| 94 |
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if (cpu_has_64bit_registers)
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mi.i_format.opcode = ld_op;
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else
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mi.i_format.opcode = lw_op;
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mi.i_format.rs = 5; /* $a1 */
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mi.i_format.rt = reg; /* $zero */
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mi.i_format.simmediate = load_offset;
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| 102 |
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load_offset += (cpu_has_64bit_registers ? 8 : 4);
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| 103 |
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| 104 |
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*epc++ = mi.word;
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}
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| 107 |
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static inline void build_load_reg(int reg)
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{
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if (cpu_has_prefetch)
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build_src_pref(pref_offset_copy);
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__build_load_reg(reg);
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}
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static inline void build_dst_pref(int advance)
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{
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if (!(store_offset & (cpu_dcache_line_size() - 1))) {
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union mips_instruction mi;
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mi.i_format.opcode = pref_op;
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mi.i_format.rs = 4; /* $a0 */
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mi.i_format.rt = pref_dst_mode;
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mi.i_format.simmediate = store_offset + advance;
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*epc++ = mi.word;
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}
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}
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static inline void build_cdex(void)
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{
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union mips_instruction mi;
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| 133 |
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if (cpu_has_cache_cdex_s &&
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!(store_offset & (cpu_scache_line_size() - 1))) {
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mi.c_format.opcode = cache_op;
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mi.c_format.rs = 4; /* $a0 */
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mi.c_format.c_op = 3; /* Create Dirty Exclusive */
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mi.c_format.cache = 3; /* Secondary Data Cache */
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mi.c_format.simmediate = store_offset;
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*epc++ = mi.word;
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}
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| 145 |
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if (store_offset & (cpu_dcache_line_size() - 1))
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return;
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| 147 |
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| 148 |
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if (R4600_V1_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2010)) {
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*epc++ = 0; /* nop */
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*epc++ = 0; /* nop */
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*epc++ = 0; /* nop */
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*epc++ = 0; /* nop */
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}
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mi.c_format.opcode = cache_op;
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mi.c_format.rs = 4; /* $a0 */
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mi.c_format.c_op = 3; /* Create Dirty Exclusive */
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mi.c_format.cache = 1; /* Data Cache */
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mi.c_format.simmediate = store_offset;
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| 161 |
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*epc++ = mi.word;
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}
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| 164 |
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static inline void __build_store_zero_reg(void)
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{
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union mips_instruction mi;
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| 168 |
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if (cpu_has_64bits)
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mi.i_format.opcode = sd_op;
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else
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mi.i_format.opcode = sw_op;
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mi.i_format.rs = 4; /* $a0 */
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mi.i_format.rt = 0; /* $zero */
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mi.i_format.simmediate = store_offset;
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store_offset += (cpu_has_64bits ? 8 : 4);
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| 178 |
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*epc++ = mi.word;
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}
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| 181 |
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static inline void __build_store_reg(int reg)
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{
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union mips_instruction mi;
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int reg_size;
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#ifdef CONFIG_MIPS32
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if (cpu_has_64bit_registers && reg == 0) {
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mi.i_format.opcode = sd_op;
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reg_size = 8;
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} else {
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mi.i_format.opcode = sw_op;
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reg_size = 4;
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}
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#endif
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| 195 |
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#ifdef CONFIG_MIPS64
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| 196 |
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mi.i_format.opcode = sd_op;
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| 197 |
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reg_size = 8;
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| 198 |
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#endif
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| 199 |
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mi.i_format.rs = 4; /* $a0 */
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| 200 |
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mi.i_format.rt = reg; /* $zero */
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| 201 |
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mi.i_format.simmediate = store_offset;
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| 202 |
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| 203 |
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store_offset += reg_size;
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| 204 |
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| 205 |
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*epc++ = mi.word;
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| 206 |
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}
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| 207 |
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| 208 |
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static inline void build_store_reg(int reg)
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| 209 |
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{
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| 210 |
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if (cpu_has_prefetch)
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| 211 |
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if (reg)
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| 212 |
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build_dst_pref(pref_offset_copy);
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| 213 |
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else
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| 214 |
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build_dst_pref(pref_offset_clear);
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| 215 |
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else if (cpu_has_cache_cdex_p)
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| 216 |
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build_cdex();
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| 217 |
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| 218 |
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__build_store_reg(reg);
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| 219 |
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}
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| 220 |
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| 221 |
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static inline void build_addiu_at_a0(unsigned long offset)
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| 222 |
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{
|
| 223 |
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union mips_instruction mi;
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| 224 |
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| 225 |
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BUG_ON(offset > 0x7fff);
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| 226 |
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| 227 |
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mi.i_format.opcode = cpu_has_64bit_addresses ? daddiu_op : addiu_op;
|
| 228 |
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mi.i_format.rs = 4; /* $a0 */
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| 229 |
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mi.i_format.rt = 1; /* $at */
|
| 230 |
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mi.i_format.simmediate = offset;
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| 231 |
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| 232 |
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*epc++ = mi.word;
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| 233 |
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}
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| 234 |
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| 235 |
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static inline void build_addiu_a1(unsigned long offset)
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| 236 |
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{
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| 237 |
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union mips_instruction mi;
|
| 238 |
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|
| 239 |
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BUG_ON(offset > 0x7fff);
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| 240 |
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|
| 241 |
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mi.i_format.opcode = cpu_has_64bit_addresses ? daddiu_op : addiu_op;
|
| 242 |
|
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mi.i_format.rs = 5; /* $a1 */
|
| 243 |
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mi.i_format.rt = 5; /* $a1 */
|
| 244 |
|
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mi.i_format.simmediate = offset;
|
| 245 |
|
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|
| 246 |
|
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load_offset -= offset;
|
| 247 |
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|
| 248 |
|
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*epc++ = mi.word;
|
| 249 |
|
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}
|
| 250 |
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|
| 251 |
|
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static inline void build_addiu_a0(unsigned long offset)
|
| 252 |
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{
|
| 253 |
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union mips_instruction mi;
|
| 254 |
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|
| 255 |
|
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BUG_ON(offset > 0x7fff);
|
| 256 |
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|
| 257 |
|
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mi.i_format.opcode = cpu_has_64bit_addresses ? daddiu_op : addiu_op;
|
| 258 |
|
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mi.i_format.rs = 4; /* $a0 */
|
| 259 |
|
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mi.i_format.rt = 4; /* $a0 */
|
| 260 |
|
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mi.i_format.simmediate = offset;
|
| 261 |
|
|
|
| 262 |
|
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store_offset -= offset;
|
| 263 |
|
|
|
| 264 |
|
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*epc++ = mi.word;
|
| 265 |
|
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}
|
| 266 |
|
|
|
| 267 |
|
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static inline void build_bne(unsigned int *dest)
|
| 268 |
|
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{
|
| 269 |
|
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union mips_instruction mi;
|
| 270 |
|
|
|
| 271 |
|
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mi.i_format.opcode = bne_op;
|
| 272 |
|
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mi.i_format.rs = 1; /* $at */
|
| 273 |
|
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mi.i_format.rt = 4; /* $a0 */
|
| 274 |
|
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mi.i_format.simmediate = dest - epc - 1;
|
| 275 |
|
|
|
| 276 |
|
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*epc++ = mi.word;
|
| 277 |
|
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}
|
| 278 |
|
|
|
| 279 |
|
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static inline void build_nop(void)
|
| 280 |
|
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{
|
| 281 |
|
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*epc++ = 0;
|
| 282 |
|
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}
|
| 283 |
|
|
|
| 284 |
|
|
static inline void build_jr_ra(void)
|
| 285 |
|
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{
|
| 286 |
|
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union mips_instruction mi;
|
| 287 |
|
|
|
| 288 |
|
|
mi.r_format.opcode = spec_op;
|
| 289 |
|
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mi.r_format.rs = 31;
|
| 290 |
|
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mi.r_format.rt = 0;
|
| 291 |
|
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mi.r_format.rd = 0;
|
| 292 |
|
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mi.r_format.re = 0;
|
| 293 |
|
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mi.r_format.func = jr_op;
|
| 294 |
|
|
|
| 295 |
|
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*epc++ = mi.word;
|
| 296 |
|
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}
|
| 297 |
|
|
|
| 298 |
|
|
void __init build_clear_page(void)
|
| 299 |
|
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{
|
| 300 |
|
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epc = (unsigned int *) &clear_page_array;
|
| 301 |
|
|
|
| 302 |
|
|
if (cpu_has_prefetch) {
|
| 303 |
|
|
switch (current_cpu_data.cputype) {
|
| 304 |
|
|
case CPU_R10000:
|
| 305 |
|
|
case CPU_R12000:
|
| 306 |
|
|
pref_src_mode = Pref_LoadStreamed;
|
| 307 |
|
|
pref_dst_mode = Pref_StoreRetained;
|
| 308 |
|
|
break;
|
| 309 |
|
|
default:
|
| 310 |
|
|
pref_src_mode = Pref_LoadStreamed;
|
| 311 |
|
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pref_dst_mode = Pref_PrepareForStore;
|
| 312 |
|
|
break;
|
| 313 |
|
|
}
|
| 314 |
|
|
}
|
| 315 |
|
|
|
| 316 |
|
|
build_addiu_at_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_clear : 0));
|
| 317 |
|
|
|
| 318 |
|
|
if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) {
|
| 319 |
|
|
*epc++ = 0x40026000; /* mfc0 $v0, $12 */
|
| 320 |
|
|
*epc++ = 0x34410001; /* ori $at, v0, 0x1 */
|
| 321 |
|
|
*epc++ = 0x38210001; /* xori $at, at, 0x1 */
|
| 322 |
|
|
*epc++ = 0x40816000; /* mtc0 $at, $12 */
|
| 323 |
|
|
*epc++ = 0x00000000; /* nop */
|
| 324 |
|
|
*epc++ = 0x00000000; /* nop */
|
| 325 |
|
|
*epc++ = 0x00000000; /* nop */
|
| 326 |
|
|
*epc++ = 0x3c01a000; /* lui $at, 0xa000 */
|
| 327 |
|
|
*epc++ = 0x8c200000; /* lw $zero, ($at) */
|
| 328 |
|
|
}
|
| 329 |
|
|
|
| 330 |
|
|
dest = epc;
|
| 331 |
|
|
build_store_reg(0);
|
| 332 |
|
|
build_store_reg(0);
|
| 333 |
|
|
build_store_reg(0);
|
| 334 |
|
|
build_store_reg(0);
|
| 335 |
|
|
if (has_scache && cpu_scache_line_size() == 128) {
|
| 336 |
|
|
build_store_reg(0);
|
| 337 |
|
|
build_store_reg(0);
|
| 338 |
|
|
build_store_reg(0);
|
| 339 |
|
|
build_store_reg(0);
|
| 340 |
|
|
}
|
| 341 |
|
|
build_addiu_a0(2 * store_offset);
|
| 342 |
|
|
build_store_reg(0);
|
| 343 |
|
|
build_store_reg(0);
|
| 344 |
|
|
if (has_scache && cpu_scache_line_size() == 128) {
|
| 345 |
|
|
build_store_reg(0);
|
| 346 |
|
|
build_store_reg(0);
|
| 347 |
|
|
build_store_reg(0);
|
| 348 |
|
|
build_store_reg(0);
|
| 349 |
|
|
}
|
| 350 |
|
|
build_store_reg(0);
|
| 351 |
|
|
build_bne(dest);
|
| 352 |
|
|
build_store_reg(0);
|
| 353 |
|
|
|
| 354 |
|
|
if (cpu_has_prefetch && pref_offset_clear) {
|
| 355 |
|
|
build_addiu_at_a0(pref_offset_clear);
|
| 356 |
|
|
dest = epc;
|
| 357 |
|
|
__build_store_reg(0);
|
| 358 |
|
|
__build_store_reg(0);
|
| 359 |
|
|
__build_store_reg(0);
|
| 360 |
|
|
__build_store_reg(0);
|
| 361 |
|
|
build_addiu_a0(2 * store_offset);
|
| 362 |
|
|
__build_store_reg(0);
|
| 363 |
|
|
__build_store_reg(0);
|
| 364 |
|
|
__build_store_reg(0);
|
| 365 |
|
|
build_bne(dest);
|
| 366 |
|
|
__build_store_reg(0);
|
| 367 |
|
|
}
|
| 368 |
|
|
|
| 369 |
|
|
build_jr_ra();
|
| 370 |
|
|
if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020))
|
| 371 |
|
|
*epc++ = 0x40826000; /* mtc0 $v0, $12 */
|
| 372 |
|
|
else
|
| 373 |
|
|
build_nop();
|
| 374 |
|
|
|
| 375 |
|
|
flush_icache_range((unsigned long)&clear_page_array,
|
| 376 |
|
|
(unsigned long) epc);
|
| 377 |
|
|
|
| 378 |
|
|
BUG_ON(epc > clear_page_array + ARRAY_SIZE(clear_page_array));
|
| 379 |
|
|
}
|
| 380 |
|
|
|
| 381 |
|
|
void __init build_copy_page(void)
|
| 382 |
|
|
{
|
| 383 |
|
|
epc = (unsigned int *) ©_page_array;
|
| 384 |
|
|
|
| 385 |
|
|
build_addiu_at_a0(PAGE_SIZE - (cpu_has_prefetch ? pref_offset_copy : 0));
|
| 386 |
|
|
|
| 387 |
|
|
if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020)) {
|
| 388 |
|
|
*epc++ = 0x40026000; /* mfc0 $v0, $12 */
|
| 389 |
|
|
*epc++ = 0x34410001; /* ori $at, v0, 0x1 */
|
| 390 |
|
|
*epc++ = 0x38210001; /* xori $at, at, 0x1 */
|
| 391 |
|
|
*epc++ = 0x40816000; /* mtc0 $at, $12 */
|
| 392 |
|
|
*epc++ = 0x00000000; /* nop */
|
| 393 |
|
|
*epc++ = 0x00000000; /* nop */
|
| 394 |
|
|
*epc++ = 0x00000000; /* nop */
|
| 395 |
|
|
*epc++ = 0x3c01a000; /* lui $at, 0xa000 */
|
| 396 |
|
|
*epc++ = 0x8c200000; /* lw $zero, ($at) */
|
| 397 |
|
|
}
|
| 398 |
|
|
|
| 399 |
|
|
dest = epc;
|
| 400 |
|
|
build_load_reg( 8);
|
| 401 |
|
|
build_load_reg( 9);
|
| 402 |
|
|
build_load_reg(10);
|
| 403 |
|
|
build_load_reg(11);
|
| 404 |
|
|
build_store_reg( 8);
|
| 405 |
|
|
build_store_reg( 9);
|
| 406 |
|
|
build_store_reg(10);
|
| 407 |
|
|
build_store_reg(11);
|
| 408 |
|
|
if (has_scache && cpu_scache_line_size() == 128) {
|
| 409 |
|
|
build_load_reg( 8);
|
| 410 |
|
|
build_load_reg( 9);
|
| 411 |
|
|
build_load_reg(10);
|
| 412 |
|
|
build_load_reg(11);
|
| 413 |
|
|
build_store_reg( 8);
|
| 414 |
|
|
build_store_reg( 9);
|
| 415 |
|
|
build_store_reg(10);
|
| 416 |
|
|
build_store_reg(11);
|
| 417 |
|
|
}
|
| 418 |
|
|
build_addiu_a0(2 * store_offset);
|
| 419 |
|
|
build_addiu_a1(2 * load_offset);
|
| 420 |
|
|
build_load_reg( 8);
|
| 421 |
|
|
build_load_reg( 9);
|
| 422 |
|
|
build_load_reg(10);
|
| 423 |
|
|
build_load_reg(11);
|
| 424 |
|
|
build_store_reg( 8);
|
| 425 |
|
|
build_store_reg( 9);
|
| 426 |
|
|
build_store_reg(10);
|
| 427 |
|
|
if (has_scache && cpu_scache_line_size() == 128) {
|
| 428 |
|
|
build_store_reg(11);
|
| 429 |
|
|
build_load_reg( 8);
|
| 430 |
|
|
build_load_reg( 9);
|
| 431 |
|
|
build_load_reg(10);
|
| 432 |
|
|
build_load_reg(11);
|
| 433 |
|
|
build_store_reg( 8);
|
| 434 |
|
|
build_store_reg( 9);
|
| 435 |
|
|
build_store_reg(10);
|
| 436 |
|
|
}
|
| 437 |
|
|
build_bne(dest);
|
| 438 |
|
|
build_store_reg(11);
|
| 439 |
|
|
|
| 440 |
|
|
if (cpu_has_prefetch && pref_offset_copy) {
|
| 441 |
|
|
build_addiu_at_a0(pref_offset_copy);
|
| 442 |
|
|
dest = epc;
|
| 443 |
|
|
__build_load_reg( 8);
|
| 444 |
|
|
__build_load_reg( 9);
|
| 445 |
|
|
__build_load_reg(10);
|
| 446 |
|
|
__build_load_reg(11);
|
| 447 |
|
|
__build_store_reg( 8);
|
| 448 |
|
|
__build_store_reg( 9);
|
| 449 |
|
|
__build_store_reg(10);
|
| 450 |
|
|
__build_store_reg(11);
|
| 451 |
|
|
build_addiu_a0(2 * store_offset);
|
| 452 |
|
|
build_addiu_a1(2 * load_offset);
|
| 453 |
|
|
__build_load_reg( 8);
|
| 454 |
|
|
__build_load_reg( 9);
|
| 455 |
|
|
__build_load_reg(10);
|
| 456 |
|
|
__build_load_reg(11);
|
| 457 |
|
|
__build_store_reg( 8);
|
| 458 |
|
|
__build_store_reg( 9);
|
| 459 |
|
|
__build_store_reg(10);
|
| 460 |
|
|
build_bne(dest);
|
| 461 |
|
|
__build_store_reg(11);
|
| 462 |
|
|
}
|
| 463 |
|
|
|
| 464 |
|
|
build_jr_ra();
|
| 465 |
|
|
if (R4600_V2_HIT_CACHEOP_WAR && ((read_c0_prid() & 0xfff0) == 0x2020))
|
| 466 |
|
|
*epc++ = 0x40826000; /* mtc0 $v0, $12 */
|
| 467 |
|
|
else
|
| 468 |
|
|
build_nop();
|
| 469 |
|
|
|
| 470 |
|
|
BUG_ON(epc > copy_page_array + ARRAY_SIZE(copy_page_array));
|
| 471 |
|
|
}
|
