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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [or32/] [kernel/] [misc.S] - Blame information for rev 1765

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/*
 *  linux/arch/or32/kernel/misc.S
 *
 *  or32 version
 *    author(s): Simon Srot (srot@opencores.org)
 *
 *  derived from cris, i386, m68k, ppc, sh ports.
 *
 *  changes:
 *  18. 11. 2003: Matjaz Breskvar (phoenix@opencores.org)
 *    initial port to or32 architecture
 *
 */
#include 
#include 
#include 
 
/* defined in  */
#define CLONE_VM  0x00000100
 
        /*
         * we could avoid saving of some registers
         * if we could guarantee certian functions to be inlined
         */
 
        .text
/*
 * Enable interrupts
 *      sti()
 */
        .global ___sti
___sti:
        l.addi  r1,r1,-0x4
        l.sw    0x0(r1),r3
 
        l.mfspr r3,r0,SPR_SR
        l.ori   r3,r3,(SPR_SR_IEE | SPR_SR_TEE)
        l.mtspr r0,r3,SPR_SR
        l.lwz   r3,0x0(r1)
        l.jr    r9
        l.addi  r1,r1,0x4
 
/*
 * Disable interrupts
 *      cli()
 */
        .global ___cli
___cli:
        l.addi  r1,r1,-0x8
        l.sw    0x0(r1),r4
        l.sw    0x4(r1),r3
 
//      l.sw    -0x4(r1),r4
        l.addi  r4,r0,-1
        l.xori  r4,r4,(SPR_SR_IEE | SPR_SR_TEE)
        l.mfspr r3,r0,SPR_SR
        l.and   r3,r3,r4
        l.mtspr r0,r3,SPR_SR
 
        l.lwz   r4,0x0(r1)
        l.lwz   r3,0x4(r1)
        l.jr    r9
        l.addi  r1,r1,0x8
//      l.lwz   r4,-0x4(r1)
 
/*
 * Get 'flags' (aka status register)
 *      save_flags(long *ptr)
 */
        .global ___save_flags
___save_flags:
        l.addi  r1,r1,-0x4
        l.sw    0x0(r1),r4
 
//      l.sw    -0x4(r1),r4
        l.mfspr r4,r0,SPR_SR
        l.sw    0(r3),r4
 
        l.lwz   r4,0x0(r1)
        l.jr    r9
        l.addi  r1,r1,0x4
//      l.lwz   r4,-0x4(r1)
 
/*
 * Get 'flags' and disable interrupts
 *      save_and_cli(long *ptr)
 */
        .global ___save_and_cli
___save_and_cli:
        l.addi  r1,r1,-0x8
        l.sw    0x0(r1),r4
        l.sw    0x4(r1),r3
 
//      l.sw    -0x4(r1),r4
        l.mfspr r4,r0,SPR_SR
        l.sw    0(r3),r4
        l.addi  r4,r0,-1
        l.xori  r4,r4,(SPR_SR_IEE | SPR_SR_TEE)
        l.mfspr r3,r0,SPR_SR
        l.and   r3,r3,r4
        l.mtspr r0,r3,SPR_SR
 
        l.lwz   r4,0x0(r1)
        l.lwz   r3,0x4(r1)
        l.jr    r9
        l.addi  r1,r1,0x8
//      l.lwz   r4,-0x4(r1)
 
/*
 * Restore 'flags'
 *      restore_flags(long val)
 */
        .global ___restore_flags
___restore_flags:
        l.mtspr r0,r3,SPR_SR
        l.jr    r9
        l.nop
 
/*
 * SPR write
 *      mtspr(long add, long val)
 */
        .global ___mtspr
___mtspr:
        l.mtspr r3,r4,0
        l.jr    r9
        l.nop
 
/*
 * SPR read
 *      mtspr(long add)
 */
        .global ___mfspr
___mfspr:
        l.mfspr r11,r3,0
        l.jr    r9
        l.nop
 
/*
 * Create a kernel thread
 *   arch)kernel_thread(fn, arg, flags)
 */
  .global _arch_kernel_thread
_arch_kernel_thread:
        l.addi  r1,r1,-8
        l.sw    0x0(r1),r6
        l.sw    0x4(r1),r3
 
        /* __PHX__ do we need to save the stat ??? */
        l.add   r6,r0,r3                /* function */
        l.ori   r3,r5,CLONE_VM          /* flags */
        l.addi  r11,r0,__NR_clone
        l.sys   1
        l.sfeqi r11,0                   /* parent or child? */
        l.bnf   1f                      /* return if parent */
        l.nop
        l.addi  r1,r1,-16               /* make top-level stack frame */
        l.sw    0(r1),r0
        l.jalr  r6                      /* load arg and call fn */
        l.add   r3,r0,r4
        l.add   r3,r3,r11
        l.addi  r11,r0,__NR_exit        /* exit after child exits */
        l.sys   1
1:
        l.lwz   r6,0x0(r1)
        l.lwz   r3,0x4(r1)
        l.jr    r9
        l.addi  r1,r1,8
 
#if 0
 
/*
 * Instruction cache enable
 *      ic_enable()
 */
        .global ___ic_enable
___ic_enable:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Invalidate IC */
        l.addi  r13,r0,0
        l.addi  r11,r0,IC_SIZE
1:
        l.mtspr r0,r13,SPR_ICBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,IC_LINE
 
        /* Enable IC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_ICE
        l.mtspr r0,r13,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        l.jr    r9
        l.nop
 
/*
 * Instruction cache disable
 *      ic_disable()
 */
        .global ___ic_disable
___ic_disable:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        l.jr    r9
        l.nop
 
/*
 * Instruction cache invalidate
 *      ic_flush()
 */
        .global ___ic_invalidate
___ic_invalidate:
        /* Disable IC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_ICE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Invalidate IC */
        l.addi  r13,r0,0
        l.addi  r11,r0,IC_SIZE
1:
        l.mtspr r0,r13,SPR_ICBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,IC_LINE
 
        /* Enable IC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_ICE
        l.mtspr r0,r13,SPR_SR
        l.nop
        l.nop
        l.nop
        l.nop
        l.nop
 
        l.jr    r9
        l.nop
 
/*
 * Data cache enable
 *      dc_enable()
 */
        .global ___dc_enable
___dc_enable:
  /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        /* Flush DC */
        l.addi  r13,r0,0
        l.addi  r11,r0,DC_SIZE
1:
        l.mtspr r0,r13,SPR_DCBIR
        l.sfne  r13,r11
        l.bf    1b
        l.addi  r13,r13,DC_LINE
 
        /* Enable DC */
        l.mfspr r13,r0,SPR_SR
        l.ori   r13,r13,SPR_SR_DCE
        l.mtspr r0,r13,SPR_SR
 
        l.jr    r9
        l.nop
 
/*
 * Data cache disable
 *      dc_disable()
 */
        .global ___dc_disable
___dc_disable:
        /* Disable DC */
        l.mfspr r13,r0,SPR_SR
        l.addi  r11,r0,-1
        l.xori  r11,r11,SPR_SR_DCE
        l.and   r11,r13,r11
        l.mtspr r0,r11,SPR_SR
 
        l.jr    r9
        l.nop
 
/*
 * Invalidate data cache line
 *      dc_line_invalidate(long ph_add)
 */
        .global ___dc_line_invalidate
___dc_line_invalidate:
  l.mfspr r4,r0,SPR_SR
  l.addi  r5,r0,-1
  l.xori  r5,r5,SPR_SR_DCE
  l.and   r5,r4,r5
  l.mtspr r0,r5,SPR_SR
  l.mtspr r0,r3,SPR_DCBIR
  l.mtspr r0,r4,SPR_SR
  l.jr    r9
  l.nop
 
/*
 * Data MMU enable
 *      dmmu_enable()
 */
        .global ___dmmu_enable
___dmmu_enable:
  /* Invalidate all sets */
  l.addi  r11,r0,DMMU_SET_NB
  l.addi  r13,r0,0
1:
  l.mtspr r13,r0,SPR_DTLBMR_BASE(0)
  l.addi  r11,r11,-1
  l.sfeqi r11,0
  l.bnf   1b
  l.addi  r13,r13,1
  l.mfspr r11,r0,SPR_SR
  l.ori   r11,r11,SPR_SR_DME
  l.mtspr r0,r11,SPR_SR
  l.jr    r9
  l.nop
 
/*
 * Instruction MMU enable
 *      immu_enable()
 */
        .global ___immu_enable
___immu_enable:
  /* Invalidate all sets */
  l.addi  r11,r0,IMMU_SET_NB
  l.addi  r13,r0,0
1:
  l.mtspr r13,r0,SPR_ITLBMR_BASE(0)
  l.addi  r11,r11,-1
  l.sfeqi r11,0
  l.bnf   1b
  l.addi  r13,r13,1
  l.mfspr r11,r0,SPR_SR
  l.ori   r11,r11,SPR_SR_IME
  l.mtspr r0,r11,SPR_SR
  l.nop
  l.nop
  l.nop
  l.nop
  l.jr    r9
  l.nop
#endif
 
 /*
 * Print utility
 *      print(const char *fmt, ...)
 */
        .global ___print
___print:
        l.lwz   r3,0(r1)
        l.addi  r4,r1,4
#       l.sys   202
  l.nop 3
        l.jr    r9
        l.nop
 

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [or32/] [kernel/] [misc.S] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	1275	phoenix	`/*`
2			`* linux/arch/or32/kernel/misc.S`
3			`*`
4			`* or32 version`
5			`* author(s): Simon Srot (srot@opencores.org)`
6			`*`
7			`* derived from cris, i386, m68k, ppc, sh ports.`
8			`*`
9			`* changes:`
10			`* 18. 11. 2003: Matjaz Breskvar (phoenix@opencores.org)`
11			`* initial port to or32 architecture`
12			`*`
13			`*/`
14			`#include`
15			`#include`
16			`#include`
17
18			`/* defined in */`
19			`#define CLONE_VM 0x00000100`
20
21			`/*`
22			`* we could avoid saving of some registers`
23			`* if we could guarantee certian functions to be inlined`
24			`*/`
25
26			`.text`
27			`/*`
28			`* Enable interrupts`
29			`* sti()`
30			`*/`
31			`.global ___sti`
32			`___sti:`
33			`l.addi r1,r1,-0x4`
34			`l.sw 0x0(r1),r3`
35
36			`l.mfspr r3,r0,SPR_SR`
37			`l.ori r3,r3,(SPR_SR_IEE \| SPR_SR_TEE)`
38			`l.mtspr r0,r3,SPR_SR`
39			`l.lwz r3,0x0(r1)`
40			`l.jr r9`
41			`l.addi r1,r1,0x4`
42
43			`/*`
44			`* Disable interrupts`
45			`* cli()`
46			`*/`
47			`.global ___cli`
48			`___cli:`
49			`l.addi r1,r1,-0x8`
50			`l.sw 0x0(r1),r4`
51			`l.sw 0x4(r1),r3`
52
53			`// l.sw -0x4(r1),r4`
54			`l.addi r4,r0,-1`
55			`l.xori r4,r4,(SPR_SR_IEE \| SPR_SR_TEE)`
56			`l.mfspr r3,r0,SPR_SR`
57			`l.and r3,r3,r4`
58			`l.mtspr r0,r3,SPR_SR`
59
60			`l.lwz r4,0x0(r1)`
61			`l.lwz r3,0x4(r1)`
62			`l.jr r9`
63			`l.addi r1,r1,0x8`
64			`// l.lwz r4,-0x4(r1)`
65
66			`/*`
67			`* Get 'flags' (aka status register)`
68			`* save_flags(long *ptr)`
69			`*/`
70			`.global ___save_flags`
71			`___save_flags:`
72			`l.addi r1,r1,-0x4`
73			`l.sw 0x0(r1),r4`
74
75			`// l.sw -0x4(r1),r4`
76			`l.mfspr r4,r0,SPR_SR`
77			`l.sw 0(r3),r4`
78
79			`l.lwz r4,0x0(r1)`
80			`l.jr r9`
81			`l.addi r1,r1,0x4`
82			`// l.lwz r4,-0x4(r1)`
83
84			`/*`
85			`* Get 'flags' and disable interrupts`
86			`* save_and_cli(long *ptr)`
87			`*/`
88			`.global ___save_and_cli`
89			`___save_and_cli:`
90			`l.addi r1,r1,-0x8`
91			`l.sw 0x0(r1),r4`
92			`l.sw 0x4(r1),r3`
93
94			`// l.sw -0x4(r1),r4`
95			`l.mfspr r4,r0,SPR_SR`
96			`l.sw 0(r3),r4`
97			`l.addi r4,r0,-1`
98			`l.xori r4,r4,(SPR_SR_IEE \| SPR_SR_TEE)`
99			`l.mfspr r3,r0,SPR_SR`
100			`l.and r3,r3,r4`
101			`l.mtspr r0,r3,SPR_SR`
102
103			`l.lwz r4,0x0(r1)`
104			`l.lwz r3,0x4(r1)`
105			`l.jr r9`
106			`l.addi r1,r1,0x8`
107			`// l.lwz r4,-0x4(r1)`
108
109			`/*`
110			`* Restore 'flags'`
111			`* restore_flags(long val)`
112			`*/`
113			`.global ___restore_flags`
114			`___restore_flags:`
115			`l.mtspr r0,r3,SPR_SR`
116			`l.jr r9`
117			`l.nop`
118
119			`/*`
120			`* SPR write`
121			`* mtspr(long add, long val)`
122			`*/`
123			`.global ___mtspr`
124			`___mtspr:`
125			`l.mtspr r3,r4,0`
126			`l.jr r9`
127			`l.nop`
128
129			`/*`
130			`* SPR read`
131			`* mtspr(long add)`
132			`*/`
133			`.global ___mfspr`
134			`___mfspr:`
135			`l.mfspr r11,r3,0`
136			`l.jr r9`
137			`l.nop`
138
139			`/*`
140			`* Create a kernel thread`
141			`* arch)kernel_thread(fn, arg, flags)`
142			`*/`
143			`.global _arch_kernel_thread`
144			`_arch_kernel_thread:`
145			`l.addi r1,r1,-8`
146			`l.sw 0x0(r1),r6`
147			`l.sw 0x4(r1),r3`
148
149			`/* __PHX__ do we need to save the stat ??? */`
150			`l.add r6,r0,r3 /* function */`
151			`l.ori r3,r5,CLONE_VM /* flags */`
152			`l.addi r11,r0,__NR_clone`
153			`l.sys 1`
154			`l.sfeqi r11,0 /* parent or child? */`
155			`l.bnf 1f /* return if parent */`
156			`l.nop`
157			`l.addi r1,r1,-16 /* make top-level stack frame */`
158			`l.sw 0(r1),r0`
159			`l.jalr r6 /* load arg and call fn */`
160			`l.add r3,r0,r4`
161			`l.add r3,r3,r11`
162			`l.addi r11,r0,__NR_exit /* exit after child exits */`
163			`l.sys 1`
164			`1:`
165			`l.lwz r6,0x0(r1)`
166			`l.lwz r3,0x4(r1)`
167			`l.jr r9`
168			`l.addi r1,r1,8`
169
170			`#if 0`
171
172			`/*`
173			`* Instruction cache enable`
174			`* ic_enable()`
175			`*/`
176			`.global ___ic_enable`
177			`___ic_enable:`
178			`/* Disable IC */`
179			`l.mfspr r13,r0,SPR_SR`
180			`l.addi r11,r0,-1`
181			`l.xori r11,r11,SPR_SR_ICE`
182			`l.and r11,r13,r11`
183			`l.mtspr r0,r11,SPR_SR`
184
185			`/* Invalidate IC */`
186			`l.addi r13,r0,0`
187			`l.addi r11,r0,IC_SIZE`
188			`1:`
189			`l.mtspr r0,r13,SPR_ICBIR`
190			`l.sfne r13,r11`
191			`l.bf 1b`
192			`l.addi r13,r13,IC_LINE`
193
194			`/* Enable IC */`
195			`l.mfspr r13,r0,SPR_SR`
196			`l.ori r13,r13,SPR_SR_ICE`
197			`l.mtspr r0,r13,SPR_SR`
198			`l.nop`
199			`l.nop`
200			`l.nop`
201			`l.nop`
202			`l.nop`
203
204			`l.jr r9`
205			`l.nop`
206
207			`/*`
208			`* Instruction cache disable`
209			`* ic_disable()`
210			`*/`
211			`.global ___ic_disable`
212			`___ic_disable:`
213			`/* Disable IC */`
214			`l.mfspr r13,r0,SPR_SR`
215			`l.addi r11,r0,-1`
216			`l.xori r11,r11,SPR_SR_ICE`
217			`l.and r11,r13,r11`
218			`l.mtspr r0,r11,SPR_SR`
219
220			`l.jr r9`
221			`l.nop`
222
223			`/*`
224			`* Instruction cache invalidate`
225			`* ic_flush()`
226			`*/`
227			`.global ___ic_invalidate`
228			`___ic_invalidate:`
229			`/* Disable IC */`
230			`l.mfspr r13,r0,SPR_SR`
231			`l.addi r11,r0,-1`
232			`l.xori r11,r11,SPR_SR_ICE`
233			`l.and r11,r13,r11`
234			`l.mtspr r0,r11,SPR_SR`
235
236			`/* Invalidate IC */`
237			`l.addi r13,r0,0`
238			`l.addi r11,r0,IC_SIZE`
239			`1:`
240			`l.mtspr r0,r13,SPR_ICBIR`
241			`l.sfne r13,r11`
242			`l.bf 1b`
243			`l.addi r13,r13,IC_LINE`
244
245			`/* Enable IC */`
246			`l.mfspr r13,r0,SPR_SR`
247			`l.ori r13,r13,SPR_SR_ICE`
248			`l.mtspr r0,r13,SPR_SR`
249			`l.nop`
250			`l.nop`
251			`l.nop`
252			`l.nop`
253			`l.nop`
254
255			`l.jr r9`
256			`l.nop`
257
258			`/*`
259			`* Data cache enable`
260			`* dc_enable()`
261			`*/`
262			`.global ___dc_enable`
263			`___dc_enable:`
264			`/* Disable DC */`
265			`l.mfspr r13,r0,SPR_SR`
266			`l.addi r11,r0,-1`
267			`l.xori r11,r11,SPR_SR_DCE`
268			`l.and r11,r13,r11`
269			`l.mtspr r0,r11,SPR_SR`
270
271			`/* Flush DC */`
272			`l.addi r13,r0,0`
273			`l.addi r11,r0,DC_SIZE`
274			`1:`
275			`l.mtspr r0,r13,SPR_DCBIR`
276			`l.sfne r13,r11`
277			`l.bf 1b`
278			`l.addi r13,r13,DC_LINE`
279
280			`/* Enable DC */`
281			`l.mfspr r13,r0,SPR_SR`
282			`l.ori r13,r13,SPR_SR_DCE`
283			`l.mtspr r0,r13,SPR_SR`
284
285			`l.jr r9`
286			`l.nop`
287
288			`/*`
289			`* Data cache disable`
290			`* dc_disable()`
291			`*/`
292			`.global ___dc_disable`
293			`___dc_disable:`
294			`/* Disable DC */`
295			`l.mfspr r13,r0,SPR_SR`
296			`l.addi r11,r0,-1`
297			`l.xori r11,r11,SPR_SR_DCE`
298			`l.and r11,r13,r11`
299			`l.mtspr r0,r11,SPR_SR`
300
301			`l.jr r9`
302			`l.nop`
303
304			`/*`
305			`* Invalidate data cache line`
306			`* dc_line_invalidate(long ph_add)`
307			`*/`
308			`.global ___dc_line_invalidate`
309			`___dc_line_invalidate:`
310			`l.mfspr r4,r0,SPR_SR`
311			`l.addi r5,r0,-1`
312			`l.xori r5,r5,SPR_SR_DCE`
313			`l.and r5,r4,r5`
314			`l.mtspr r0,r5,SPR_SR`
315			`l.mtspr r0,r3,SPR_DCBIR`
316			`l.mtspr r0,r4,SPR_SR`
317			`l.jr r9`
318			`l.nop`
319
320			`/*`
321			`* Data MMU enable`
322			`* dmmu_enable()`
323			`*/`
324			`.global ___dmmu_enable`
325			`___dmmu_enable:`
326			`/* Invalidate all sets */`
327			`l.addi r11,r0,DMMU_SET_NB`
328			`l.addi r13,r0,0`
329			`1:`
330			`l.mtspr r13,r0,SPR_DTLBMR_BASE(0)`
331			`l.addi r11,r11,-1`
332			`l.sfeqi r11,0`
333			`l.bnf 1b`
334			`l.addi r13,r13,1`
335			`l.mfspr r11,r0,SPR_SR`
336			`l.ori r11,r11,SPR_SR_DME`
337			`l.mtspr r0,r11,SPR_SR`
338			`l.jr r9`
339			`l.nop`
340
341			`/*`
342			`* Instruction MMU enable`
343			`* immu_enable()`
344			`*/`
345			`.global ___immu_enable`
346			`___immu_enable:`
347			`/* Invalidate all sets */`
348			`l.addi r11,r0,IMMU_SET_NB`
349			`l.addi r13,r0,0`
350			`1:`
351			`l.mtspr r13,r0,SPR_ITLBMR_BASE(0)`
352			`l.addi r11,r11,-1`
353			`l.sfeqi r11,0`
354			`l.bnf 1b`
355			`l.addi r13,r13,1`
356			`l.mfspr r11,r0,SPR_SR`
357			`l.ori r11,r11,SPR_SR_IME`
358			`l.mtspr r0,r11,SPR_SR`
359			`l.nop`
360			`l.nop`
361			`l.nop`
362			`l.nop`
363			`l.jr r9`
364			`l.nop`
365			`#endif`
366
367			`/*`
368			`* Print utility`
369			`* print(const char *fmt, ...)`
370			`*/`
371			`.global ___print`
372			`___print:`
373			`l.lwz r3,0(r1)`
374			`l.addi r4,r1,4`
375			`# l.sys 202`
376			`l.nop 3`
377			`l.jr r9`
378			`l.nop`
379