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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [or32/] [kernel/] [or32_funcs.S] - Blame information for rev 1318

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Line No. Rev Author Line
1 1317 phoenix
/*
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 *  linux/arch/or32/kernel/or32_funcs.S
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 *
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 *  or32 version
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 *    author(s): Matjaz Breskvar (phoenix@opencores.org)
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 *
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 *  some helper functions for or32 assembler programming
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 *
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 */
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#define ENTRY(symbol)                   \
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        .global symbol                  ;\
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symbol:
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#define CLEAR_GPR(gpr)                  \
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    l.or    gpr,r0,r0
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#define LOAD_SYMBOL_2_GPR(gpr,symbol)   \
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    l.movhi gpr,hi(symbol)              ;\
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    l.ori   gpr,gpr,lo(symbol)
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/*
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 * DSCR: lower bits of SPR_SR defined by mask will be set to 1
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 *
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 * PRMS: t1 is temporary (and destroyed)
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 */
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#define SR_ENABLE_LO_BITS(mask,t1)      \
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    l.mfspr t1,r0,SPR_SR                ;\
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    l.ori   t1,t1,lo(mask)              ;\
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    l.mtspr r0,t1,SPR_SR
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/*
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 * DSCR: bits set in mask will be set to 1
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 *
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 * PRMS: t1 is temporary register
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 *       t2 is temporary register
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 */
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#define SR_ENABLE_BITS(mask,t1,t2)      \
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    l.mfspr t2,r0,SPR_SR                ;\
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    LOAD_SYMBOL_2_GPR(t1,mask)          ;\
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    l.or    t2,t2,t1                    ;\
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    l.mtspr r0,t2,SPR_SR
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/*
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 * DSCR: bits set in mask will be set to 0
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 *
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 * PRMS: t1 is temporary register
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 *       t2 is temporary register
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 */
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#define SR_DISABLE_BITS(mask,t1,t2)     \
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    l.mfspr t2,r0,SPR_SR                ;\
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    LOAD_SYMBOL_2_GPR(t1,(~mask))       ;\
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    l.and   t2,t2,t1                    ;\
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    l.mtspr r0,t2,SPR_SR
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/*
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 * DSCR: lower bits of SPR defined by mask will be set to 1
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 *
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 * PRMS: t1 is temporary (and destroyed)
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 */
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#define SPR_ENABLE_LO_BITS(SPR,mask,t1) \
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    l.mfspr t1,r0,SPR                   ;\
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    l.ori  t1,t1,lo(mask)               ;\
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    l.mtspr r0,t1,SPR
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/*
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 * DSCR: lower bits of SPR defined by mask will be set to 0
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 *
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 * PRMS: t1 is temporary (and destroyed)
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 */
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#define SPR_DISABLE_LO_BITS(SPR,mask,t1) \
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    l.mfspr t1,r0,SPR                   ;\
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    l.andi  t1,t1,lo(~mask)             ;\
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    l.mtspr r0,t1,SPR
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#define DISABLE_INTERRUPTS(t1,t2)       \
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    SR_DISABLE_BITS((SPR_SR_IEE|SPR_SR_TEE),t1,t2)
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#define ENABLE_INTERRUPTS(t1)           \
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    SR_ENABLE_LO_BITS((SPR_SR_IEE|SPR_SR_TEE),t1)

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