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1275 |
phoenix |
/*
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* This file contains the routines for initializing the MMU
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* on the 4xx series of chips.
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* -- paulus
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*
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* Derived from arch/ppc/mm/init.c:
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* Copyright (C) 1995-1996 Gary Thomas (gdt@linuxppc.org)
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*
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* Modifications by Paul Mackerras (PowerMac) (paulus@cs.anu.edu.au)
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* and Cort Dougan (PReP) (cort@cs.nmt.edu)
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* Copyright (C) 1996 Paul Mackerras
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* Amiga/APUS changes by Jesper Skov (jskov@cygnus.co.uk).
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*
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* Derived from "arch/i386/mm/init.c"
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* Copyright (C) 1991, 1992, 1993, 1994 Linus Torvalds
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*
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*/
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#include <linux/config.h>
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#include <linux/signal.h>
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#include <linux/sched.h>
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#include <linux/kernel.h>
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#include <linux/errno.h>
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#include <linux/string.h>
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#include <linux/types.h>
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#include <linux/ptrace.h>
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#include <linux/mman.h>
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#include <linux/mm.h>
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#include <linux/swap.h>
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#include <linux/stddef.h>
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#include <linux/vmalloc.h>
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#include <linux/init.h>
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#include <linux/delay.h>
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#include <linux/bootmem.h>
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#include <linux/highmem.h>
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#include <asm/pgalloc.h>
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#include <asm/prom.h>
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#include <asm/io.h>
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#include <asm/mmu_context.h>
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#include <asm/pgtable.h>
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#include <asm/mmu.h>
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#include <asm/uaccess.h>
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#include <asm/smp.h>
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#include <asm/bootx.h>
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#include <asm/machdep.h>
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#include <asm/setup.h>
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/*
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* MMU_init_hw does the chip-specific initialization of the MMU hardware.
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*/
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void __init MMU_init_hw(void)
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{
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/*
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* The Zone Protection Register (ZPR) defines how protection will
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* be applied to every page which is a member of a given zone. At
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* present, we utilize only two of the 4xx's zones.
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* The zone index bits (of ZSEL) in the PTE are used for software
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* indicators, except the LSB. For user access, zone 1 is used,
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* for kernel access, zone 0 is used. We set all but zone 1
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* to zero, allowing only kernel access as indicated in the PTE.
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* For zone 1, we set a 01 binary (a value of 10 will not work)
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* to allow user access as indicated in the PTE. This also allows
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* kernel access as indicated in the PTE.
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*/
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mtspr(SPRN_ZPR, 0x10000000);
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flush_instruction_cache();
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/*
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* Set up the real-mode cache parameters for the exception vector
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* handlers (which are run in real-mode).
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*/
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mtspr(SPRN_DCWR, 0x00000000); /* All caching is write-back */
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/*
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* Cache instruction and data space where the exception
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* vectors and the kernel live in real-mode.
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*/
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/*
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* Once the following code is enhanced to not assume that it should
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* just enable caching on the first 512MB, we need to make sure that
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* we either are given the cache in a known state or handle correctly
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* the cache being enabled previously. Currently this will clear
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* without flushing. -- Tom
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*/
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mtspr(SPRN_DCCR, 0xF0000000); /* 512 MB of data space at 0x0. */
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mtspr(SPRN_ICCR, 0xF0000000); /* 512 MB of instr. space at 0x0. */
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}
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