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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [sh/] [kernel/] [pci-v320usc.h] - Blame information for rev 1765

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/*
 * v320usc.h: Register defines for the V320USC family of devices.
 *
 * Copyright (C) 1999,2000 Dan Aizenstros (dan@vcubed.com)
 *
 * $Id: pci-v320usc.h,v 1.1.1.1 2004-04-15 01:17:37 phoenix Exp $
 */
 
#ifndef _V320USC_H_
#define _V320USC_H_
 
#include <linux/pci.h>
 
/*
 * General parameters
 */
/* set debug level 4=verbose...1=terse */
#define DEBUG_PCI 3
// #undef DEBUG_PCI
 
#ifdef DEBUG_PCI
#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }
#else
#define PCIDBG(n, x...)
#endif
 
#if 0
/* startup values */
#define PCI_PROBE_BIOS 1
#define PCI_PROBE_CONF1 2
#define PCI_PROBE_CONF2 4
#define PCI_NO_SORT 0x100
#define PCI_BIOS_SORT 0x200
#define PCI_NO_CHECKS 0x400
#define PCI_ASSIGN_ROMS 0x1000
#define PCI_BIOS_IRQ_SCAN 0x2000
#endif
 
 
/*
 *      platform specific parameters
 */
 
/*
 * PCI Command Register
 * - Offset 04h, Size 16 bits
 */
#define PCI_CMD_W_IO_EN                 0x0001          /* I/O access */
#define PCI_CMD_W_MEM_EN                0x0002          /* Memory access */
#define PCI_CMD_W_MASTER_EN             0x0004          /* PCI Master */
#define PCI_CMD_W_MWI_EN                0x0010          /* Memory Write and */
                                                        /* Invalidate enable            */
#define PCI_CMD_W_PAR_EN                0x0040          /* Parity error */
#define PCI_CMD_W_SERR_EN               0x0100          /* System error */
                                                        /* If PAR_EN is enabled then SERR is  */
                                                        /* driven in response to parity error */
#define PCI_CMD_W_FBB_EN                0x0200          /* Fast back to back */
                                                        /* transfers when Bus Master     */
 
/*
 * PCI Status Register
 * - Offset 06h, Size 16 bits
 */
#define PCI_STAT_W_NEW_CAP              0x0010          /* New Capabilites          */
#define PCI_STAT_W_UDF                  0x0040          /* User Defined Feature     */
#define PCI_STAT_W_FAST_BACK            0x0008          /* Fast Back to Back Target */
                                                        /* - Used to indicate ability of this   */
                                                        /* device to other Bus Masters          */
#define PCI_STAT_W_PAR_REP              0x0010          /* Data Parity Report when    */
                                                        /* USC is a Bus Master and PERR is driven */
#define PCI_STAT_W_DEVSEL_MASK          0x0600          /* 10-9 Bits Device Select */
                                                        /* Timing                              */
#define PCI_STAT_W_DEVSEL_SHIFT         9
 
#define PCI_STAT_W_T_ABORT              0x1000          /* Target Abort - set in */
                                                        /* response to a target abort detected */
                                                        /* while USC was a Bus Master          */
#define PCI_STAT_W_M_ABORT              0x2000          /* Master Abort - set in   */
                                                        /* response to a master abort detected */
                                                        /* while USC was a Bus Master          */
#define PCI_STAT_W_SYS_ERR              0x4000          /* System Error - set in */
                                                        /* response to a system error on the */
                                                        /* SERR pin                          */
#define PCI_STAT_W_PAR_ERR              0x8000          /* Parity Error - set in */
                                                        /* response to a parity error on the */
                                                        /* PCI bus                           */
 
/*
 * PCI Class and Revision Register
 * - Offset 08h, Size 32 bits
 */
#define PCI_CC_REV_VREV_MASK            0x0000000f      /* 3-0 Bits Stepping ID  */
                                                        /* Rev A = 0,Rev B0 = 1, Rev B1 = 2, */
                                                        /* Rev B2 = 3 */
#define PCI_CC_REV_VREV_SHIFT           0
 
#define PCI_CC_REV_UREV_MASK            0x000000f0      /* 7-4 Bits User Revision ID */
                                                        /* user definable for system revisions   */
#define PCI_CC_REV_UREV_SHIFT           4
 
#define PCI_CC_REV_PROG_IF_MASK         0x0000ff00      /* 15-8 Bits PCI Programming */
                                                        /* Interface code                        */
#define PCI_CC_REV_PROG_IF_SHIFT        8
 
#define PCI_CC_REV_SUB_CLASS_MASK       0x00ff0000      /* 23-16 Bits PCI Sub Class */
#define PCI_CC_REV_SUB_CLASS_SHIFT      16
 
#define PCI_CC_REV_BASE_CLASS_MASK      0xff000000      /* 32-24 Bits PCI Base Class */
#define PCI_CC_REV_BASE_CLASS_SHIFT     24
 
/*
 * PCI Access to local memory map access
 * - Offset 10h, Size 32 bits (I2O mode)
 */
#define PCI_I2O_BASE_IO                 0x00000001      /* I/O 1 - I/O space */
                                                        /* 0 - Memory Space              */
#define PCI_I2O_BASE_TYPE_MASK          0x00000006      /* 2-1 Bits Address range */
                                                        /* type                               */
#define PCI_I2O_BASE_TYPE_SHIFT         1               /* 0 - device can be mapped */
                                                        /* any where in a 32 bit address space  */
#define PCI_I2O_BASE_PREFETCH           0x00000008      /* Prefetchable - no effect */
#define PCI_I2O_BASE_ADR_BASE_MASK      0xfff00000      /* 31-20 Bits Base address */
                                                        /* of ATU                              */
#define PCI_I2O_BASE_ADR_BASE_SHIFT     20
 
/*
 * PCI Access to local memory map access
 * - Offset 14h, Size 32 bits
 */
#define PCI_MEM_BASE_IO                 0x00000001      /* I/O 1 - I/O space */
                                                        /* 0 - Memory Space              */
#define PCI_MEM_BASE_TYPE_MASK          0x00000006      /* 2-1 Bits Address range */
                                                        /* type                               */
#define PCI_MEM_BASE_TYPE_SHIFT         1               /* 0 - device can be mapped */
                                                        /* any where in a 32 bit address space  */
#define PCI_MEM_BASE_PREFETCH           0x00000008      /* Prefetchable - no effect */
#define PCI_MEM_BASE_ADR_BASE_MASK      0xfff00000      /* 31-20 Bits Base address */
                                                        /* of ATU                              */
#define PCI_MEM_BASE_ADR_BASE_SHIFT     20
 
/*
 * PCI Bus Parameters Register
 * - Offset 3ch, Size 32 bits
 */
#define PCI_BPARAM_INT_LINE_MASK        0x000000ff      /* 7-0 Bits Interrupt Line */
#define PCI_BPARAM_INT_LINE_SHIFT       0
#define PCI_BPARAM_INT_PIN_MASK         0x00000700      /* 10-8 Bits Interrupt Pin */
                                                        /* 0 - disable, 1 - INTA, 2 - INT B    */
                                                        /* 3 - INT C, 4 - INT C                */
#define PCI_BPARAM_INT_PIN_SHIFT        8
#define PCI_BPARAM_MIN_GRANT_MASK       0x00ff0000      /* 23-16 Bits Minimum Grant */
#define PCI_BPARAM_MIN_GRANT_SHIFT      16
#define PCI_BPARAM_MAX_LAT_MASK         0xff000000      /* 31-24 Bits Maximum Latency */
#define PCI_BPARAM_MAX_LAT_SHIFT        24
 
/*
 * LB_PCI_BASEx Registers
 * - Offset 60h, Size 32 bits
 * - Offset 64h, Size 32 bits
 */
#define LB_PCI_BASEX_ALOW_MASK          0x00000003      /* select value AD1:0 */
#define LB_PCI_BASEX_ALOW_SHIFT         0x00000000
#define LB_PCI_BASEX_ERR_EN             0x00000004
#define LB_PCI_BASEX_PREFETCH           0x00000008      /* prefetch */
#define LB_PCI_BASEX_SIZE_DISABLE       0x00000000
#define LB_PCI_BASEX_SIZE_16MB          0x00000010
#define LB_PCI_BASEX_SIZE_32MB          0x00000020
#define LB_PCI_BASEX_SIZE_64MB          0x00000030
#define LB_PCI_BASEX_SIZE_128MB         0x00000040
#define LB_PCI_BASEX_SIZE_256MB         0x00000050
#define LB_PCI_BASEX_SIZE_512MB         0x00000060
#define LB_PCI_BASEX_SIZE_1GB           0x00000070
#define LB_PCI_BASEX_BYTE_SWAP_NO       0x00000000      /* No swap 32 bits */
#define LB_PCI_BASEX_BYTE_SWAP_16       0x00000100      /* 16 bits */
#define LB_PCI_BASEX_BYTE_SWAP_8        0x00000200      /* bits */
#define LB_PCI_BASEX_BYTE_SWAP_AUTO     0x00000300      /* Auto swap use BE[3:0] */
#define LB_PCI_BASEX_COMBINE            0x00000800      /* Burst Write Combine */
 
#define LB_PCI_BASEX_PCI_CMD_MASK       0x0000e000
#define LB_PCI_BASEX_PCI_CMD_SHIFT      13
#define LB_PCI_BASEX_INT_ACK            0x00000000      /* Interrupt Ack */
#define LB_PCI_BASEX_IO                 0x00002000      /* I/O Read/Write */
#define LB_PCI_BASEX_MEMORY             0x00006000      /* Memory Read/Write */
#define LB_PCI_BASEX_CONFIG             0x0000a000      /* Configuration Read/Write */
#define LB_PCI_BASEX_MULTI_MEMORY       0x0000c000      /* Multiple Memory Read/Write */
#define LB_PCI_BASEX_MEMORY_INVALIDATE  0x0000e000      /* Multiple Memory Read/e */
                                                        /* Write Invalidate       */
#define LB_PCI_BASEX_MAP_ADR_MASK       0x00ff0000      /* PCI Address map */
#define LB_PCI_BASEX_MAP_ADR_SHIFT      16
#define LB_PCI_BASEX_BASE               0xff000000      /* Local Address base */
#define LB_PCI_BASEX_BASE_ADR_SHIFT     24
 
 
/*
 * SDRAM Local Base Address Register
 * - Offset 78h, Size 32 bits
 */
#define LB_SDRAM_BASE_ENABLE            0x01            /* must be enabled to access */
#define LB_SDRAM_BASE_SIZE_64M          0x00
#define LB_SDRAM_BASE_SIZE_128M         0x10
#define LB_SDRAM_BASE_SIZE_256M         0x20
#define LB_SDRAM_BASE_SIZE_512M         0x30
#define LB_SDRAM_BASE_SIZE_1G           0x40
 
#define LB_SDRAM_BASE_MASK              0xfc000000
#define LB_SDRAM_BASE_SHIFT             26
 
 
/*
 * Interrupt Configuration Register
 * - Offset e0h, Size 32 bits
 * - Offset e4h, Size 32 bits
 * - Offset e8h, Size 32 bits
 * - Offset 158h, Size 32 bits
 */
#define INT_CFGX_LB_MBI                 0x00000001
#define INT_CFGX_PCI_MBI                0x00000002
#define INT_CFGX_I2O_OP_NE              0x00000008
#define INT_CFGX_I2O_IF_NF              0x00000010
#define INT_CFGX_I2O_IP_NE              0x00000020
#define INT_CFGX_I2O_OP_NF              0x00000040
#define INT_CFGX_I2O_OF_NE              0x00000080
#define INT_CFGX_INT0                   0x00000100
#define INT_CFGX_INT1                   0x00000200
#define INT_CFGX_INT2                   0x00000400
#define INT_CFGX_INT3                   0x00000800
#define INT_CFGX_TIMER0                 0x00001000
#define INT_CFGX_TIMER1                 0x00002000
#define INT_CFGX_ENUM                   0x00004000
#define INT_CFGX_DMA0                   0x00010000
#define INT_CFGX_DMA1                   0x00020000
#define INT_CFGX_PWR_STATE              0x00100000
#define INT_CFGX_HBI                    0x00200000
#define INT_CFGX_WDI                    0x00400000
#define INT_CFGX_BWI                    0x00800000
#define INT_CFGX_PSLAVE_PI              0x01000000
#define INT_CFGX_PMASTER_PI             0x02000000
#define INT_CFGX_PCI_T_ABORT            0x04000000
#define INT_CFGX_PCI_M_ABORT            0x08000000
#define INT_CFGX_DRA_PI                 0x10000000
#define INT_CFGX_MODE                   0x20000000
#define INT_CFGX_DI0                    0x40000000
#define INT_CFGX_DI1                    0x80000000
 
 
/*
 * Interrupt Status Register
 * - Offset ECh, Size 32 bits
 */
#define INT_STAT_BWI                    0x00800000
#define INT_STAT_WDI                    0x00400000
#define INT_STAT_HBI                    0x00200000
#define INT_STAT_DMA1                   0x00020000
#define INT_STAT_DMA0                   0x00010000
#define INT_STAT_TIMER1                 0x00002000
#define INT_STAT_TIMER0                 0x00001000
#define INT_STAT_INT3                   0x00000800
#define INT_STAT_INT2                   0x00000400
#define INT_STAT_INT1                   0x00000200
#define INT_STAT_INT0                   0x00000100
 
 
/*
 * General Purpose Timer Control Register
 * - Offset 150h, Size 16 bits
 * - Offset 152h, Size 16 bits
 */
#define TIMER_CTLX_W_TI_MODE_0          0x0000          /* Timer input event */
#define TIMER_CTLX_W_TI_MODE_1          0x0001
#define TIMER_CTLX_W_TI_MODE_2          0x0002
#define TIMER_CTLX_W_TI_MODE_3          0x0003
 
#define TIMER_CTLX_W_CNT_EN_0           0x0000          /* Count enable */
#define TIMER_CTLX_W_CNT_EN_1           0x0004
#define TIMER_CTLX_W_CNT_EN_2           0x0008
#define TIMER_CTLX_W_CNT_EN_3           0x000C
 
#define TIMER_CTLX_W_TRG_MODE_0         0x0000          /* Trigger mode */
#define TIMER_CTLX_W_TRG_MODE_1         0x0010
#define TIMER_CTLX_W_TRG_MODE_2         0x0020
#define TIMER_CTLX_W_TRG_MODE_3         0x0030
 
#define TIMER_CTLX_W_TO_MODE_0          0x0000          /* Timer output mode */
#define TIMER_CTLX_W_TO_MODE_1          0x0100
#define TIMER_CTLX_W_TO_MODE_2          0x0200
#define TIMER_CTLX_W_TO_MODE_3          0x0300
#define TIMER_CTLX_W_TO_MODE_4          0x0400
#define TIMER_CTLX_W_TO_MODE_5          0x0500
 
#define TIMER_CTLX_W_DLTCH_0            0x0000          /* Data latch mode */
#define TIMER_CTLX_W_DLTCH_1            0x0800
#define TIMER_CTLX_W_DLTCH_2            0x1000
 
#define TIMER_CTLX_W_ENABLE             0x8000          /* Timer enable */
 
 
/*
 * DMA Delay Register
 * - Offset 16Ch, Size 8 bits
 */
#define DMA_DELAY_MASK                  0x000000ff
#define DMA_DELAY_SHIFT                 0
 
/*
 * DMA Command / Status Register
 * - Offset 170h, Size 32 bits
 * - Offset 174h, Size 32 bits
 */
#define DMA_CSR_IPR                     0x00000001      /* initiate DMA transfer */
#define DMA_CSR_HALT                    0x00000002      /* pause DMA transfer */
#define DMA_CSR_DONE                    0x00000004      /* DMA transfer complete */
#define DMA_CSR_DCI                     0x00000008      /* DMA control interrupt status */
#define DMA_CSR_DPE                     0x00000010      /* DMA PCI BUS error status */
#define DMA_CSR_DONE_EN                 0x00000400      /* DONE interrupt enable */
#define DMA_CSR_DCI_EN                  0x00000800      /* DCI interrupt enable */
#define DMA_CSR_DPE_EN                  0x00001000      /* DPE interrupt enable */
#define DMA_CSR_PRIORITY                0x00008000      /* DMA channel priority */
#define DMA_CSR_PCI_CMD0_MASK           0x000E0000      /* PCI Command Type 0 */
#define DMA_CSR_PCI_CMD0_SHIFT          17
#define DMA_CSR_PCI_CMD1_MASK           0x00E00000      /* PCI Command Type 1 */
#define DMA_CSR_PCI_CMD1_SHIFT          21
 
/*
 * DMA Transfer Control Register
 * - Offset 180h, Size 32 bits
 * - Offset 190h, Size 32 bits
 */
#define DMA_XFER_DMA_CNT_MASK           0x000FFFFF      /* DMA transfer count */
#define DMA_XFER_DMA_CNT_SHIFT          0
#define DMA_XFER_DTERM_EN               0x00400000      /* External terminate count enable */
#define DMA_XFER_BLOCK_FILL             0x00800000      /* Block fill feature enable */
#define DMA_XFER_DST_BUS                0x01000000      /* DMA destination BUS */
#define DMA_XFER_SRC_BUS                0x02000000      /* DMA source BUS */
#define DMA_XFER_PDST_TYPE              0x04000000      /* PCI destination command type */
#define DMA_XFER_PSRC_TYPE              0x08000000      /* PCI source command type */
#define DMA_XFER_SWAP_MASK              0x30000000      /* Byte swap control */
#define DMA_XFER_SWAP_SHIFT             28
#define DMA_XFER_UPDT_CNT               0x40000000      /* Update count */
#define DMA_XFER_DREQ_EN                0x80000000      /* External DRQ enable */
 
 
/*
 * DMA Control Block Register
 * - Offset 180h, Size 32 bits
 * - Offset 190h, Size 32 bits
 */
#define DMA_CTLB_BUS                    0x00000001      /* DMA Control block address space */
#define DMA_CTLB_SA_INC_DIS             0x00000004      /* Source address increment disable */
#define DMA_CTLB_DA_INC_DIS             0x00000008      /* Dest address increment disable */
#define DMA_CTLB_ADDR_MASK              0xFFFFFFF0      /* DMA Control block address mask */
#define DMA_CTLB_ADDR_SHIFT             4
 
 
/*
 * V320USC registers offsets
 */
#define V320USC_PCI_VENDOR              0x00
#define V320USC_PCI_DEVICE              0x02
#define V320USC_PCI_CMD_W               0x04
#define V320USC_PCI_STAT_W              0x06
#define V320USC_PCI_CC_REV              0x08
#define V320USC_PCI_HDR_CFG             0x0c
#define V320USC_PCI_I2O_BASE    0x10
#define V320USC_PCI_MEM_BASE    0x14
#define V320USC_PCI_REG_BASE    0x18
#define V320USC_PCI_PCU_BASE    0x1c
#define V320USC_PCI_BPARM               0x3c
#define V320USC_PCI_I2O_MAP             0x50
#define V320USC_PCI_MEM_MAP             0x54
#define V320USC_PCI_BUS_CFG             0x5c
#define V320USC_LB_PCI_BASE0    0x60
#define V320USC_LB_PCI_BASE1    0x64
#define V320USC_LB_PCU_BASE             0x6c
#define V320USC_SYSTEM                  0x73
#define V320USC_LB_SDRAM_BASE   0x78
#define V320USC_LB_BUS_CFG              0x7c
#define V320USC_LB_PCI_CTL_W    0x84
#define V320USC_DRAM_CFG        0x8C
#define V320USC_DRAM_BLK0       0x90
#define V320USC_DRAM_BLK1       0x94
#define V320USC_DRAM_BLK2       0x98
#define V320USC_DRAM_BLK3       0x9c
#define V320USC_INT_CFG0                0xe0
#define V320USC_INT_CFG1                0xe4
#define V320USC_INT_CFG2                0xe8
#define V320USC_INT_STAT                0xec
#define V320USC_WD_HBI_W                0xf4
#define V320USC_TIMER_DATA0             0x140
#define V320USC_TIMER_DATA1             0x144
#define V320USC_TIMER_CTL0_W            0x150
#define V320USC_TIMER_CTL1_W            0x152
#define V320USC_INT_CFG3                0x158
#define V320USC_DMA_DELAY               0x16C
#define V320USC_DMA_CSR0                0x170
#define V320USC_DMA_CSR1                0x174
#define V320USC_DMA_XFER_CTL0           0x180
#define V320USC_DMA_SRC_ADR0            0x184
#define V320USC_DMA_DST_ADR0            0x188
#define V320USC_DMA_CTLB_ADR0           0x18C
#define V320USC_DMA_XFER_CTL1           0x190
#define V320USC_DMA_SRC_ADR1            0x194
#define V320USC_DMA_DST_ADR1            0x198
#define V320USC_DMA_CTLB_ADR1           0x19C
 
/*
 * Vendor/Device ID settings
 */
 
#define V3USC_PCI_VENDOR                0x11b0
#define V3USC_PCI_DEVICE_MIPS_9 0x0100
#define V3USC_PCI_DEVICE_MIPS_5 0x0101
#define V3USC_PCI_DEVICE_SH3    0x0102
#define V3USC_PCI_DEVICE_SH4    0x0103
 
/*
 * Stepping of V3USC320 as read back from V3USC_PCI_CC_REV register
 */
#define V3USC_REV_A0 0
#define V3USC_REV_B0 1
#define V3USC_REV_B1 2
 
/*
 * PCI Bus Parameters Register
 * - Offset 3ch, Size 32 bits
 */
#define INTERRUPT_PIN_DISABLE           0x0             /* Disabled */
#define INTERRUPT_PIN_INTA              0x1             /* Use INTA */
#define INTERRUPT_PIN_INTB              0x2             /* Use INTB */
#define INTERRUPT_PIN_INTC              0x3             /* Use INTC */
#define INTERRUPT_PIN_INTD              0x4             /* Use INTD */
 
/*
 * PCI Base Address for Peripheral Access
 * - Offset 1ch, Size 32 bits
 * PCI Intelligent I/O Address Translation Unit Local Bus Address Map Register
 * - Offset ??h, Size 32 bits
 */
#define BYTE_SWAP_NO                    0x0             /* No swap 32 bits */
#define BYTE_SWAP_16                    0x1             /* 16 bits */
#define BYTE_SWAP_8                     0x2             /* 8 bits */
#define BYTE_SWAP_AUTO                  0x3             /* Auto swap use BE[3:0]   */
#define APERTURE_SIZE_1M                0x0             /* Aperture size of 1 MB   */
#define APERTURE_SIZE_2M                0x1             /* Aperture size of 2 MB   */
#define APERTURE_SIZE_4M                0x2             /* Aperture size of 4 MB   */
#define APERTURE_SIZE_8M                0x3             /* Aperture size of 8 MB   */
#define APERTURE_SIZE_16M               0x4             /* Aperture size of 16 MB  */
#define APERTURE_SIZE_32M               0x5             /* Aperture size of 32 MB  */
#define APERTURE_SIZE_64M               0x6             /* Aperture size of 64 MB  */
#define APERTURE_SIZE_128M              0x7             /* Aperture size of 128 MB */
#define APERTURE_SIZE_256M              0x8             /* Aperture size of 256 MB */
#define APERTURE_SIZE_512M              0x9             /* Aperture size of 512 MB */
#define APERTURE_SIZE_1G                0xa             /* Aperture size of 1 GB   */
 
#endif /* _V320USC_H_ */

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [sh/] [kernel/] [pci-v320usc.h] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	1275	phoenix	`/*`
2			`* v320usc.h: Register defines for the V320USC family of devices.`
3			`*`
4			`* Copyright (C) 1999,2000 Dan Aizenstros (dan@vcubed.com)`
5			`*`
6			`* $Id: pci-v320usc.h,v 1.1.1.1 2004-04-15 01:17:37 phoenix Exp $`
7			`*/`
8
9			`#ifndef _V320USC_H_`
10			`#define _V320USC_H_`
11
12			`#include <linux/pci.h>`
13
14			`/*`
15			`* General parameters`
16			`*/`
17			`/* set debug level 4=verbose...1=terse */`
18			`#define DEBUG_PCI 3`
19			`// #undef DEBUG_PCI`
20
21			`#ifdef DEBUG_PCI`
22			`#define PCIDBG(n, x...) { if(DEBUG_PCI>=n) printk(x); }`
23			`#else`
24			`#define PCIDBG(n, x...)`
25			`#endif`
26
27			`#if 0`
28			`/* startup values */`
29			`#define PCI_PROBE_BIOS 1`
30			`#define PCI_PROBE_CONF1 2`
31			`#define PCI_PROBE_CONF2 4`
32			`#define PCI_NO_SORT 0x100`
33			`#define PCI_BIOS_SORT 0x200`
34			`#define PCI_NO_CHECKS 0x400`
35			`#define PCI_ASSIGN_ROMS 0x1000`
36			`#define PCI_BIOS_IRQ_SCAN 0x2000`
37			`#endif`
38
39
40			`/*`
41			`* platform specific parameters`
42			`*/`
43
44			`/*`
45			`* PCI Command Register`
46			`* - Offset 04h, Size 16 bits`
47			`*/`
48			`#define PCI_CMD_W_IO_EN 0x0001 /* I/O access */`
49			`#define PCI_CMD_W_MEM_EN 0x0002 /* Memory access */`
50			`#define PCI_CMD_W_MASTER_EN 0x0004 /* PCI Master */`
51			`#define PCI_CMD_W_MWI_EN 0x0010 /* Memory Write and */`
52			`/* Invalidate enable */`
53			`#define PCI_CMD_W_PAR_EN 0x0040 /* Parity error */`
54			`#define PCI_CMD_W_SERR_EN 0x0100 /* System error */`
55			`/* If PAR_EN is enabled then SERR is */`
56			`/* driven in response to parity error */`
57			`#define PCI_CMD_W_FBB_EN 0x0200 /* Fast back to back */`
58			`/* transfers when Bus Master */`
59
60			`/*`
61			`* PCI Status Register`
62			`* - Offset 06h, Size 16 bits`
63			`*/`
64			`#define PCI_STAT_W_NEW_CAP 0x0010 /* New Capabilites */`
65			`#define PCI_STAT_W_UDF 0x0040 /* User Defined Feature */`
66			`#define PCI_STAT_W_FAST_BACK 0x0008 /* Fast Back to Back Target */`
67			`/* - Used to indicate ability of this */`
68			`/* device to other Bus Masters */`
69			`#define PCI_STAT_W_PAR_REP 0x0010 /* Data Parity Report when */`
70			`/* USC is a Bus Master and PERR is driven */`
71			`#define PCI_STAT_W_DEVSEL_MASK 0x0600 /* 10-9 Bits Device Select */`
72			`/* Timing */`
73			`#define PCI_STAT_W_DEVSEL_SHIFT 9`
74
75			`#define PCI_STAT_W_T_ABORT 0x1000 /* Target Abort - set in */`
76			`/* response to a target abort detected */`
77			`/* while USC was a Bus Master */`
78			`#define PCI_STAT_W_M_ABORT 0x2000 /* Master Abort - set in */`
79			`/* response to a master abort detected */`
80			`/* while USC was a Bus Master */`
81			`#define PCI_STAT_W_SYS_ERR 0x4000 /* System Error - set in */`
82			`/* response to a system error on the */`
83			`/* SERR pin */`
84			`#define PCI_STAT_W_PAR_ERR 0x8000 /* Parity Error - set in */`
85			`/* response to a parity error on the */`
86			`/* PCI bus */`
87
88			`/*`
89			`* PCI Class and Revision Register`
90			`* - Offset 08h, Size 32 bits`
91			`*/`
92			`#define PCI_CC_REV_VREV_MASK 0x0000000f /* 3-0 Bits Stepping ID */`
93			`/* Rev A = 0,Rev B0 = 1, Rev B1 = 2, */`
94			`/* Rev B2 = 3 */`
95			`#define PCI_CC_REV_VREV_SHIFT 0`
96
97			`#define PCI_CC_REV_UREV_MASK 0x000000f0 /* 7-4 Bits User Revision ID */`
98			`/* user definable for system revisions */`
99			`#define PCI_CC_REV_UREV_SHIFT 4`
100
101			`#define PCI_CC_REV_PROG_IF_MASK 0x0000ff00 /* 15-8 Bits PCI Programming */`
102			`/* Interface code */`
103			`#define PCI_CC_REV_PROG_IF_SHIFT 8`
104
105			`#define PCI_CC_REV_SUB_CLASS_MASK 0x00ff0000 /* 23-16 Bits PCI Sub Class */`
106			`#define PCI_CC_REV_SUB_CLASS_SHIFT 16`
107
108			`#define PCI_CC_REV_BASE_CLASS_MASK 0xff000000 /* 32-24 Bits PCI Base Class */`
109			`#define PCI_CC_REV_BASE_CLASS_SHIFT 24`
110
111			`/*`
112			`* PCI Access to local memory map access`
113			`* - Offset 10h, Size 32 bits (I2O mode)`
114			`*/`
115			`#define PCI_I2O_BASE_IO 0x00000001 /* I/O 1 - I/O space */`
116			`/* 0 - Memory Space */`
117			`#define PCI_I2O_BASE_TYPE_MASK 0x00000006 /* 2-1 Bits Address range */`
118			`/* type */`
119			`#define PCI_I2O_BASE_TYPE_SHIFT 1 /* 0 - device can be mapped */`
120			`/* any where in a 32 bit address space */`
121			`#define PCI_I2O_BASE_PREFETCH 0x00000008 /* Prefetchable - no effect */`
122			`#define PCI_I2O_BASE_ADR_BASE_MASK 0xfff00000 /* 31-20 Bits Base address */`
123			`/* of ATU */`
124			`#define PCI_I2O_BASE_ADR_BASE_SHIFT 20`
125
126			`/*`
127			`* PCI Access to local memory map access`
128			`* - Offset 14h, Size 32 bits`
129			`*/`
130			`#define PCI_MEM_BASE_IO 0x00000001 /* I/O 1 - I/O space */`
131			`/* 0 - Memory Space */`
132			`#define PCI_MEM_BASE_TYPE_MASK 0x00000006 /* 2-1 Bits Address range */`
133			`/* type */`
134			`#define PCI_MEM_BASE_TYPE_SHIFT 1 /* 0 - device can be mapped */`
135			`/* any where in a 32 bit address space */`
136			`#define PCI_MEM_BASE_PREFETCH 0x00000008 /* Prefetchable - no effect */`
137			`#define PCI_MEM_BASE_ADR_BASE_MASK 0xfff00000 /* 31-20 Bits Base address */`
138			`/* of ATU */`
139			`#define PCI_MEM_BASE_ADR_BASE_SHIFT 20`
140
141			`/*`
142			`* PCI Bus Parameters Register`
143			`* - Offset 3ch, Size 32 bits`
144			`*/`
145			`#define PCI_BPARAM_INT_LINE_MASK 0x000000ff /* 7-0 Bits Interrupt Line */`
146			`#define PCI_BPARAM_INT_LINE_SHIFT 0`
147			`#define PCI_BPARAM_INT_PIN_MASK 0x00000700 /* 10-8 Bits Interrupt Pin */`
148			`/* 0 - disable, 1 - INTA, 2 - INT B */`
149			`/* 3 - INT C, 4 - INT C */`
150			`#define PCI_BPARAM_INT_PIN_SHIFT 8`
151			`#define PCI_BPARAM_MIN_GRANT_MASK 0x00ff0000 /* 23-16 Bits Minimum Grant */`
152			`#define PCI_BPARAM_MIN_GRANT_SHIFT 16`
153			`#define PCI_BPARAM_MAX_LAT_MASK 0xff000000 /* 31-24 Bits Maximum Latency */`
154			`#define PCI_BPARAM_MAX_LAT_SHIFT 24`
155
156			`/*`
157			`* LB_PCI_BASEx Registers`
158			`* - Offset 60h, Size 32 bits`
159			`* - Offset 64h, Size 32 bits`
160			`*/`
161			`#define LB_PCI_BASEX_ALOW_MASK 0x00000003 /* select value AD1:0 */`
162			`#define LB_PCI_BASEX_ALOW_SHIFT 0x00000000`
163			`#define LB_PCI_BASEX_ERR_EN 0x00000004`
164			`#define LB_PCI_BASEX_PREFETCH 0x00000008 /* prefetch */`
165			`#define LB_PCI_BASEX_SIZE_DISABLE 0x00000000`
166			`#define LB_PCI_BASEX_SIZE_16MB 0x00000010`
167			`#define LB_PCI_BASEX_SIZE_32MB 0x00000020`
168			`#define LB_PCI_BASEX_SIZE_64MB 0x00000030`
169			`#define LB_PCI_BASEX_SIZE_128MB 0x00000040`
170			`#define LB_PCI_BASEX_SIZE_256MB 0x00000050`
171			`#define LB_PCI_BASEX_SIZE_512MB 0x00000060`
172			`#define LB_PCI_BASEX_SIZE_1GB 0x00000070`
173			`#define LB_PCI_BASEX_BYTE_SWAP_NO 0x00000000 /* No swap 32 bits */`
174			`#define LB_PCI_BASEX_BYTE_SWAP_16 0x00000100 /* 16 bits */`
175			`#define LB_PCI_BASEX_BYTE_SWAP_8 0x00000200 /* bits */`
176			`#define LB_PCI_BASEX_BYTE_SWAP_AUTO 0x00000300 /* Auto swap use BE[3:0] */`
177			`#define LB_PCI_BASEX_COMBINE 0x00000800 /* Burst Write Combine */`
178
179			`#define LB_PCI_BASEX_PCI_CMD_MASK 0x0000e000`
180			`#define LB_PCI_BASEX_PCI_CMD_SHIFT 13`
181			`#define LB_PCI_BASEX_INT_ACK 0x00000000 /* Interrupt Ack */`
182			`#define LB_PCI_BASEX_IO 0x00002000 /* I/O Read/Write */`
183			`#define LB_PCI_BASEX_MEMORY 0x00006000 /* Memory Read/Write */`
184			`#define LB_PCI_BASEX_CONFIG 0x0000a000 /* Configuration Read/Write */`
185			`#define LB_PCI_BASEX_MULTI_MEMORY 0x0000c000 /* Multiple Memory Read/Write */`
186			`#define LB_PCI_BASEX_MEMORY_INVALIDATE 0x0000e000 /* Multiple Memory Read/e */`
187			`/* Write Invalidate */`
188			`#define LB_PCI_BASEX_MAP_ADR_MASK 0x00ff0000 /* PCI Address map */`
189			`#define LB_PCI_BASEX_MAP_ADR_SHIFT 16`
190			`#define LB_PCI_BASEX_BASE 0xff000000 /* Local Address base */`
191			`#define LB_PCI_BASEX_BASE_ADR_SHIFT 24`
192
193
194			`/*`
195			`* SDRAM Local Base Address Register`
196			`* - Offset 78h, Size 32 bits`
197			`*/`
198			`#define LB_SDRAM_BASE_ENABLE 0x01 /* must be enabled to access */`
199			`#define LB_SDRAM_BASE_SIZE_64M 0x00`
200			`#define LB_SDRAM_BASE_SIZE_128M 0x10`
201			`#define LB_SDRAM_BASE_SIZE_256M 0x20`
202			`#define LB_SDRAM_BASE_SIZE_512M 0x30`
203			`#define LB_SDRAM_BASE_SIZE_1G 0x40`
204
205			`#define LB_SDRAM_BASE_MASK 0xfc000000`
206			`#define LB_SDRAM_BASE_SHIFT 26`
207
208
209			`/*`
210			`* Interrupt Configuration Register`
211			`* - Offset e0h, Size 32 bits`
212			`* - Offset e4h, Size 32 bits`
213			`* - Offset e8h, Size 32 bits`
214			`* - Offset 158h, Size 32 bits`
215			`*/`
216			`#define INT_CFGX_LB_MBI 0x00000001`
217			`#define INT_CFGX_PCI_MBI 0x00000002`
218			`#define INT_CFGX_I2O_OP_NE 0x00000008`
219			`#define INT_CFGX_I2O_IF_NF 0x00000010`
220			`#define INT_CFGX_I2O_IP_NE 0x00000020`
221			`#define INT_CFGX_I2O_OP_NF 0x00000040`
222			`#define INT_CFGX_I2O_OF_NE 0x00000080`
223			`#define INT_CFGX_INT0 0x00000100`
224			`#define INT_CFGX_INT1 0x00000200`
225			`#define INT_CFGX_INT2 0x00000400`
226			`#define INT_CFGX_INT3 0x00000800`
227			`#define INT_CFGX_TIMER0 0x00001000`
228			`#define INT_CFGX_TIMER1 0x00002000`
229			`#define INT_CFGX_ENUM 0x00004000`
230			`#define INT_CFGX_DMA0 0x00010000`
231			`#define INT_CFGX_DMA1 0x00020000`
232			`#define INT_CFGX_PWR_STATE 0x00100000`
233			`#define INT_CFGX_HBI 0x00200000`
234			`#define INT_CFGX_WDI 0x00400000`
235			`#define INT_CFGX_BWI 0x00800000`
236			`#define INT_CFGX_PSLAVE_PI 0x01000000`
237			`#define INT_CFGX_PMASTER_PI 0x02000000`
238			`#define INT_CFGX_PCI_T_ABORT 0x04000000`
239			`#define INT_CFGX_PCI_M_ABORT 0x08000000`
240			`#define INT_CFGX_DRA_PI 0x10000000`
241			`#define INT_CFGX_MODE 0x20000000`
242			`#define INT_CFGX_DI0 0x40000000`
243			`#define INT_CFGX_DI1 0x80000000`
244
245
246			`/*`
247			`* Interrupt Status Register`
248			`* - Offset ECh, Size 32 bits`
249			`*/`
250			`#define INT_STAT_BWI 0x00800000`
251			`#define INT_STAT_WDI 0x00400000`
252			`#define INT_STAT_HBI 0x00200000`
253			`#define INT_STAT_DMA1 0x00020000`
254			`#define INT_STAT_DMA0 0x00010000`
255			`#define INT_STAT_TIMER1 0x00002000`
256			`#define INT_STAT_TIMER0 0x00001000`
257			`#define INT_STAT_INT3 0x00000800`
258			`#define INT_STAT_INT2 0x00000400`
259			`#define INT_STAT_INT1 0x00000200`
260			`#define INT_STAT_INT0 0x00000100`
261
262
263			`/*`
264			`* General Purpose Timer Control Register`
265			`* - Offset 150h, Size 16 bits`
266			`* - Offset 152h, Size 16 bits`
267			`*/`
268			`#define TIMER_CTLX_W_TI_MODE_0 0x0000 /* Timer input event */`
269			`#define TIMER_CTLX_W_TI_MODE_1 0x0001`
270			`#define TIMER_CTLX_W_TI_MODE_2 0x0002`
271			`#define TIMER_CTLX_W_TI_MODE_3 0x0003`
272
273			`#define TIMER_CTLX_W_CNT_EN_0 0x0000 /* Count enable */`
274			`#define TIMER_CTLX_W_CNT_EN_1 0x0004`
275			`#define TIMER_CTLX_W_CNT_EN_2 0x0008`
276			`#define TIMER_CTLX_W_CNT_EN_3 0x000C`
277
278			`#define TIMER_CTLX_W_TRG_MODE_0 0x0000 /* Trigger mode */`
279			`#define TIMER_CTLX_W_TRG_MODE_1 0x0010`
280			`#define TIMER_CTLX_W_TRG_MODE_2 0x0020`
281			`#define TIMER_CTLX_W_TRG_MODE_3 0x0030`
282
283			`#define TIMER_CTLX_W_TO_MODE_0 0x0000 /* Timer output mode */`
284			`#define TIMER_CTLX_W_TO_MODE_1 0x0100`
285			`#define TIMER_CTLX_W_TO_MODE_2 0x0200`
286			`#define TIMER_CTLX_W_TO_MODE_3 0x0300`
287			`#define TIMER_CTLX_W_TO_MODE_4 0x0400`
288			`#define TIMER_CTLX_W_TO_MODE_5 0x0500`
289
290			`#define TIMER_CTLX_W_DLTCH_0 0x0000 /* Data latch mode */`
291			`#define TIMER_CTLX_W_DLTCH_1 0x0800`
292			`#define TIMER_CTLX_W_DLTCH_2 0x1000`
293
294			`#define TIMER_CTLX_W_ENABLE 0x8000 /* Timer enable */`
295
296
297			`/*`
298			`* DMA Delay Register`
299			`* - Offset 16Ch, Size 8 bits`
300			`*/`
301			`#define DMA_DELAY_MASK 0x000000ff`
302			`#define DMA_DELAY_SHIFT 0`
303
304			`/*`
305			`* DMA Command / Status Register`
306			`* - Offset 170h, Size 32 bits`
307			`* - Offset 174h, Size 32 bits`
308			`*/`
309			`#define DMA_CSR_IPR 0x00000001 /* initiate DMA transfer */`
310			`#define DMA_CSR_HALT 0x00000002 /* pause DMA transfer */`
311			`#define DMA_CSR_DONE 0x00000004 /* DMA transfer complete */`
312			`#define DMA_CSR_DCI 0x00000008 /* DMA control interrupt status */`
313			`#define DMA_CSR_DPE 0x00000010 /* DMA PCI BUS error status */`
314			`#define DMA_CSR_DONE_EN 0x00000400 /* DONE interrupt enable */`
315			`#define DMA_CSR_DCI_EN 0x00000800 /* DCI interrupt enable */`
316			`#define DMA_CSR_DPE_EN 0x00001000 /* DPE interrupt enable */`
317			`#define DMA_CSR_PRIORITY 0x00008000 /* DMA channel priority */`
318			`#define DMA_CSR_PCI_CMD0_MASK 0x000E0000 /* PCI Command Type 0 */`
319			`#define DMA_CSR_PCI_CMD0_SHIFT 17`
320			`#define DMA_CSR_PCI_CMD1_MASK 0x00E00000 /* PCI Command Type 1 */`
321			`#define DMA_CSR_PCI_CMD1_SHIFT 21`
322
323			`/*`
324			`* DMA Transfer Control Register`
325			`* - Offset 180h, Size 32 bits`
326			`* - Offset 190h, Size 32 bits`
327			`*/`
328			`#define DMA_XFER_DMA_CNT_MASK 0x000FFFFF /* DMA transfer count */`
329			`#define DMA_XFER_DMA_CNT_SHIFT 0`
330			`#define DMA_XFER_DTERM_EN 0x00400000 /* External terminate count enable */`
331			`#define DMA_XFER_BLOCK_FILL 0x00800000 /* Block fill feature enable */`
332			`#define DMA_XFER_DST_BUS 0x01000000 /* DMA destination BUS */`
333			`#define DMA_XFER_SRC_BUS 0x02000000 /* DMA source BUS */`
334			`#define DMA_XFER_PDST_TYPE 0x04000000 /* PCI destination command type */`
335			`#define DMA_XFER_PSRC_TYPE 0x08000000 /* PCI source command type */`
336			`#define DMA_XFER_SWAP_MASK 0x30000000 /* Byte swap control */`
337			`#define DMA_XFER_SWAP_SHIFT 28`
338			`#define DMA_XFER_UPDT_CNT 0x40000000 /* Update count */`
339			`#define DMA_XFER_DREQ_EN 0x80000000 /* External DRQ enable */`
340
341
342			`/*`
343			`* DMA Control Block Register`
344			`* - Offset 180h, Size 32 bits`
345			`* - Offset 190h, Size 32 bits`
346			`*/`
347			`#define DMA_CTLB_BUS 0x00000001 /* DMA Control block address space */`
348			`#define DMA_CTLB_SA_INC_DIS 0x00000004 /* Source address increment disable */`
349			`#define DMA_CTLB_DA_INC_DIS 0x00000008 /* Dest address increment disable */`
350			`#define DMA_CTLB_ADDR_MASK 0xFFFFFFF0 /* DMA Control block address mask */`
351			`#define DMA_CTLB_ADDR_SHIFT 4`
352
353
354			`/*`
355			`* V320USC registers offsets`
356			`*/`
357			`#define V320USC_PCI_VENDOR 0x00`
358			`#define V320USC_PCI_DEVICE 0x02`
359			`#define V320USC_PCI_CMD_W 0x04`
360			`#define V320USC_PCI_STAT_W 0x06`
361			`#define V320USC_PCI_CC_REV 0x08`
362			`#define V320USC_PCI_HDR_CFG 0x0c`
363			`#define V320USC_PCI_I2O_BASE 0x10`
364			`#define V320USC_PCI_MEM_BASE 0x14`
365			`#define V320USC_PCI_REG_BASE 0x18`
366			`#define V320USC_PCI_PCU_BASE 0x1c`
367			`#define V320USC_PCI_BPARM 0x3c`
368			`#define V320USC_PCI_I2O_MAP 0x50`
369			`#define V320USC_PCI_MEM_MAP 0x54`
370			`#define V320USC_PCI_BUS_CFG 0x5c`
371			`#define V320USC_LB_PCI_BASE0 0x60`
372			`#define V320USC_LB_PCI_BASE1 0x64`
373			`#define V320USC_LB_PCU_BASE 0x6c`
374			`#define V320USC_SYSTEM 0x73`
375			`#define V320USC_LB_SDRAM_BASE 0x78`
376			`#define V320USC_LB_BUS_CFG 0x7c`
377			`#define V320USC_LB_PCI_CTL_W 0x84`
378			`#define V320USC_DRAM_CFG 0x8C`
379			`#define V320USC_DRAM_BLK0 0x90`
380			`#define V320USC_DRAM_BLK1 0x94`
381			`#define V320USC_DRAM_BLK2 0x98`
382			`#define V320USC_DRAM_BLK3 0x9c`
383			`#define V320USC_INT_CFG0 0xe0`
384			`#define V320USC_INT_CFG1 0xe4`
385			`#define V320USC_INT_CFG2 0xe8`
386			`#define V320USC_INT_STAT 0xec`
387			`#define V320USC_WD_HBI_W 0xf4`
388			`#define V320USC_TIMER_DATA0 0x140`
389			`#define V320USC_TIMER_DATA1 0x144`
390			`#define V320USC_TIMER_CTL0_W 0x150`
391			`#define V320USC_TIMER_CTL1_W 0x152`
392			`#define V320USC_INT_CFG3 0x158`
393			`#define V320USC_DMA_DELAY 0x16C`
394			`#define V320USC_DMA_CSR0 0x170`
395			`#define V320USC_DMA_CSR1 0x174`
396			`#define V320USC_DMA_XFER_CTL0 0x180`
397			`#define V320USC_DMA_SRC_ADR0 0x184`
398			`#define V320USC_DMA_DST_ADR0 0x188`
399			`#define V320USC_DMA_CTLB_ADR0 0x18C`
400			`#define V320USC_DMA_XFER_CTL1 0x190`
401			`#define V320USC_DMA_SRC_ADR1 0x194`
402			`#define V320USC_DMA_DST_ADR1 0x198`
403			`#define V320USC_DMA_CTLB_ADR1 0x19C`
404
405			`/*`
406			`* Vendor/Device ID settings`
407			`*/`
408
409			`#define V3USC_PCI_VENDOR 0x11b0`
410			`#define V3USC_PCI_DEVICE_MIPS_9 0x0100`
411			`#define V3USC_PCI_DEVICE_MIPS_5 0x0101`
412			`#define V3USC_PCI_DEVICE_SH3 0x0102`
413			`#define V3USC_PCI_DEVICE_SH4 0x0103`
414
415			`/*`
416			`* Stepping of V3USC320 as read back from V3USC_PCI_CC_REV register`
417			`*/`
418			`#define V3USC_REV_A0 0`
419			`#define V3USC_REV_B0 1`
420			`#define V3USC_REV_B1 2`
421
422			`/*`
423			`* PCI Bus Parameters Register`
424			`* - Offset 3ch, Size 32 bits`
425			`*/`
426			`#define INTERRUPT_PIN_DISABLE 0x0 /* Disabled */`
427			`#define INTERRUPT_PIN_INTA 0x1 /* Use INTA */`
428			`#define INTERRUPT_PIN_INTB 0x2 /* Use INTB */`
429			`#define INTERRUPT_PIN_INTC 0x3 /* Use INTC */`
430			`#define INTERRUPT_PIN_INTD 0x4 /* Use INTD */`
431
432			`/*`
433			`* PCI Base Address for Peripheral Access`
434			`* - Offset 1ch, Size 32 bits`
435			`* PCI Intelligent I/O Address Translation Unit Local Bus Address Map Register`
436			`* - Offset ??h, Size 32 bits`
437			`*/`
438			`#define BYTE_SWAP_NO 0x0 /* No swap 32 bits */`
439			`#define BYTE_SWAP_16 0x1 /* 16 bits */`
440			`#define BYTE_SWAP_8 0x2 /* 8 bits */`
441			`#define BYTE_SWAP_AUTO 0x3 /* Auto swap use BE[3:0] */`
442			`#define APERTURE_SIZE_1M 0x0 /* Aperture size of 1 MB */`
443			`#define APERTURE_SIZE_2M 0x1 /* Aperture size of 2 MB */`
444			`#define APERTURE_SIZE_4M 0x2 /* Aperture size of 4 MB */`
445			`#define APERTURE_SIZE_8M 0x3 /* Aperture size of 8 MB */`
446			`#define APERTURE_SIZE_16M 0x4 /* Aperture size of 16 MB */`
447			`#define APERTURE_SIZE_32M 0x5 /* Aperture size of 32 MB */`
448			`#define APERTURE_SIZE_64M 0x6 /* Aperture size of 64 MB */`
449			`#define APERTURE_SIZE_128M 0x7 /* Aperture size of 128 MB */`
450			`#define APERTURE_SIZE_256M 0x8 /* Aperture size of 256 MB */`
451			`#define APERTURE_SIZE_512M 0x9 /* Aperture size of 512 MB */`
452			`#define APERTURE_SIZE_1G 0xa /* Aperture size of 1 GB */`
453
454			`#endif /* _V320USC_H_ */`