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phoenix |
/* $Id: dtlb_backend.S,v 1.1.1.1 2004-04-15 01:34:21 phoenix Exp $
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* dtlb_backend.S: Back end to DTLB miss replacement strategy.
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* This is included directly into the trap table.
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*
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* Copyright (C) 1996,1998 David S. Miller (davem@redhat.com)
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* Copyright (C) 1997,1998 Jakub Jelinek (jj@ultra.linux.cz)
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*/
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#include
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#if PAGE_SHIFT == 13
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#define FILL_VALID_SZ_BITS1(r1) \
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sllx %g2, 62, r1
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#define FILL_VALID_SZ_BITS2(r1)
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#define FILL_VALID_SZ_BITS_NOP nop
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#elif PAGE_SHIFT == 16
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#define FILL_VALID_SZ_BITS1(r1) \
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or %g0, 5, r1
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#define FILL_VALID_SZ_BITS2(r1) \
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sllx r1, 61, r1
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#define FILL_VALID_SZ_BITS_NOP
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#else
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#error unsupported PAGE_SIZE
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#endif /* PAGE_SHIFT */
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#define VPTE_BITS (_PAGE_CP | _PAGE_CV | _PAGE_P )
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#define VPTE_SHIFT (PAGE_SHIFT - 3)
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#define TLB_PMD_SHIFT (PAGE_SHIFT - 3 + 3)
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#define TLB_PGD_SHIFT (PMD_BITS + PAGE_SHIFT - 3 + 3)
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#define TLB_PMD_MASK (((1 << PMD_BITS) - 1) << 1)
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#define TLB_PGD_MASK (((1 << (VA_BITS - PAGE_SHIFT - (PAGE_SHIFT - 3) - PMD_BITS)) - 1) << 2)
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/* Ways we can get here:
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*
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* 1) Nucleus loads and stores to/from PA-->VA direct mappings at tl>1.
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* 2) Nucleus loads and stores to/from user/kernel window save areas.
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* 3) VPTE misses from dtlb_base and itlb_base.
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*/
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/* TLB1 ** ICACHE line 1: tl1 DTLB and quick VPTE miss */
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ldxa [%g1 + %g1] ASI_DMMU, %g4 ! Get TAG_ACCESS
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add %g3, %g3, %g5 ! Compute VPTE base
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cmp %g4, %g5 ! VPTE miss?
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bgeu,pt %xcc, 1f ! Continue here
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andcc %g4, TAG_CONTEXT_BITS, %g5 ! From Nucleus? (for tl0 miss)
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ba,pt %xcc, from_tl1_trap ! Fall to tl0 miss
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rdpr %tl, %g5 ! For tl0 miss TL==3 test
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1: sllx %g6, VPTE_SHIFT, %g4 ! Position TAG_ACCESS
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/* TLB1 ** ICACHE line 2: Quick VPTE miss */
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or %g4, %g5, %g4 ! Prepare TAG_ACCESS
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mov TSB_REG, %g1 ! Grab TSB reg
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ldxa [%g1] ASI_DMMU, %g5 ! Doing PGD caching?
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srlx %g6, (TLB_PMD_SHIFT - 1), %g1 ! Position PMD offset
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be,pn %xcc, sparc64_vpte_nucleus ! Is it from Nucleus?
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and %g1, TLB_PMD_MASK, %g1 ! Mask PMD offset bits
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brnz,pt %g5, sparc64_vpte_continue ! Yep, go like smoke
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add %g1, %g1, %g1 ! Position PMD offset some more
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/* TLB1 ** ICACHE line 3: Quick VPTE miss */
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srlx %g6, (TLB_PGD_SHIFT - 2), %g5 ! Position PGD offset
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and %g5, TLB_PGD_MASK, %g5 ! Mask PGD offset
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lduwa [%g7 + %g5] ASI_PHYS_USE_EC, %g5! Load PGD
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brz,pn %g5, vpte_noent ! Valid?
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sparc64_kpte_continue:
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sllx %g5, 11, %g5 ! Shift into place
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sparc64_vpte_continue:
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lduwa [%g5 + %g1] ASI_PHYS_USE_EC, %g5! Load PMD
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sllx %g5, 11, %g5 ! Shift into place
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brz,pn %g5, vpte_noent ! Valid?
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/* TLB1 ** ICACHE line 4: Quick VPTE miss */
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FILL_VALID_SZ_BITS1(%g1) ! Put _PAGE_VALID into %g1
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FILL_VALID_SZ_BITS2(%g1) ! Put _PAGE_VALID into %g1
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or %g5, VPTE_BITS, %g5 ! Prepare VPTE data
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or %g5, %g1, %g5 ! ...
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mov TLB_SFSR, %g1 ! Restore %g1 value
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stxa %g5, [%g0] ASI_DTLB_DATA_IN ! Load VPTE into TLB
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stxa %g4, [%g1 + %g1] ASI_DMMU ! Restore previous TAG_ACCESS
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retry ! Load PTE once again
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FILL_VALID_SZ_BITS_NOP
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#undef VPTE_SHIFT
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#undef TLB_PMD_SHIFT
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#undef TLB_PGD_SHIFT
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#undef VPTE_BITS
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#undef TLB_PMD_MASK
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#undef TLB_PGD_MASK
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#undef FILL_VALID_SZ_BITS1
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#undef FILL_VALID_SZ_BITS2
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#undef FILL_VALID_SZ_BITS_NOP
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