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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [sparc64/] [lib/] [VISmemset.S] - Blame information for rev 1765

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/* $Id: VISmemset.S,v 1.1.1.1 2004-04-15 01:33:49 phoenix Exp $
 * VISmemset.S: High speed memset operations utilizing the UltraSparc
 *        Visual Instruction Set.
 *
 * Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
 * Copyright (C) 1996, 1997, 1999 Jakub Jelinek (jakub@redhat.com)
 */
 
#include "VIS.h"
 
#ifdef REGS_64BIT
#define SET_BLOCKS(base, offset, source)        \
        stx     source, [base - offset - 0x18]; \
        stx     source, [base - offset - 0x10]; \
        stx     source, [base - offset - 0x08]; \
        stx     source, [base - offset - 0x00];
#else
#define SET_BLOCKS(base, offset, source)        \
        stw     source, [base - offset - 0x18]; \
        stw     source, [base - offset - 0x14]; \
        stw     source, [base - offset - 0x10]; \
        stw     source, [base - offset - 0x0c]; \
        stw     source, [base - offset - 0x08]; \
        stw     source, [base - offset - 0x04]; \
        stw     source, [base - offset - 0x00]; \
        stw     source, [base - offset + 0x04];
#endif
 
#ifndef __KERNEL__
/* So that the brz,a,pt in memset doesn't have to get through PLT, here we go... */
#include "VISbzero.S"
#endif
 
#ifdef __KERNEL__
#include 
#endif
 
        /* Well, memset is a lot easier to get right than bcopy... */
        .text
        .align          32
#ifdef __KERNEL__
        .globl          __memset
__memset:
#endif
        .globl          memset
memset:
#ifndef __KERNEL__
        brz,a,pt        %o1, bzero_private
         mov            %o2, %o1
#ifndef REGS_64BIT
        srl             %o2, 0, %o2
#endif
#endif
        mov             %o0, %o4
        cmp             %o2, 7
        bleu,pn         %xcc, 17f
         andcc          %o0, 3, %g5
        be,pt           %xcc, 4f
         and            %o1, 0xff, %o1
        cmp             %g5, 3
        be,pn           %xcc, 2f
         stb            %o1, [%o0 + 0x00]
        cmp             %g5, 2
        be,pt           %xcc, 2f
         stb            %o1, [%o0 + 0x01]
        stb             %o1, [%o0 + 0x02]
2:      sub             %g5, 4, %g5
        sub             %o0, %g5, %o0
        add             %o2, %g5, %o2
4:      sllx            %o1, 8, %g1
        andcc           %o0, 4, %g0
        or              %o1, %g1, %o1
        sllx            %o1, 16, %g1
        or              %o1, %g1, %o1
        be,pt           %xcc, 2f
#ifdef REGS_64BIT
         sllx           %o1, 32, %g1
#else
         cmp            %o2, 128
#endif
        stw             %o1, [%o0]
        sub             %o2, 4, %o2
        add             %o0, 4, %o0
2:
#ifdef REGS_64BIT
        cmp             %o2, 128
        or              %o1, %g1, %o1
#endif
        blu,pn          %xcc, 9f
         andcc          %o0, 0x38, %g5
        be,pn           %icc, 6f
         mov            64, %o5
        andcc           %o0, 8, %g0
        be,pn           %icc, 1f
         sub            %o5, %g5, %o5
#ifdef REGS_64BIT
        stx             %o1, [%o0]
#else
        stw             %o1, [%o0]
        stw             %o1, [%o0 + 4]
#endif
        add             %o0, 8, %o0
1:      andcc           %o5, 16, %g0
        be,pn           %icc, 1f
         sub            %o2, %o5, %o2
#ifdef REGS_64BIT
        stx             %o1, [%o0]
        stx             %o1, [%o0 + 8]
#else
        stw             %o1, [%o0]
        stw             %o1, [%o0 + 4]
        stw             %o1, [%o0 + 8]
        stw             %o1, [%o0 + 12]
#endif
        add             %o0, 16, %o0
1:      andcc           %o5, 32, %g0
        be,pn           %icc, 7f
         andncc         %o2, 0x3f, %o3
#ifdef REGS_64BIT
        stx             %o1, [%o0]
        stx             %o1, [%o0 + 8]
        stx             %o1, [%o0 + 16]
        stx             %o1, [%o0 + 24]
#else
        stw             %o1, [%o0]
        stw             %o1, [%o0 + 4]
        stw             %o1, [%o0 + 8]
        stw             %o1, [%o0 + 12]
        stw             %o1, [%o0 + 16]
        stw             %o1, [%o0 + 20]
        stw             %o1, [%o0 + 24]
        stw             %o1, [%o0 + 28]
#endif
        add             %o0, 32, %o0
7:      be,pn           %xcc, 9f
         nop
#ifdef __KERNEL__
        VISEntryHalf
#endif
        ldd             [%o0 - 8], %f0
18:     rd              %asi, %g2
        wr              %g0, ASI_BLK_P, %asi
        membar          #StoreStore | #LoadStore
        andcc           %o3, 0xc0, %g5
        and             %o2, 0x3f, %o2
        fmovd           %f0, %f2
        fmovd           %f0, %f4
        andn            %o3, 0xff, %o3
        fmovd           %f0, %f6
        cmp             %g5, 64
        fmovd           %f0, %f8
        fmovd           %f0, %f10
        fmovd           %f0, %f12
        brz,pn          %g5, 10f
         fmovd          %f0, %f14
        be,pn           %icc, 2f
         stda           %f0, [%o0 + 0x00] %asi
        cmp             %g5, 128
        be,pn           %icc, 2f
         stda           %f0, [%o0 + 0x40] %asi
        stda            %f0, [%o0 + 0x80] %asi
2:      brz,pn          %o3, 12f
         add            %o0, %g5, %o0
10:     stda            %f0, [%o0 + 0x00] %asi
        stda            %f0, [%o0 + 0x40] %asi
        stda            %f0, [%o0 + 0x80] %asi
        stda            %f0, [%o0 + 0xc0] %asi
11:     subcc           %o3, 256, %o3
        bne,pt          %xcc, 10b
         add            %o0, 256, %o0
12:
#ifdef __KERNEL__
        wr              %g2, %g0, %asi
        VISExitHalf
#else
#ifndef REGS_64BIT
        wr              %g0, FPRS_FEF, %fprs
#endif
#endif
        membar          #StoreLoad | #StoreStore
9:      andcc           %o2, 0x78, %g5
        be,pn           %xcc, 13f
         andcc          %o2, 7, %o2
#ifdef __KERNEL__
14:     srl             %g5, 1, %o3
        sethi           %hi(13f), %g3
        sub             %g3, %o3, %g3
        jmpl            %g3 + %lo(13f), %g0
         add            %o0, %g5, %o0
#else
14:     rd              %pc, %g3
#ifdef REGS_64BIT
        srl             %g5, 1, %o3
        sub             %g3, %o3, %g3
#else
        sub             %g3, %g5, %g3
#endif
        jmpl            %g3 + (13f - 14b), %g0
         add            %o0, %g5, %o0
#endif
12:     SET_BLOCKS(%o0, 0x68, %o1)
        SET_BLOCKS(%o0, 0x48, %o1)
        SET_BLOCKS(%o0, 0x28, %o1)
        SET_BLOCKS(%o0, 0x08, %o1)
13:     be,pn           %xcc, 8f
         andcc          %o2, 4, %g0
        be,pn           %xcc, 1f
         andcc          %o2, 2, %g0
        stw             %o1, [%o0]
        add             %o0, 4, %o0
1:      be,pn           %xcc, 1f
         andcc          %o2, 1, %g0
        sth             %o1, [%o0]
        add             %o0, 2, %o0
1:      bne,a,pn        %xcc, 8f
         stb            %o1, [%o0]
8:      retl
         mov            %o4, %o0
17:     brz,pn          %o2, 0f
8:       add            %o0, 1, %o0
        subcc           %o2, 1, %o2
        bne,pt          %xcc, 8b
         stb            %o1, [%o0 - 1]
0:      retl
         mov            %o4, %o0
6:
#ifdef REGS_64BIT
        stx             %o1, [%o0]
#else
        stw             %o1, [%o0]
        stw             %o1, [%o0 + 4]
#endif
        andncc          %o2, 0x3f, %o3
        be,pn           %xcc, 9b
         nop
#ifdef __KERNEL__
        VISEntryHalf
#endif
        ba,pt           %xcc, 18b
         ldd            [%o0], %f0

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [sparc64/] [lib/] [VISmemset.S] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	1275	phoenix	`/* $Id: VISmemset.S,v 1.1.1.1 2004-04-15 01:33:49 phoenix Exp $`
2			`* VISmemset.S: High speed memset operations utilizing the UltraSparc`
3			`* Visual Instruction Set.`
4			`*`
5			`* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)`
6			`* Copyright (C) 1996, 1997, 1999 Jakub Jelinek (jakub@redhat.com)`
7			`*/`
8
9			`#include "VIS.h"`
10
11			`#ifdef REGS_64BIT`
12			`#define SET_BLOCKS(base, offset, source) \`
13			`stx source, [base - offset - 0x18]; \`
14			`stx source, [base - offset - 0x10]; \`
15			`stx source, [base - offset - 0x08]; \`
16			`stx source, [base - offset - 0x00];`
17			`#else`
18			`#define SET_BLOCKS(base, offset, source) \`
19			`stw source, [base - offset - 0x18]; \`
20			`stw source, [base - offset - 0x14]; \`
21			`stw source, [base - offset - 0x10]; \`
22			`stw source, [base - offset - 0x0c]; \`
23			`stw source, [base - offset - 0x08]; \`
24			`stw source, [base - offset - 0x04]; \`
25			`stw source, [base - offset - 0x00]; \`
26			`stw source, [base - offset + 0x04];`
27			`#endif`
28
29			`#ifndef __KERNEL__`
30			`/* So that the brz,a,pt in memset doesn't have to get through PLT, here we go... */`
31			`#include "VISbzero.S"`
32			`#endif`
33
34			`#ifdef __KERNEL__`
35			`#include`
36			`#endif`
37
38			`/* Well, memset is a lot easier to get right than bcopy... */`
39			`.text`
40			`.align 32`
41			`#ifdef __KERNEL__`
42			`.globl __memset`
43			`__memset:`
44			`#endif`
45			`.globl memset`
46			`memset:`
47			`#ifndef __KERNEL__`
48			`brz,a,pt %o1, bzero_private`
49			`mov %o2, %o1`
50			`#ifndef REGS_64BIT`
51			`srl %o2, 0, %o2`
52			`#endif`
53			`#endif`
54			`mov %o0, %o4`
55			`cmp %o2, 7`
56			`bleu,pn %xcc, 17f`
57			`andcc %o0, 3, %g5`
58			`be,pt %xcc, 4f`
59			`and %o1, 0xff, %o1`
60			`cmp %g5, 3`
61			`be,pn %xcc, 2f`
62			`stb %o1, [%o0 + 0x00]`
63			`cmp %g5, 2`
64			`be,pt %xcc, 2f`
65			`stb %o1, [%o0 + 0x01]`
66			`stb %o1, [%o0 + 0x02]`
67			`2: sub %g5, 4, %g5`
68			`sub %o0, %g5, %o0`
69			`add %o2, %g5, %o2`
70			`4: sllx %o1, 8, %g1`
71			`andcc %o0, 4, %g0`
72			`or %o1, %g1, %o1`
73			`sllx %o1, 16, %g1`
74			`or %o1, %g1, %o1`
75			`be,pt %xcc, 2f`
76			`#ifdef REGS_64BIT`
77			`sllx %o1, 32, %g1`
78			`#else`
79			`cmp %o2, 128`
80			`#endif`
81			`stw %o1, [%o0]`
82			`sub %o2, 4, %o2`
83			`add %o0, 4, %o0`
84			`2:`
85			`#ifdef REGS_64BIT`
86			`cmp %o2, 128`
87			`or %o1, %g1, %o1`
88			`#endif`
89			`blu,pn %xcc, 9f`
90			`andcc %o0, 0x38, %g5`
91			`be,pn %icc, 6f`
92			`mov 64, %o5`
93			`andcc %o0, 8, %g0`
94			`be,pn %icc, 1f`
95			`sub %o5, %g5, %o5`
96			`#ifdef REGS_64BIT`
97			`stx %o1, [%o0]`
98			`#else`
99			`stw %o1, [%o0]`
100			`stw %o1, [%o0 + 4]`
101			`#endif`
102			`add %o0, 8, %o0`
103			`1: andcc %o5, 16, %g0`
104			`be,pn %icc, 1f`
105			`sub %o2, %o5, %o2`
106			`#ifdef REGS_64BIT`
107			`stx %o1, [%o0]`
108			`stx %o1, [%o0 + 8]`
109			`#else`
110			`stw %o1, [%o0]`
111			`stw %o1, [%o0 + 4]`
112			`stw %o1, [%o0 + 8]`
113			`stw %o1, [%o0 + 12]`
114			`#endif`
115			`add %o0, 16, %o0`
116			`1: andcc %o5, 32, %g0`
117			`be,pn %icc, 7f`
118			`andncc %o2, 0x3f, %o3`
119			`#ifdef REGS_64BIT`
120			`stx %o1, [%o0]`
121			`stx %o1, [%o0 + 8]`
122			`stx %o1, [%o0 + 16]`
123			`stx %o1, [%o0 + 24]`
124			`#else`
125			`stw %o1, [%o0]`
126			`stw %o1, [%o0 + 4]`
127			`stw %o1, [%o0 + 8]`
128			`stw %o1, [%o0 + 12]`
129			`stw %o1, [%o0 + 16]`
130			`stw %o1, [%o0 + 20]`
131			`stw %o1, [%o0 + 24]`
132			`stw %o1, [%o0 + 28]`
133			`#endif`
134			`add %o0, 32, %o0`
135			`7: be,pn %xcc, 9f`
136			`nop`
137			`#ifdef __KERNEL__`
138			`VISEntryHalf`
139			`#endif`
140			`ldd [%o0 - 8], %f0`
141			`18: rd %asi, %g2`
142			`wr %g0, ASI_BLK_P, %asi`
143			`membar #StoreStore \| #LoadStore`
144			`andcc %o3, 0xc0, %g5`
145			`and %o2, 0x3f, %o2`
146			`fmovd %f0, %f2`
147			`fmovd %f0, %f4`
148			`andn %o3, 0xff, %o3`
149			`fmovd %f0, %f6`
150			`cmp %g5, 64`
151			`fmovd %f0, %f8`
152			`fmovd %f0, %f10`
153			`fmovd %f0, %f12`
154			`brz,pn %g5, 10f`
155			`fmovd %f0, %f14`
156			`be,pn %icc, 2f`
157			`stda %f0, [%o0 + 0x00] %asi`
158			`cmp %g5, 128`
159			`be,pn %icc, 2f`
160			`stda %f0, [%o0 + 0x40] %asi`
161			`stda %f0, [%o0 + 0x80] %asi`
162			`2: brz,pn %o3, 12f`
163			`add %o0, %g5, %o0`
164			`10: stda %f0, [%o0 + 0x00] %asi`
165			`stda %f0, [%o0 + 0x40] %asi`
166			`stda %f0, [%o0 + 0x80] %asi`
167			`stda %f0, [%o0 + 0xc0] %asi`
168			`11: subcc %o3, 256, %o3`
169			`bne,pt %xcc, 10b`
170			`add %o0, 256, %o0`
171			`12:`
172			`#ifdef __KERNEL__`
173			`wr %g2, %g0, %asi`
174			`VISExitHalf`
175			`#else`
176			`#ifndef REGS_64BIT`
177			`wr %g0, FPRS_FEF, %fprs`
178			`#endif`
179			`#endif`
180			`membar #StoreLoad \| #StoreStore`
181			`9: andcc %o2, 0x78, %g5`
182			`be,pn %xcc, 13f`
183			`andcc %o2, 7, %o2`
184			`#ifdef __KERNEL__`
185			`14: srl %g5, 1, %o3`
186			`sethi %hi(13f), %g3`
187			`sub %g3, %o3, %g3`
188			`jmpl %g3 + %lo(13f), %g0`
189			`add %o0, %g5, %o0`
190			`#else`
191			`14: rd %pc, %g3`
192			`#ifdef REGS_64BIT`
193			`srl %g5, 1, %o3`
194			`sub %g3, %o3, %g3`
195			`#else`
196			`sub %g3, %g5, %g3`
197			`#endif`
198			`jmpl %g3 + (13f - 14b), %g0`
199			`add %o0, %g5, %o0`
200			`#endif`
201			`12: SET_BLOCKS(%o0, 0x68, %o1)`
202			`SET_BLOCKS(%o0, 0x48, %o1)`
203			`SET_BLOCKS(%o0, 0x28, %o1)`
204			`SET_BLOCKS(%o0, 0x08, %o1)`
205			`13: be,pn %xcc, 8f`
206			`andcc %o2, 4, %g0`
207			`be,pn %xcc, 1f`
208			`andcc %o2, 2, %g0`
209			`stw %o1, [%o0]`
210			`add %o0, 4, %o0`
211			`1: be,pn %xcc, 1f`
212			`andcc %o2, 1, %g0`
213			`sth %o1, [%o0]`
214			`add %o0, 2, %o0`
215			`1: bne,a,pn %xcc, 8f`
216			`stb %o1, [%o0]`
217			`8: retl`
218			`mov %o4, %o0`
219			`17: brz,pn %o2, 0f`
220			`8: add %o0, 1, %o0`
221			`subcc %o2, 1, %o2`
222			`bne,pt %xcc, 8b`
223			`stb %o1, [%o0 - 1]`
224			`0: retl`
225			`mov %o4, %o0`
226			`6:`
227			`#ifdef REGS_64BIT`
228			`stx %o1, [%o0]`
229			`#else`
230			`stw %o1, [%o0]`
231			`stw %o1, [%o0 + 4]`
232			`#endif`
233			`andncc %o2, 0x3f, %o3`
234			`be,pn %xcc, 9b`
235			`nop`
236			`#ifdef __KERNEL__`
237			`VISEntryHalf`
238			`#endif`
239			`ba,pt %xcc, 18b`
240			`ldd [%o0], %f0`