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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [sparc64/] [lib/] [bitops.S] - Blame information for rev 1765

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1 1275 phoenix 
/* $Id: bitops.S,v 1.1.1.1 2004-04-15 01:33:42 phoenix Exp $
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 * bitops.S: Sparc64 atomic bit operations.
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 *
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 * Copyright (C) 2000 David S. Miller (davem@redhat.com)
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 */
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#include
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        .text
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        .align  64
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        .globl  __bitops_begin
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__bitops_begin:
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        .globl  ___test_and_set_bit
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___test_and_set_bit:    /* %o0=nr, %o1=addr */
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        srlx    %o0, 6, %g1
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        mov     1, %g5
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        sllx    %g1, 3, %g3
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        and     %o0, 63, %g2
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        sllx    %g5, %g2, %g5
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        add     %o1, %g3, %o1
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        ldx     [%o1], %g7
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1:      andcc   %g7, %g5, %o0
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        bne,pn  %xcc, 2f
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         xor    %g7, %g5, %g1
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        casx    [%o1], %g7, %g1
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        cmp     %g7, %g1
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        bne,a,pn %xcc, 1b
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         ldx    [%o1], %g7
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2:      retl
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         membar #StoreLoad | #StoreStore
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        .globl  ___test_and_clear_bit
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___test_and_clear_bit:  /* %o0=nr, %o1=addr */
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        srlx    %o0, 6, %g1
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        mov     1, %g5
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        sllx    %g1, 3, %g3
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        and     %o0, 63, %g2
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        sllx    %g5, %g2, %g5
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        add     %o1, %g3, %o1
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        ldx     [%o1], %g7
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1:      andcc   %g7, %g5, %o0
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        be,pn   %xcc, 2f
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         xor    %g7, %g5, %g1
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        casx    [%o1], %g7, %g1
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        cmp     %g7, %g1
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        bne,a,pn %xcc, 1b
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         ldx    [%o1], %g7
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2:      retl
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         membar #StoreLoad | #StoreStore
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        .globl  ___test_and_change_bit
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___test_and_change_bit: /* %o0=nr, %o1=addr */
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        srlx    %o0, 6, %g1
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        mov     1, %g5
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        sllx    %g1, 3, %g3
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        and     %o0, 63, %g2
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        sllx    %g5, %g2, %g5
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        add     %o1, %g3, %o1
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        ldx     [%o1], %g7
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1:      and     %g7, %g5, %o0
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        xor     %g7, %g5, %g1
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        casx    [%o1], %g7, %g1
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        cmp     %g7, %g1
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        bne,a,pn %xcc, 1b
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         ldx    [%o1], %g7
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2:      retl
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         membar #StoreLoad | #StoreStore
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        nop
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        .globl  ___test_and_set_le_bit
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___test_and_set_le_bit: /* %o0=nr, %o1=addr */
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        srlx    %o0, 5, %g1
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        mov     1, %g5
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        sllx    %g1, 2, %g3
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        and     %o0, 31, %g2
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        sllx    %g5, %g2, %g5
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        add     %o1, %g3, %o1
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        lduwa   [%o1] ASI_PL, %g7
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1:      andcc   %g7, %g5, %o0
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        bne,pn  %icc, 2f
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         xor    %g7, %g5, %g1
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        casa    [%o1] ASI_PL, %g7, %g1
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        cmp     %g7, %g1
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        bne,a,pn %icc, 1b
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         lduwa  [%o1] ASI_PL, %g7
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2:      retl
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         membar #StoreLoad | #StoreStore
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        .globl  ___test_and_clear_le_bit
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___test_and_clear_le_bit:       /* %o0=nr, %o1=addr */
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        srlx    %o0, 5, %g1
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        mov     1, %g5
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        sllx    %g1, 2, %g3
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        and     %o0, 31, %g2
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        sllx    %g5, %g2, %g5
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        add     %o1, %g3, %o1
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        lduwa   [%o1] ASI_PL, %g7
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1:      andcc   %g7, %g5, %o0
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        be,pn   %icc, 2f
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         xor    %g7, %g5, %g1
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        casa    [%o1] ASI_PL, %g7, %g1
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        cmp     %g7, %g1
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        bne,a,pn %icc, 1b
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         lduwa  [%o1] ASI_PL, %g7
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2:      retl
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         membar #StoreLoad | #StoreStore
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        .globl  __bitops_end
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__bitops_end:

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