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/* $Id: math.c,v 1.1.1.1 2004-04-15 01:34:02 phoenix Exp $
 * arch/sparc64/math-emu/math.c
 *
 * Copyright (C) 1997,1999 Jakub Jelinek (jj@ultra.linux.cz)
 * Copyright (C) 1999 David S. Miller (davem@redhat.com)
 *
 * Emulation routines originate from soft-fp package, which is part
 * of glibc and has appropriate copyrights in it.
 */
 
#include <linux/types.h>
#include <linux/sched.h>
 
#include <asm/fpumacro.h>
#include <asm/ptrace.h>
#include <asm/uaccess.h>
 
#include "sfp-util.h"
#include <math-emu/soft-fp.h>
#include <math-emu/single.h>
#include <math-emu/double.h>
#include <math-emu/quad.h>
 
/* QUAD - ftt == 3 */
#define FMOVQ   0x003
#define FNEGQ   0x007
#define FABSQ   0x00b
#define FSQRTQ  0x02b
#define FADDQ   0x043
#define FSUBQ   0x047
#define FMULQ   0x04b
#define FDIVQ   0x04f
#define FDMULQ  0x06e
#define FQTOX   0x083
#define FXTOQ   0x08c
#define FQTOS   0x0c7
#define FQTOD   0x0cb
#define FITOQ   0x0cc
#define FSTOQ   0x0cd
#define FDTOQ   0x0ce
#define FQTOI   0x0d3
/* SUBNORMAL - ftt == 2 */
#define FSQRTS  0x029
#define FSQRTD  0x02a
#define FADDS   0x041
#define FADDD   0x042
#define FSUBS   0x045
#define FSUBD   0x046
#define FMULS   0x049
#define FMULD   0x04a
#define FDIVS   0x04d
#define FDIVD   0x04e
#define FSMULD  0x069
#define FSTOX   0x081
#define FDTOX   0x082
#define FDTOS   0x0c6
#define FSTOD   0x0c9
#define FSTOI   0x0d1
#define FDTOI   0x0d2
#define FXTOS   0x084 /* Only Ultra-III generates this. */
#define FXTOD   0x088 /* Only Ultra-III generates this. */
#if 0   /* Optimized inline in sparc64/kernel/entry.S */
#define FITOS   0x0c4 /* Only Ultra-III generates this. */
#endif
#define FITOD   0x0c8 /* Only Ultra-III generates this. */
/* FPOP2 */
#define FCMPQ   0x053
#define FCMPEQ  0x057
#define FMOVQ0  0x003
#define FMOVQ1  0x043
#define FMOVQ2  0x083
#define FMOVQ3  0x0c3
#define FMOVQI  0x103
#define FMOVQX  0x183
#define FMOVQZ  0x027
#define FMOVQLE 0x047
#define FMOVQLZ 0x067
#define FMOVQNZ 0x0a7
#define FMOVQGZ 0x0c7
#define FMOVQGE 0x0e7
 
#define FSR_TEM_SHIFT   23UL
#define FSR_TEM_MASK    (0x1fUL << FSR_TEM_SHIFT)
#define FSR_AEXC_SHIFT  5UL
#define FSR_AEXC_MASK   (0x1fUL << FSR_AEXC_SHIFT)
#define FSR_CEXC_SHIFT  0UL
#define FSR_CEXC_MASK   (0x1fUL << FSR_CEXC_SHIFT)
 
/* All routines returning an exception to raise should detect
 * such exceptions _before_ rounding to be consistant with
 * the behavior of the hardware in the implemented cases
 * (and thus with the recommendations in the V9 architecture
 * manual).
 *
 * We return 0 if a SIGFPE should be sent, 1 otherwise.
 */
static inline int record_exception(struct pt_regs *regs, int eflag)
{
        u64 fsr = current->thread.xfsr[0];
        int would_trap;
 
        /* Determine if this exception would have generated a trap. */
        would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;
 
        /* If trapping, we only want to signal one bit. */
        if(would_trap != 0) {
                eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);
                if((eflag & (eflag - 1)) != 0) {
                        if(eflag & FP_EX_INVALID)
                                eflag = FP_EX_INVALID;
                        else if(eflag & FP_EX_OVERFLOW)
                                eflag = FP_EX_OVERFLOW;
                        else if(eflag & FP_EX_UNDERFLOW)
                                eflag = FP_EX_UNDERFLOW;
                        else if(eflag & FP_EX_DIVZERO)
                                eflag = FP_EX_DIVZERO;
                        else if(eflag & FP_EX_INEXACT)
                                eflag = FP_EX_INEXACT;
                }
        }
 
        /* Set CEXC, here is the rule:
         *
         *    In general all FPU ops will set one and only one
         *    bit in the CEXC field, this is always the case
         *    when the IEEE exception trap is enabled in TEM.
         */
        fsr &= ~(FSR_CEXC_MASK);
        fsr |= ((long)eflag << FSR_CEXC_SHIFT);
 
        /* Set the AEXC field, rule is:
         *
         *    If a trap would not be generated, the
         *    CEXC just generated is OR'd into the
         *    existing value of AEXC.
         */
        if(would_trap == 0)
                fsr |= ((long)eflag << FSR_AEXC_SHIFT);
 
        /* If trapping, indicate fault trap type IEEE. */
        if(would_trap != 0)
                fsr |= (1UL << 14);
 
        current->thread.xfsr[0] = fsr;
 
        /* If we will not trap, advance the program counter over
         * the instruction being handled.
         */
        if(would_trap == 0) {
                regs->tpc = regs->tnpc;
                regs->tnpc += 4;
        }
 
        return (would_trap ? 0 : 1);
}
 
typedef union {
        u32 s;
        u64 d;
        u64 q[2];
} *argp;
 
int do_mathemu(struct pt_regs *regs, struct fpustate *f)
{
        unsigned long pc = regs->tpc;
        unsigned long tstate = regs->tstate;
        u32 insn = 0;
        int type = 0;
        /* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells
           whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)
           non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */
#define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) | (a << 0) | (bu << 5) | (b << 3) | (ru << 8) | (r << 6) | (ftt << 9)
        int freg;
        static u64 zero[2] = { 0L, 0L };
        int flags;
        FP_DECL_EX;
        FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);
        FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);
        FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);
        int IR;
        long XR, xfsr;
 
        if(tstate & TSTATE_PRIV)
                die_if_kernel("unfinished/unimplemented FPop from kernel", regs);
        if(current->thread.flags & SPARC_FLAG_32BIT)
                pc = (u32)pc;
        if (get_user(insn, (u32 *)pc) != -EFAULT) {
                if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {
                        switch ((insn >> 5) & 0x1ff) {
                        /* QUAD - ftt == 3 */
                        case FMOVQ:
                        case FNEGQ:
                        case FABSQ: TYPE(3,3,0,3,0,0,0); break;
                        case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;
                        case FADDQ:
                        case FSUBQ:
                        case FMULQ:
                        case FDIVQ: TYPE(3,3,1,3,1,3,1); break;
                        case FDMULQ: TYPE(3,3,1,2,1,2,1); break;
                        case FQTOX: TYPE(3,2,0,3,1,0,0); break;
                        case FXTOQ: TYPE(3,3,1,2,0,0,0); break;
                        case FQTOS: TYPE(3,1,1,3,1,0,0); break;
                        case FQTOD: TYPE(3,2,1,3,1,0,0); break;
                        case FITOQ: TYPE(3,3,1,1,0,0,0); break;
                        case FSTOQ: TYPE(3,3,1,1,1,0,0); break;
                        case FDTOQ: TYPE(3,3,1,2,1,0,0); break;
                        case FQTOI: TYPE(3,1,0,3,1,0,0); break;
                        /* SUBNORMAL - ftt == 2 */
                        case FSQRTS: TYPE(2,1,1,1,1,0,0); break;
                        case FSQRTD: TYPE(2,2,1,2,1,0,0); break;
                        case FADDD:
                        case FSUBD:
                        case FMULD:
                        case FDIVD: TYPE(2,2,1,2,1,2,1); break;
                        case FADDS:
                        case FSUBS:
                        case FMULS:
                        case FDIVS: TYPE(2,1,1,1,1,1,1); break;
                        case FSMULD: TYPE(2,2,1,1,1,1,1); break;
                        case FSTOX: TYPE(2,2,0,1,1,0,0); break;
                        case FDTOX: TYPE(2,2,0,2,1,0,0); break;
                        case FDTOS: TYPE(2,1,1,2,1,0,0); break;
                        case FSTOD: TYPE(2,2,1,1,1,0,0); break;
                        case FSTOI: TYPE(2,1,0,1,1,0,0); break;
                        case FDTOI: TYPE(2,1,0,2,1,0,0); break;
 
                        /* Only Ultra-III generates these */
                        case FXTOS: TYPE(2,1,1,2,0,0,0); break;
                        case FXTOD: TYPE(2,2,1,2,0,0,0); break;
#if 0                   /* Optimized inline in sparc64/kernel/entry.S */
                        case FITOS: TYPE(2,1,1,1,0,0,0); break;
#endif
                        case FITOD: TYPE(2,2,1,1,0,0,0); break;
                        }
                }
                else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {
                        IR = 2;
                        switch ((insn >> 5) & 0x1ff) {
                        case FCMPQ: TYPE(3,0,0,3,1,3,1); break;
                        case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;
                        /* Now the conditional fmovq support */
                        case FMOVQ0:
                        case FMOVQ1:
                        case FMOVQ2:
                        case FMOVQ3:
                                /* fmovq %fccX, %fY, %fZ */
                                if (!((insn >> 11) & 3))
                                        XR = current->thread.xfsr[0] >> 10;
                                else
                                        XR = current->thread.xfsr[0] >> (30 + ((insn >> 10) & 0x6));
                                XR &= 3;
                                IR = 0;
                                switch ((insn >> 14) & 0x7) {
                                /* case 0: IR = 0; break; */                    /* Never */
                                case 1: if (XR) IR = 1; break;                  /* Not Equal */
                                case 2: if (XR == 1 || XR == 2) IR = 1; break;  /* Less or Greater */
                                case 3: if (XR & 1) IR = 1; break;              /* Unordered or Less */
                                case 4: if (XR == 1) IR = 1; break;             /* Less */
                                case 5: if (XR & 2) IR = 1; break;              /* Unordered or Greater */
                                case 6: if (XR == 2) IR = 1; break;             /* Greater */
                                case 7: if (XR == 3) IR = 1; break;             /* Unordered */
                                }
                                if ((insn >> 14) & 8)
                                        IR ^= 1;
                                break;
                        case FMOVQI:
                        case FMOVQX:
                                /* fmovq %[ix]cc, %fY, %fZ */
                                XR = regs->tstate >> 32;
                                if ((insn >> 5) & 0x80)
                                        XR >>= 4;
                                XR &= 0xf;
                                IR = 0;
                                freg = ((XR >> 2) ^ XR) & 2;
                                switch ((insn >> 14) & 0x7) {
                                /* case 0: IR = 0; break; */                    /* Never */
                                case 1: if (XR & 4) IR = 1; break;              /* Equal */
                                case 2: if ((XR & 4) || freg) IR = 1; break;    /* Less or Equal */
                                case 3: if (freg) IR = 1; break;                /* Less */
                                case 4: if (XR & 5) IR = 1; break;              /* Less or Equal Unsigned */
                                case 5: if (XR & 1) IR = 1; break;              /* Carry Set */
                                case 6: if (XR & 8) IR = 1; break;              /* Negative */
                                case 7: if (XR & 2) IR = 1; break;              /* Overflow Set */
                                }
                                if ((insn >> 14) & 8)
                                        IR ^= 1;
                                break;
                        case FMOVQZ:
                        case FMOVQLE:
                        case FMOVQLZ:
                        case FMOVQNZ:
                        case FMOVQGZ:
                        case FMOVQGE:
                                freg = (insn >> 14) & 0x1f;
                                if (!freg)
                                        XR = 0;
                                else if (freg < 16)
                                        XR = regs->u_regs[freg];
                                else if (current->thread.flags & SPARC_FLAG_32BIT) {
                                        struct reg_window32 *win32;
                                        flushw_user ();
                                        win32 = (struct reg_window32 *)((unsigned long)((u32)regs->u_regs[UREG_FP]));
                                        get_user(XR, &win32->locals[freg - 16]);
                                } else {
                                        struct reg_window *win;
                                        flushw_user ();
                                        win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS);
                                        get_user(XR, &win->locals[freg - 16]);
                                }
                                IR = 0;
                                switch ((insn >> 10) & 3) {
                                case 1: if (!XR) IR = 1; break;                 /* Register Zero */
                                case 2: if (XR <= 0) IR = 1; break;              /* Register Less Than or Equal to Zero */
                                case 3: if (XR < 0) IR = 1; break;               /* Register Less Than Zero */
                                }
                                if ((insn >> 10) & 4)
                                        IR ^= 1;
                                break;
                        }
                        if (IR == 0) {
                                /* The fmov test was false. Do a nop instead */
                                current->thread.xfsr[0] &= ~(FSR_CEXC_MASK);
                                regs->tpc = regs->tnpc;
                                regs->tnpc += 4;
                                return 1;
                        } else if (IR == 1) {
                                /* Change the instruction into plain fmovq */
                                insn = (insn & 0x3e00001f) | 0x81a00060;
                                TYPE(3,3,0,3,0,0,0);
                        }
                }
        }
        if (type) {
                argp rs1 = NULL, rs2 = NULL, rd = NULL;
 
                freg = (current->thread.xfsr[0] >> 14) & 0xf;
                if (freg != (type >> 9))
                        goto err;
                current->thread.xfsr[0] &= ~0x1c000;
                freg = ((insn >> 14) & 0x1f);
                switch (type & 0x3) {
                case 3: if (freg & 2) {
                                current->thread.xfsr[0] |= (6 << 14) /* invalid_fp_register */;
                                goto err;
                        }
                case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
                case 1: rs1 = (argp)&f->regs[freg];
                        flags = (freg < 32) ? FPRS_DL : FPRS_DU;
                        if (!(current->thread.fpsaved[0] & flags))
                                rs1 = (argp)&zero;
                        break;
                }
                switch (type & 0x7) {
                case 7: FP_UNPACK_QP (QA, rs1); break;
                case 6: FP_UNPACK_DP (DA, rs1); break;
                case 5: FP_UNPACK_SP (SA, rs1); break;
                }
                freg = (insn & 0x1f);
                switch ((type >> 3) & 0x3) {
                case 3: if (freg & 2) {
                                current->thread.xfsr[0] |= (6 << 14) /* invalid_fp_register */;
                                goto err;
                        }
                case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
                case 1: rs2 = (argp)&f->regs[freg];
                        flags = (freg < 32) ? FPRS_DL : FPRS_DU;
                        if (!(current->thread.fpsaved[0] & flags))
                                rs2 = (argp)&zero;
                        break;
                }
                switch ((type >> 3) & 0x7) {
                case 7: FP_UNPACK_QP (QB, rs2); break;
                case 6: FP_UNPACK_DP (DB, rs2); break;
                case 5: FP_UNPACK_SP (SB, rs2); break;
                }
                freg = ((insn >> 25) & 0x1f);
                switch ((type >> 6) & 0x3) {
                case 3: if (freg & 2) {
                                current->thread.xfsr[0] |= (6 << 14) /* invalid_fp_register */;
                                goto err;
                        }
                case 2: freg = ((freg & 1) << 5) | (freg & 0x1e);
                case 1: rd = (argp)&f->regs[freg];
                        flags = (freg < 32) ? FPRS_DL : FPRS_DU;
                        if (!(current->thread.fpsaved[0] & FPRS_FEF)) {
                                current->thread.fpsaved[0] = FPRS_FEF;
                                current->thread.gsr[0] = 0;
                        }
                        if (!(current->thread.fpsaved[0] & flags)) {
                                if (freg < 32)
                                        memset(f->regs, 0, 32*sizeof(u32));
                                else
                                        memset(f->regs+32, 0, 32*sizeof(u32));
                        }
                        current->thread.fpsaved[0] |= flags;
                        break;
                }
                switch ((insn >> 5) & 0x1ff) {
                /* + */
                case FADDS: FP_ADD_S (SR, SA, SB); break;
                case FADDD: FP_ADD_D (DR, DA, DB); break;
                case FADDQ: FP_ADD_Q (QR, QA, QB); break;
                /* - */
                case FSUBS: FP_SUB_S (SR, SA, SB); break;
                case FSUBD: FP_SUB_D (DR, DA, DB); break;
                case FSUBQ: FP_SUB_Q (QR, QA, QB); break;
                /* * */
                case FMULS: FP_MUL_S (SR, SA, SB); break;
                case FSMULD: FP_CONV (D, S, 1, 1, DA, SA);
                             FP_CONV (D, S, 1, 1, DB, SB);
                case FMULD: FP_MUL_D (DR, DA, DB); break;
                case FDMULQ: FP_CONV (Q, D, 2, 1, QA, DA);
                             FP_CONV (Q, D, 2, 1, QB, DB);
                case FMULQ: FP_MUL_Q (QR, QA, QB); break;
                /* / */
                case FDIVS: FP_DIV_S (SR, SA, SB); break;
                case FDIVD: FP_DIV_D (DR, DA, DB); break;
                case FDIVQ: FP_DIV_Q (QR, QA, QB); break;
                /* sqrt */
                case FSQRTS: FP_SQRT_S (SR, SB); break;
                case FSQRTD: FP_SQRT_D (DR, DB); break;
                case FSQRTQ: FP_SQRT_Q (QR, QB); break;
                /* mov */
                case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break;
                case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break;
                case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break;
                /* float to int */
                case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;
                case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;
                case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;
                case FSTOX: FP_TO_INT_S (XR, SB, 64, 1); break;
                case FDTOX: FP_TO_INT_D (XR, DB, 64, 1); break;
                case FQTOX: FP_TO_INT_Q (XR, QB, 64, 1); break;
                /* int to float */
                case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;
                case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break;
                /* Only Ultra-III generates these */
                case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break;
                case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break;
#if 0           /* Optimized inline in sparc64/kernel/entry.S */
                case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;
#endif
                case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;
                /* float to float */
                case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break;
                case FSTOQ: FP_CONV (Q, S, 2, 1, QR, SB); break;
                case FDTOQ: FP_CONV (Q, D, 2, 1, QR, DB); break;
                case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break;
                case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break;
                case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break;
                /* comparison */
                case FCMPQ:
                case FCMPEQ:
                        FP_CMP_Q(XR, QB, QA, 3);
                        if (XR == 3 &&
                            (((insn >> 5) & 0x1ff) == FCMPEQ ||
                             FP_ISSIGNAN_Q(QA) ||
                             FP_ISSIGNAN_Q(QB)))
                                FP_SET_EXCEPTION (FP_EX_INVALID);
                }
                if (!FP_INHIBIT_RESULTS) {
                        switch ((type >> 6) & 0x7) {
                        case 0: xfsr = current->thread.xfsr[0];
                                if (XR == -1) XR = 2;
                                switch (freg & 3) {
                                /* fcc0, 1, 2, 3 */
                                case 0: xfsr &= ~0xc00; xfsr |= (XR << 10); break;
                                case 1: xfsr &= ~0x300000000UL; xfsr |= (XR << 32); break;
                                case 2: xfsr &= ~0xc00000000UL; xfsr |= (XR << 34); break;
                                case 3: xfsr &= ~0x3000000000UL; xfsr |= (XR << 36); break;
                                }
                                current->thread.xfsr[0] = xfsr;
                                break;
                        case 1: rd->s = IR; break;
                        case 2: rd->d = XR; break;
                        case 5: FP_PACK_SP (rd, SR); break;
                        case 6: FP_PACK_DP (rd, DR); break;
                        case 7: FP_PACK_QP (rd, QR); break;
                        }
                }
 
                if(_fex != 0)
                        return record_exception(regs, _fex);
 
                /* Success and no exceptions detected. */
                current->thread.xfsr[0] &= ~(FSR_CEXC_MASK);
                regs->tpc = regs->tnpc;
                regs->tnpc += 4;
                return 1;
        }
err:    return 0;
}

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [arch/] [sparc64/] [math-emu/] [math.c] - Blame information for rev 1275

Line No.	Rev	Author	Line
1	1275	phoenix	`/* $Id: math.c,v 1.1.1.1 2004-04-15 01:34:02 phoenix Exp $`
2			`* arch/sparc64/math-emu/math.c`
3			`*`
4			`* Copyright (C) 1997,1999 Jakub Jelinek (jj@ultra.linux.cz)`
5			`* Copyright (C) 1999 David S. Miller (davem@redhat.com)`
6			`*`
7			`* Emulation routines originate from soft-fp package, which is part`
8			`* of glibc and has appropriate copyrights in it.`
9			`*/`
10
11			`#include <linux/types.h>`
12			`#include <linux/sched.h>`
13
14			`#include <asm/fpumacro.h>`
15			`#include <asm/ptrace.h>`
16			`#include <asm/uaccess.h>`
17
18			`#include "sfp-util.h"`
19			`#include <math-emu/soft-fp.h>`
20			`#include <math-emu/single.h>`
21			`#include <math-emu/double.h>`
22			`#include <math-emu/quad.h>`
23
24			`/* QUAD - ftt == 3 */`
25			`#define FMOVQ 0x003`
26			`#define FNEGQ 0x007`
27			`#define FABSQ 0x00b`
28			`#define FSQRTQ 0x02b`
29			`#define FADDQ 0x043`
30			`#define FSUBQ 0x047`
31			`#define FMULQ 0x04b`
32			`#define FDIVQ 0x04f`
33			`#define FDMULQ 0x06e`
34			`#define FQTOX 0x083`
35			`#define FXTOQ 0x08c`
36			`#define FQTOS 0x0c7`
37			`#define FQTOD 0x0cb`
38			`#define FITOQ 0x0cc`
39			`#define FSTOQ 0x0cd`
40			`#define FDTOQ 0x0ce`
41			`#define FQTOI 0x0d3`
42			`/* SUBNORMAL - ftt == 2 */`
43			`#define FSQRTS 0x029`
44			`#define FSQRTD 0x02a`
45			`#define FADDS 0x041`
46			`#define FADDD 0x042`
47			`#define FSUBS 0x045`
48			`#define FSUBD 0x046`
49			`#define FMULS 0x049`
50			`#define FMULD 0x04a`
51			`#define FDIVS 0x04d`
52			`#define FDIVD 0x04e`
53			`#define FSMULD 0x069`
54			`#define FSTOX 0x081`
55			`#define FDTOX 0x082`
56			`#define FDTOS 0x0c6`
57			`#define FSTOD 0x0c9`
58			`#define FSTOI 0x0d1`
59			`#define FDTOI 0x0d2`
60			`#define FXTOS 0x084 /* Only Ultra-III generates this. */`
61			`#define FXTOD 0x088 /* Only Ultra-III generates this. */`
62			`#if 0 /* Optimized inline in sparc64/kernel/entry.S */`
63			`#define FITOS 0x0c4 /* Only Ultra-III generates this. */`
64			`#endif`
65			`#define FITOD 0x0c8 /* Only Ultra-III generates this. */`
66			`/* FPOP2 */`
67			`#define FCMPQ 0x053`
68			`#define FCMPEQ 0x057`
69			`#define FMOVQ0 0x003`
70			`#define FMOVQ1 0x043`
71			`#define FMOVQ2 0x083`
72			`#define FMOVQ3 0x0c3`
73			`#define FMOVQI 0x103`
74			`#define FMOVQX 0x183`
75			`#define FMOVQZ 0x027`
76			`#define FMOVQLE 0x047`
77			`#define FMOVQLZ 0x067`
78			`#define FMOVQNZ 0x0a7`
79			`#define FMOVQGZ 0x0c7`
80			`#define FMOVQGE 0x0e7`
81
82			`#define FSR_TEM_SHIFT 23UL`
83			`#define FSR_TEM_MASK (0x1fUL << FSR_TEM_SHIFT)`
84			`#define FSR_AEXC_SHIFT 5UL`
85			`#define FSR_AEXC_MASK (0x1fUL << FSR_AEXC_SHIFT)`
86			`#define FSR_CEXC_SHIFT 0UL`
87			`#define FSR_CEXC_MASK (0x1fUL << FSR_CEXC_SHIFT)`
88
89			`/* All routines returning an exception to raise should detect`
90			`* such exceptions _before_ rounding to be consistant with`
91			`* the behavior of the hardware in the implemented cases`
92			`* (and thus with the recommendations in the V9 architecture`
93			`* manual).`
94			`*`
95			`* We return 0 if a SIGFPE should be sent, 1 otherwise.`
96			`*/`
97			`static inline int record_exception(struct pt_regs *regs, int eflag)`
98			`{`
99			`u64 fsr = current->thread.xfsr[0];`
100			`int would_trap;`
101
102			`/* Determine if this exception would have generated a trap. */`
103			`would_trap = (fsr & ((long)eflag << FSR_TEM_SHIFT)) != 0UL;`
104
105			`/* If trapping, we only want to signal one bit. */`
106			`if(would_trap != 0) {`
107			`eflag &= ((fsr & FSR_TEM_MASK) >> FSR_TEM_SHIFT);`
108			`if((eflag & (eflag - 1)) != 0) {`
109			`if(eflag & FP_EX_INVALID)`
110			`eflag = FP_EX_INVALID;`
111			`else if(eflag & FP_EX_OVERFLOW)`
112			`eflag = FP_EX_OVERFLOW;`
113			`else if(eflag & FP_EX_UNDERFLOW)`
114			`eflag = FP_EX_UNDERFLOW;`
115			`else if(eflag & FP_EX_DIVZERO)`
116			`eflag = FP_EX_DIVZERO;`
117			`else if(eflag & FP_EX_INEXACT)`
118			`eflag = FP_EX_INEXACT;`
119			`}`
120			`}`
121
122			`/* Set CEXC, here is the rule:`
123			`*`
124			`* In general all FPU ops will set one and only one`
125			`* bit in the CEXC field, this is always the case`
126			`* when the IEEE exception trap is enabled in TEM.`
127			`*/`
128			`fsr &= ~(FSR_CEXC_MASK);`
129			`fsr \|= ((long)eflag << FSR_CEXC_SHIFT);`
130
131			`/* Set the AEXC field, rule is:`
132			`*`
133			`* If a trap would not be generated, the`
134			`* CEXC just generated is OR'd into the`
135			`* existing value of AEXC.`
136			`*/`
137			`if(would_trap == 0)`
138			`fsr \|= ((long)eflag << FSR_AEXC_SHIFT);`
139
140			`/* If trapping, indicate fault trap type IEEE. */`
141			`if(would_trap != 0)`
142			`fsr \|= (1UL << 14);`
143
144			`current->thread.xfsr[0] = fsr;`
145
146			`/* If we will not trap, advance the program counter over`
147			`* the instruction being handled.`
148			`*/`
149			`if(would_trap == 0) {`
150			`regs->tpc = regs->tnpc;`
151			`regs->tnpc += 4;`
152			`}`
153
154			`return (would_trap ? 0 : 1);`
155			`}`
156
157			`typedef union {`
158			`u32 s;`
159			`u64 d;`
160			`u64 q[2];`
161			`} *argp;`
162
163			`int do_mathemu(struct pt_regs regs, struct fpustate f)`
164			`{`
165			`unsigned long pc = regs->tpc;`
166			`unsigned long tstate = regs->tstate;`
167			`u32 insn = 0;`
168			`int type = 0;`
169			`/* ftt tells which ftt it may happen in, r is rd, b is rs2 and a is rs1. The *u arg tells`
170			`whether the argument should be packed/unpacked (0 - do not unpack/pack, 1 - unpack/pack)`
171			`non-u args tells the size of the argument (0 - no argument, 1 - single, 2 - double, 3 - quad */`
172			`#define TYPE(ftt, r, ru, b, bu, a, au) type = (au << 2) \| (a << 0) \| (bu << 5) \| (b << 3) \| (ru << 8) \| (r << 6) \| (ftt << 9)`
173			`int freg;`
174			`static u64 zero[2] = { 0L, 0L };`
175			`int flags;`
176			`FP_DECL_EX;`
177			`FP_DECL_S(SA); FP_DECL_S(SB); FP_DECL_S(SR);`
178			`FP_DECL_D(DA); FP_DECL_D(DB); FP_DECL_D(DR);`
179			`FP_DECL_Q(QA); FP_DECL_Q(QB); FP_DECL_Q(QR);`
180			`int IR;`
181			`long XR, xfsr;`
182
183			`if(tstate & TSTATE_PRIV)`
184			`die_if_kernel("unfinished/unimplemented FPop from kernel", regs);`
185			`if(current->thread.flags & SPARC_FLAG_32BIT)`
186			`pc = (u32)pc;`
187			`if (get_user(insn, (u32 *)pc) != -EFAULT) {`
188			`if ((insn & 0xc1f80000) == 0x81a00000) /* FPOP1 */ {`
189			`switch ((insn >> 5) & 0x1ff) {`
190			`/* QUAD - ftt == 3 */`
191			`case FMOVQ:`
192			`case FNEGQ:`
193			`case FABSQ: TYPE(3,3,0,3,0,0,0); break;`
194			`case FSQRTQ: TYPE(3,3,1,3,1,0,0); break;`
195			`case FADDQ:`
196			`case FSUBQ:`
197			`case FMULQ:`
198			`case FDIVQ: TYPE(3,3,1,3,1,3,1); break;`
199			`case FDMULQ: TYPE(3,3,1,2,1,2,1); break;`
200			`case FQTOX: TYPE(3,2,0,3,1,0,0); break;`
201			`case FXTOQ: TYPE(3,3,1,2,0,0,0); break;`
202			`case FQTOS: TYPE(3,1,1,3,1,0,0); break;`
203			`case FQTOD: TYPE(3,2,1,3,1,0,0); break;`
204			`case FITOQ: TYPE(3,3,1,1,0,0,0); break;`
205			`case FSTOQ: TYPE(3,3,1,1,1,0,0); break;`
206			`case FDTOQ: TYPE(3,3,1,2,1,0,0); break;`
207			`case FQTOI: TYPE(3,1,0,3,1,0,0); break;`
208			`/* SUBNORMAL - ftt == 2 */`
209			`case FSQRTS: TYPE(2,1,1,1,1,0,0); break;`
210			`case FSQRTD: TYPE(2,2,1,2,1,0,0); break;`
211			`case FADDD:`
212			`case FSUBD:`
213			`case FMULD:`
214			`case FDIVD: TYPE(2,2,1,2,1,2,1); break;`
215			`case FADDS:`
216			`case FSUBS:`
217			`case FMULS:`
218			`case FDIVS: TYPE(2,1,1,1,1,1,1); break;`
219			`case FSMULD: TYPE(2,2,1,1,1,1,1); break;`
220			`case FSTOX: TYPE(2,2,0,1,1,0,0); break;`
221			`case FDTOX: TYPE(2,2,0,2,1,0,0); break;`
222			`case FDTOS: TYPE(2,1,1,2,1,0,0); break;`
223			`case FSTOD: TYPE(2,2,1,1,1,0,0); break;`
224			`case FSTOI: TYPE(2,1,0,1,1,0,0); break;`
225			`case FDTOI: TYPE(2,1,0,2,1,0,0); break;`
226
227			`/* Only Ultra-III generates these */`
228			`case FXTOS: TYPE(2,1,1,2,0,0,0); break;`
229			`case FXTOD: TYPE(2,2,1,2,0,0,0); break;`
230			`#if 0 /* Optimized inline in sparc64/kernel/entry.S */`
231			`case FITOS: TYPE(2,1,1,1,0,0,0); break;`
232			`#endif`
233			`case FITOD: TYPE(2,2,1,1,0,0,0); break;`
234			`}`
235			`}`
236			`else if ((insn & 0xc1f80000) == 0x81a80000) /* FPOP2 */ {`
237			`IR = 2;`
238			`switch ((insn >> 5) & 0x1ff) {`
239			`case FCMPQ: TYPE(3,0,0,3,1,3,1); break;`
240			`case FCMPEQ: TYPE(3,0,0,3,1,3,1); break;`
241			`/* Now the conditional fmovq support */`
242			`case FMOVQ0:`
243			`case FMOVQ1:`
244			`case FMOVQ2:`
245			`case FMOVQ3:`
246			`/* fmovq %fccX, %fY, %fZ */`
247			`if (!((insn >> 11) & 3))`
248			`XR = current->thread.xfsr[0] >> 10;`
249			`else`
250			`XR = current->thread.xfsr[0] >> (30 + ((insn >> 10) & 0x6));`
251			`XR &= 3;`
252			`IR = 0;`
253			`switch ((insn >> 14) & 0x7) {`
254			`/* case 0: IR = 0; break; / / Never */`
255			`case 1: if (XR) IR = 1; break; /* Not Equal */`
256			`case 2: if (XR == 1 \|\| XR == 2) IR = 1; break; /* Less or Greater */`
257			`case 3: if (XR & 1) IR = 1; break; /* Unordered or Less */`
258			`case 4: if (XR == 1) IR = 1; break; /* Less */`
259			`case 5: if (XR & 2) IR = 1; break; /* Unordered or Greater */`
260			`case 6: if (XR == 2) IR = 1; break; /* Greater */`
261			`case 7: if (XR == 3) IR = 1; break; /* Unordered */`
262			`}`
263			`if ((insn >> 14) & 8)`
264			`IR ^= 1;`
265			`break;`
266			`case FMOVQI:`
267			`case FMOVQX:`
268			`/* fmovq %[ix]cc, %fY, %fZ */`
269			`XR = regs->tstate >> 32;`
270			`if ((insn >> 5) & 0x80)`
271			`XR >>= 4;`
272			`XR &= 0xf;`
273			`IR = 0;`
274			`freg = ((XR >> 2) ^ XR) & 2;`
275			`switch ((insn >> 14) & 0x7) {`
276			`/* case 0: IR = 0; break; / / Never */`
277			`case 1: if (XR & 4) IR = 1; break; /* Equal */`
278			`case 2: if ((XR & 4) \|\| freg) IR = 1; break; /* Less or Equal */`
279			`case 3: if (freg) IR = 1; break; /* Less */`
280			`case 4: if (XR & 5) IR = 1; break; /* Less or Equal Unsigned */`
281			`case 5: if (XR & 1) IR = 1; break; /* Carry Set */`
282			`case 6: if (XR & 8) IR = 1; break; /* Negative */`
283			`case 7: if (XR & 2) IR = 1; break; /* Overflow Set */`
284			`}`
285			`if ((insn >> 14) & 8)`
286			`IR ^= 1;`
287			`break;`
288			`case FMOVQZ:`
289			`case FMOVQLE:`
290			`case FMOVQLZ:`
291			`case FMOVQNZ:`
292			`case FMOVQGZ:`
293			`case FMOVQGE:`
294			`freg = (insn >> 14) & 0x1f;`
295			`if (!freg)`
296			`XR = 0;`
297			`else if (freg < 16)`
298			`XR = regs->u_regs[freg];`
299			`else if (current->thread.flags & SPARC_FLAG_32BIT) {`
300			`struct reg_window32 *win32;`
301			`flushw_user ();`
302			`win32 = (struct reg_window32 *)((unsigned long)((u32)regs->u_regs[UREG_FP]));`
303			`get_user(XR, &win32->locals[freg - 16]);`
304			`} else {`
305			`struct reg_window *win;`
306			`flushw_user ();`
307			`win = (struct reg_window *)(regs->u_regs[UREG_FP] + STACK_BIAS);`
308			`get_user(XR, &win->locals[freg - 16]);`
309			`}`
310			`IR = 0;`
311			`switch ((insn >> 10) & 3) {`
312			`case 1: if (!XR) IR = 1; break; /* Register Zero */`
313			`case 2: if (XR <= 0) IR = 1; break; /* Register Less Than or Equal to Zero */`
314			`case 3: if (XR < 0) IR = 1; break; /* Register Less Than Zero */`
315			`}`
316			`if ((insn >> 10) & 4)`
317			`IR ^= 1;`
318			`break;`
319			`}`
320			`if (IR == 0) {`
321			`/* The fmov test was false. Do a nop instead */`
322			`current->thread.xfsr[0] &= ~(FSR_CEXC_MASK);`
323			`regs->tpc = regs->tnpc;`
324			`regs->tnpc += 4;`
325			`return 1;`
326			`} else if (IR == 1) {`
327			`/* Change the instruction into plain fmovq */`
328			`insn = (insn & 0x3e00001f) \| 0x81a00060;`
329			`TYPE(3,3,0,3,0,0,0);`
330			`}`
331			`}`
332			`}`
333			`if (type) {`
334			`argp rs1 = NULL, rs2 = NULL, rd = NULL;`
335
336			`freg = (current->thread.xfsr[0] >> 14) & 0xf;`
337			`if (freg != (type >> 9))`
338			`goto err;`
339			`current->thread.xfsr[0] &= ~0x1c000;`
340			`freg = ((insn >> 14) & 0x1f);`
341			`switch (type & 0x3) {`
342			`case 3: if (freg & 2) {`
343			`current->thread.xfsr[0] \|= (6 << 14) /* invalid_fp_register */;`
344			`goto err;`
345			`}`
346			`case 2: freg = ((freg & 1) << 5) \| (freg & 0x1e);`
347			`case 1: rs1 = (argp)&f->regs[freg];`
348			`flags = (freg < 32) ? FPRS_DL : FPRS_DU;`
349			`if (!(current->thread.fpsaved[0] & flags))`
350			`rs1 = (argp)&zero;`
351			`break;`
352			`}`
353			`switch (type & 0x7) {`
354			`case 7: FP_UNPACK_QP (QA, rs1); break;`
355			`case 6: FP_UNPACK_DP (DA, rs1); break;`
356			`case 5: FP_UNPACK_SP (SA, rs1); break;`
357			`}`
358			`freg = (insn & 0x1f);`
359			`switch ((type >> 3) & 0x3) {`
360			`case 3: if (freg & 2) {`
361			`current->thread.xfsr[0] \|= (6 << 14) /* invalid_fp_register */;`
362			`goto err;`
363			`}`
364			`case 2: freg = ((freg & 1) << 5) \| (freg & 0x1e);`
365			`case 1: rs2 = (argp)&f->regs[freg];`
366			`flags = (freg < 32) ? FPRS_DL : FPRS_DU;`
367			`if (!(current->thread.fpsaved[0] & flags))`
368			`rs2 = (argp)&zero;`
369			`break;`
370			`}`
371			`switch ((type >> 3) & 0x7) {`
372			`case 7: FP_UNPACK_QP (QB, rs2); break;`
373			`case 6: FP_UNPACK_DP (DB, rs2); break;`
374			`case 5: FP_UNPACK_SP (SB, rs2); break;`
375			`}`
376			`freg = ((insn >> 25) & 0x1f);`
377			`switch ((type >> 6) & 0x3) {`
378			`case 3: if (freg & 2) {`
379			`current->thread.xfsr[0] \|= (6 << 14) /* invalid_fp_register */;`
380			`goto err;`
381			`}`
382			`case 2: freg = ((freg & 1) << 5) \| (freg & 0x1e);`
383			`case 1: rd = (argp)&f->regs[freg];`
384			`flags = (freg < 32) ? FPRS_DL : FPRS_DU;`
385			`if (!(current->thread.fpsaved[0] & FPRS_FEF)) {`
386			`current->thread.fpsaved[0] = FPRS_FEF;`
387			`current->thread.gsr[0] = 0;`
388			`}`
389			`if (!(current->thread.fpsaved[0] & flags)) {`
390			`if (freg < 32)`
391			`memset(f->regs, 0, 32*sizeof(u32));`
392			`else`
393			`memset(f->regs+32, 0, 32*sizeof(u32));`
394			`}`
395			`current->thread.fpsaved[0] \|= flags;`
396			`break;`
397			`}`
398			`switch ((insn >> 5) & 0x1ff) {`
399			`/* + */`
400			`case FADDS: FP_ADD_S (SR, SA, SB); break;`
401			`case FADDD: FP_ADD_D (DR, DA, DB); break;`
402			`case FADDQ: FP_ADD_Q (QR, QA, QB); break;`
403			`/* - */`
404			`case FSUBS: FP_SUB_S (SR, SA, SB); break;`
405			`case FSUBD: FP_SUB_D (DR, DA, DB); break;`
406			`case FSUBQ: FP_SUB_Q (QR, QA, QB); break;`
407			`/* * */`
408			`case FMULS: FP_MUL_S (SR, SA, SB); break;`
409			`case FSMULD: FP_CONV (D, S, 1, 1, DA, SA);`
410			`FP_CONV (D, S, 1, 1, DB, SB);`
411			`case FMULD: FP_MUL_D (DR, DA, DB); break;`
412			`case FDMULQ: FP_CONV (Q, D, 2, 1, QA, DA);`
413			`FP_CONV (Q, D, 2, 1, QB, DB);`
414			`case FMULQ: FP_MUL_Q (QR, QA, QB); break;`
415			`/* / */`
416			`case FDIVS: FP_DIV_S (SR, SA, SB); break;`
417			`case FDIVD: FP_DIV_D (DR, DA, DB); break;`
418			`case FDIVQ: FP_DIV_Q (QR, QA, QB); break;`
419			`/* sqrt */`
420			`case FSQRTS: FP_SQRT_S (SR, SB); break;`
421			`case FSQRTD: FP_SQRT_D (DR, DB); break;`
422			`case FSQRTQ: FP_SQRT_Q (QR, QB); break;`
423			`/* mov */`
424			`case FMOVQ: rd->q[0] = rs2->q[0]; rd->q[1] = rs2->q[1]; break;`
425			`case FABSQ: rd->q[0] = rs2->q[0] & 0x7fffffffffffffffUL; rd->q[1] = rs2->q[1]; break;`
426			`case FNEGQ: rd->q[0] = rs2->q[0] ^ 0x8000000000000000UL; rd->q[1] = rs2->q[1]; break;`
427			`/* float to int */`
428			`case FSTOI: FP_TO_INT_S (IR, SB, 32, 1); break;`
429			`case FDTOI: FP_TO_INT_D (IR, DB, 32, 1); break;`
430			`case FQTOI: FP_TO_INT_Q (IR, QB, 32, 1); break;`
431			`case FSTOX: FP_TO_INT_S (XR, SB, 64, 1); break;`
432			`case FDTOX: FP_TO_INT_D (XR, DB, 64, 1); break;`
433			`case FQTOX: FP_TO_INT_Q (XR, QB, 64, 1); break;`
434			`/* int to float */`
435			`case FITOQ: IR = rs2->s; FP_FROM_INT_Q (QR, IR, 32, int); break;`
436			`case FXTOQ: XR = rs2->d; FP_FROM_INT_Q (QR, XR, 64, long); break;`
437			`/* Only Ultra-III generates these */`
438			`case FXTOS: XR = rs2->d; FP_FROM_INT_S (SR, XR, 64, long); break;`
439			`case FXTOD: XR = rs2->d; FP_FROM_INT_D (DR, XR, 64, long); break;`
440			`#if 0 /* Optimized inline in sparc64/kernel/entry.S */`
441			`case FITOS: IR = rs2->s; FP_FROM_INT_S (SR, IR, 32, int); break;`
442			`#endif`
443			`case FITOD: IR = rs2->s; FP_FROM_INT_D (DR, IR, 32, int); break;`
444			`/* float to float */`
445			`case FSTOD: FP_CONV (D, S, 1, 1, DR, SB); break;`
446			`case FSTOQ: FP_CONV (Q, S, 2, 1, QR, SB); break;`
447			`case FDTOQ: FP_CONV (Q, D, 2, 1, QR, DB); break;`
448			`case FDTOS: FP_CONV (S, D, 1, 1, SR, DB); break;`
449			`case FQTOS: FP_CONV (S, Q, 1, 2, SR, QB); break;`
450			`case FQTOD: FP_CONV (D, Q, 1, 2, DR, QB); break;`
451			`/* comparison */`
452			`case FCMPQ:`
453			`case FCMPEQ:`
454			`FP_CMP_Q(XR, QB, QA, 3);`
455			`if (XR == 3 &&`
456			`(((insn >> 5) & 0x1ff) == FCMPEQ \|\|`
457			`FP_ISSIGNAN_Q(QA) \|\|`
458			`FP_ISSIGNAN_Q(QB)))`
459			`FP_SET_EXCEPTION (FP_EX_INVALID);`
460			`}`
461			`if (!FP_INHIBIT_RESULTS) {`
462			`switch ((type >> 6) & 0x7) {`
463			`case 0: xfsr = current->thread.xfsr[0];`
464			`if (XR == -1) XR = 2;`
465			`switch (freg & 3) {`
466			`/* fcc0, 1, 2, 3 */`
467			`case 0: xfsr &= ~0xc00; xfsr \|= (XR << 10); break;`
468			`case 1: xfsr &= ~0x300000000UL; xfsr \|= (XR << 32); break;`
469			`case 2: xfsr &= ~0xc00000000UL; xfsr \|= (XR << 34); break;`
470			`case 3: xfsr &= ~0x3000000000UL; xfsr \|= (XR << 36); break;`
471			`}`
472			`current->thread.xfsr[0] = xfsr;`
473			`break;`
474			`case 1: rd->s = IR; break;`
475			`case 2: rd->d = XR; break;`
476			`case 5: FP_PACK_SP (rd, SR); break;`
477			`case 6: FP_PACK_DP (rd, DR); break;`
478			`case 7: FP_PACK_QP (rd, QR); break;`
479			`}`
480			`}`
481
482			`if(_fex != 0)`
483			`return record_exception(regs, _fex);`
484
485			`/* Success and no exceptions detected. */`
486			`current->thread.xfsr[0] &= ~(FSR_CEXC_MASK);`
487			`regs->tpc = regs->tnpc;`
488			`regs->tnpc += 4;`
489			`return 1;`
490			`}`
491			`err: return 0;`
492			`}`