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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [atm/] [nicstarmac.c] - Blame information for rev 1765

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Line No. Rev Author Line
1 1275 phoenix
/*
2
 * this file included by nicstar.c
3
 */
4
 
5
/*
6
 * nicstarmac.c
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 * Read this ForeRunner's MAC address from eprom/eeprom
8
 */
9
 
10
#define CYCLE_DELAY 5
11
 
12
/* This was the original definition
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#define osp_MicroDelay(microsec) \
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    do { int _i = 4*microsec; while (--_i > 0) { __SLOW_DOWN_IO; }} while (0)
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*/
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#define osp_MicroDelay(microsec) {unsigned long useconds = (microsec); \
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                                  udelay((useconds));}
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19
 
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/* The following tables represent the timing diagrams found in
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 * the Data Sheet for the Xicor X25020 EEProm.  The #defines below
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 * represent the bits in the NICStAR's General Purpose register
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 * that must be toggled for the corresponding actions on the EEProm
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 * to occur.
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 */
26
 
27
/* Write Data To EEProm from SI line on rising edge of CLK */
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/* Read Data From EEProm on falling edge of CLK */
29
 
30
#define CS_HIGH         0x0002          /* Chip select high */
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#define CS_LOW          0x0000          /* Chip select low (active low)*/
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#define CLK_HIGH        0x0004          /* Clock high */
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#define CLK_LOW         0x0000          /* Clock low  */
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#define SI_HIGH         0x0001          /* Serial input data high */
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#define SI_LOW          0x0000          /* Serial input data low */
36
 
37
/* Read Status Register = 0000 0101b */
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static u_int32_t rdsrtab[] =
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{
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    CS_HIGH | CLK_HIGH,
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    CS_LOW | CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW | SI_HIGH,
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    CLK_HIGH | SI_HIGH,   /* 1 */
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    CLK_LOW | SI_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW | SI_HIGH,
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    CLK_HIGH | SI_HIGH   /* 1 */
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};
58
 
59
 
60
/* Read from EEPROM = 0000 0011b */
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static u_int32_t readtab[] =
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{
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    /*
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    CS_HIGH | CLK_HIGH,
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    */
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    CS_LOW | CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW,
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    CLK_HIGH,             /* 0 */
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    CLK_LOW | SI_HIGH,
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    CLK_HIGH | SI_HIGH,   /* 1 */
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    CLK_LOW | SI_HIGH,
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    CLK_HIGH | SI_HIGH    /* 1 */
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};
83
 
84
 
85
/* Clock to read from/write to the eeprom */
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static u_int32_t clocktab[] =
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{
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    CLK_LOW,
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    CLK_HIGH,
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    CLK_LOW,
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    CLK_HIGH,
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    CLK_LOW,
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    CLK_HIGH,
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    CLK_LOW,
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    CLK_HIGH,
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    CLK_LOW,
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    CLK_HIGH,
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    CLK_LOW,
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    CLK_HIGH,
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    CLK_LOW,
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    CLK_HIGH,
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    CLK_LOW,
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    CLK_HIGH,
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    CLK_LOW
105
};
106
 
107
 
108
#define NICSTAR_REG_WRITE(bs, reg, val) \
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        while ( readl(bs + STAT) & 0x0200 ) ; \
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        writel((val),(base)+(reg))
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#define NICSTAR_REG_READ(bs, reg) \
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        readl((base)+(reg))
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#define NICSTAR_REG_GENERAL_PURPOSE GP
114
 
115
/*
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 * This routine will clock the Read_Status_reg function into the X2520
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 * eeprom, then pull the result from bit 16 of the NicSTaR's General Purpose
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 * register.
119
 */
120
 
121
u_int32_t
122
nicstar_read_eprom_status( virt_addr_t base )
123
{
124
   u_int32_t    val;
125
   u_int32_t    rbyte;
126
   int32_t      i, j;
127
 
128
   /* Send read instruction */
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   val = NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) & 0xFFFFFFF0;
130
 
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   for (i=0; i<sizeof rdsrtab/sizeof rdsrtab[0]; i++)
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   {
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        NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE,
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                (val | rdsrtab[i]) );
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        osp_MicroDelay( CYCLE_DELAY );
136
   }
137
 
138
   /* Done sending instruction - now pull data off of bit 16, MSB first */
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   /* Data clocked out of eeprom on falling edge of clock */
140
 
141
   rbyte = 0;
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   for (i=7, j=0; i>=0; i--)
143
   {
144
        NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE,
145
                (val | clocktab[j++]) );
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        rbyte |= (((NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE)
147
                        & 0x00010000) >> 16) << i);
148
        NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE,
149
                (val | clocktab[j++]) );
150
        osp_MicroDelay( CYCLE_DELAY );
151
   }
152
   NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 2 );
153
   osp_MicroDelay( CYCLE_DELAY );
154
   return rbyte;
155
}
156
 
157
 
158
/*
159
 * This routine will clock the Read_data function into the X2520
160
 * eeprom, followed by the address to read from, through the NicSTaR's General
161
 * Purpose register.
162
 */
163
 
164
static u_int8_t
165
read_eprom_byte(u_int32_t base, u_int8_t offset)
166
{
167
   u_int32_t val = 0;
168
   int i,j=0;
169
   u_int8_t tempread = 0;
170
 
171
   val = NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE ) & 0xFFFFFFF0;
172
 
173
   /* Send READ instruction */
174
   for (i=0; i<sizeof readtab/sizeof readtab[0]; i++)
175
   {
176
        NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE,
177
                (val | readtab[i]) );
178
        osp_MicroDelay( CYCLE_DELAY );
179
   }
180
 
181
   /* Next, we need to send the byte address to read from */
182
   for (i=7; i>=0; i--)
183
   {
184
      NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE,
185
                (val | clocktab[j++] | ((offset >> i) & 1) ) );
186
      osp_MicroDelay(CYCLE_DELAY);
187
      NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE,
188
                (val | clocktab[j++] | ((offset >> i) & 1) ) );
189
      osp_MicroDelay( CYCLE_DELAY );
190
   }
191
 
192
   j = 0;
193
 
194
   /* Now, we can read data from the eeprom by clocking it in */
195
   for (i=7; i>=0; i--)
196
   {
197
      NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE,
198
                (val | clocktab[j++]) );
199
      osp_MicroDelay( CYCLE_DELAY );
200
      tempread |= (((NICSTAR_REG_READ( base, NICSTAR_REG_GENERAL_PURPOSE )
201
                & 0x00010000) >> 16) << i);
202
      NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE,
203
                (val | clocktab[j++]) );
204
      osp_MicroDelay( CYCLE_DELAY );
205
   }
206
 
207
   NICSTAR_REG_WRITE( base, NICSTAR_REG_GENERAL_PURPOSE, 2 );
208
   osp_MicroDelay( CYCLE_DELAY );
209
   return tempread;
210
}
211
 
212
 
213
void
214
nicstar_init_eprom( virt_addr_t base )
215
{
216
    u_int32_t val;
217
 
218
    /*
219
     * turn chip select off
220
     */
221
    val = NICSTAR_REG_READ(base, NICSTAR_REG_GENERAL_PURPOSE) & 0xFFFFFFF0;
222
 
223
    NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
224
        (val | CS_HIGH | CLK_HIGH));
225
    osp_MicroDelay( CYCLE_DELAY );
226
 
227
    NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
228
        (val | CS_HIGH | CLK_LOW));
229
    osp_MicroDelay( CYCLE_DELAY );
230
 
231
    NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
232
        (val | CS_HIGH | CLK_HIGH));
233
    osp_MicroDelay( CYCLE_DELAY );
234
 
235
    NICSTAR_REG_WRITE(base, NICSTAR_REG_GENERAL_PURPOSE,
236
        (val | CS_HIGH | CLK_LOW));
237
    osp_MicroDelay( CYCLE_DELAY );
238
}
239
 
240
 
241
/*
242
 * This routine will be the interface to the ReadPromByte function
243
 * above.
244
 */
245
 
246
void
247
nicstar_read_eprom(
248
    virt_addr_t base,
249
    u_int8_t    prom_offset,
250
    u_int8_t    *buffer,
251
    u_int32_t   nbytes )
252
{
253
    u_int               i;
254
 
255
    for (i=0; i<nbytes; i++)
256
    {
257
        buffer[i] = read_eprom_byte( base, prom_offset );
258
        ++prom_offset;
259
        osp_MicroDelay( CYCLE_DELAY );
260
    }
261
}
262
 
263
 
264
/*
265
void osp_MicroDelay(int x) {
266
 
267
}
268
*/
269
 

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