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phoenix |
/************************************************************************/
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/* */
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/* Title : SX Shared Memory Window Structure */
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/* */
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/* Author : N.P.Vassallo */
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/* */
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/* Creation : 16th March 1998 */
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/* */
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/* Version : 3.0.0 */
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/* */
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/* Copyright : (c) Specialix International Ltd. 1998 */
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/* */
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/* Description : Prototypes, structures and definitions */
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/* describing the SX/SI/XIO cards shared */
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/* memory window structure: */
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/* SXCARD */
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/* SXMODULE */
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/* SXCHANNEL */
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/* */
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/************************************************************************/
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/* History...
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3.0.0 16/03/98 NPV Creation. (based on STRUCT.H)
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*/
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#ifndef _sxwindow_h /* If SXWINDOW.H not already defined */
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#define _sxwindow_h 1
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/*****************************************************************************
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*************************** ***************************
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*************************** Common Definitions ***************************
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*************************** ***************************
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*****************************************************************************/
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typedef struct _SXCARD *PSXCARD; /* SXCARD structure pointer */
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typedef struct _SXMODULE *PMOD; /* SXMODULE structure pointer */
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typedef struct _SXCHANNEL *PCHAN; /* SXCHANNEL structure pointer */
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/*****************************************************************************
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********************************* *********************************
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********************************* SXCARD *********************************
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********************************* *********************************
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*****************************************************************************/
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typedef struct _SXCARD
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{
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BYTE cc_init_status; /* 0x00 Initialisation status */
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BYTE cc_mem_size; /* 0x01 Size of memory on card */
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WORD cc_int_count; /* 0x02 Interrupt count */
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WORD cc_revision; /* 0x04 Download code revision */
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BYTE cc_isr_count; /* 0x06 Count when ISR is run */
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BYTE cc_main_count; /* 0x07 Count when main loop is run */
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WORD cc_int_pending; /* 0x08 Interrupt pending */
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WORD cc_poll_count; /* 0x0A Count when poll is run */
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BYTE cc_int_set_count; /* 0x0C Count when host interrupt is set */
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BYTE cc_rfu[0x80 - 0x0D]; /* 0x0D Pad structure to 128 bytes (0x80) */
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} SXCARD;
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/* SXCARD.cc_init_status definitions... */
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#define ADAPTERS_FOUND (BYTE)0x01
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#define NO_ADAPTERS_FOUND (BYTE)0xFF
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/* SXCARD.cc_mem_size definitions... */
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#define SX_MEMORY_SIZE (BYTE)0x40
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/* SXCARD.cc_int_count definitions... */
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#define INT_COUNT_DEFAULT 100 /* Hz */
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/*****************************************************************************
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******************************** ********************************
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******************************** SXMODULE ********************************
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******************************** ********************************
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*****************************************************************************/
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#define TOP_POINTER(a) ((a)|0x8000) /* Sets top bit of word */
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#define UNTOP_POINTER(a) ((a)&~0x8000) /* Clears top bit of word */
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typedef struct _SXMODULE
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{
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WORD mc_next; /* 0x00 Next module "pointer" (ORed with 0x8000) */
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BYTE mc_type; /* 0x02 Type of TA in terms of number of channels */
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BYTE mc_mod_no; /* 0x03 Module number on SI bus cable (0 closest to card) */
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BYTE mc_dtr; /* 0x04 Private DTR copy (TA only) */
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BYTE mc_rfu1; /* 0x05 Reserved */
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WORD mc_uart; /* 0x06 UART base address for this module */
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BYTE mc_chip; /* 0x08 Chip type / number of ports */
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BYTE mc_current_uart; /* 0x09 Current uart selected for this module */
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#ifdef DOWNLOAD
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PCHAN mc_chan_pointer[8]; /* 0x0A Pointer to each channel structure */
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#else
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WORD mc_chan_pointer[8]; /* 0x0A Define as WORD if not compiling into download */
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#endif
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WORD mc_rfu2; /* 0x1A Reserved */
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BYTE mc_opens1; /* 0x1C Number of open ports on first four ports on MTA/SXDC */
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BYTE mc_opens2; /* 0x1D Number of open ports on second four ports on MTA/SXDC */
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BYTE mc_mods; /* 0x1E Types of connector module attached to MTA/SXDC */
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BYTE mc_rev1; /* 0x1F Revision of first CD1400 on MTA/SXDC */
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BYTE mc_rev2; /* 0x20 Revision of second CD1400 on MTA/SXDC */
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BYTE mc_mtaasic_rev; /* 0x21 Revision of MTA ASIC 1..4 -> A, B, C, D */
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BYTE mc_rfu3[0x100 - 0x22]; /* 0x22 Pad structure to 256 bytes (0x100) */
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} SXMODULE;
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/* SXMODULE.mc_type definitions... */
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#define FOUR_PORTS (BYTE)4
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#define EIGHT_PORTS (BYTE)8
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/* SXMODULE.mc_chip definitions... */
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#define CHIP_MASK 0xF0
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#define TA (BYTE)0
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#define TA4 (TA | FOUR_PORTS)
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#define TA8 (TA | EIGHT_PORTS)
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#define TA4_ASIC (BYTE)0x0A
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#define TA8_ASIC (BYTE)0x0B
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#define MTA_CD1400 (BYTE)0x28
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#define SXDC (BYTE)0x48
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/* SXMODULE.mc_mods definitions... */
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#define MOD_RS232DB25 0x00 /* RS232 DB25 (socket/plug) */
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#define MOD_RS232RJ45 0x01 /* RS232 RJ45 (shielded/opto-isolated) */
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#define MOD_RESERVED_2 0x02 /* Reserved (RS485) */
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#define MOD_RS422DB25 0x03 /* RS422 DB25 Socket */
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#define MOD_RESERVED_4 0x04 /* Reserved */
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#define MOD_PARALLEL 0x05 /* Parallel */
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#define MOD_RESERVED_6 0x06 /* Reserved (RS423) */
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#define MOD_RESERVED_7 0x07 /* Reserved */
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#define MOD_2_RS232DB25 0x08 /* Rev 2.0 RS232 DB25 (socket/plug) */
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#define MOD_2_RS232RJ45 0x09 /* Rev 2.0 RS232 RJ45 */
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#define MOD_RESERVED_A 0x0A /* Rev 2.0 Reserved */
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#define MOD_2_RS422DB25 0x0B /* Rev 2.0 RS422 DB25 */
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#define MOD_RESERVED_C 0x0C /* Rev 2.0 Reserved */
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#define MOD_2_PARALLEL 0x0D /* Rev 2.0 Parallel */
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#define MOD_RESERVED_E 0x0E /* Rev 2.0 Reserved */
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#define MOD_BLANK 0x0F /* Blank Panel */
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/*****************************************************************************
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******************************** *******************************
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******************************** SXCHANNEL *******************************
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******************************** *******************************
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*****************************************************************************/
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#define TX_BUFF_OFFSET 0x60 /* Transmit buffer offset in channel structure */
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#define BUFF_POINTER(a) (((a)+TX_BUFF_OFFSET)|0x8000)
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#define UNBUFF_POINTER(a) (jet_channel*)(((a)&~0x8000)-TX_BUFF_OFFSET)
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#define BUFFER_SIZE 256
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#define HIGH_WATER ((BUFFER_SIZE / 4) * 3)
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#define LOW_WATER (BUFFER_SIZE / 4)
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typedef struct _SXCHANNEL
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{
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WORD next_item; /* 0x00 Offset from window base of next channels hi_txbuf (ORred with 0x8000) */
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WORD addr_uart; /* 0x02 INTERNAL pointer to uart address. Includes FASTPATH bit */
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WORD module; /* 0x04 Offset from window base of parent SXMODULE structure */
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BYTE type; /* 0x06 Chip type / number of ports (copy of mc_chip) */
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BYTE chan_number; /* 0x07 Channel number on the TA/MTA/SXDC */
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WORD xc_status; /* 0x08 Flow control and I/O status */
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BYTE hi_rxipos; /* 0x0A Receive buffer input index */
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BYTE hi_rxopos; /* 0x0B Receive buffer output index */
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BYTE hi_txopos; /* 0x0C Transmit buffer output index */
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BYTE hi_txipos; /* 0x0D Transmit buffer input index */
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BYTE hi_hstat; /* 0x0E Command register */
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BYTE dtr_bit; /* 0x0F INTERNAL DTR control byte (TA only) */
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BYTE txon; /* 0x10 INTERNAL copy of hi_txon */
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BYTE txoff; /* 0x11 INTERNAL copy of hi_txoff */
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BYTE rxon; /* 0x12 INTERNAL copy of hi_rxon */
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BYTE rxoff; /* 0x13 INTERNAL copy of hi_rxoff */
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BYTE hi_mr1; /* 0x14 Mode Register 1 (databits,parity,RTS rx flow)*/
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BYTE hi_mr2; /* 0x15 Mode Register 2 (stopbits,local,CTS tx flow)*/
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BYTE hi_csr; /* 0x16 Clock Select Register (baud rate) */
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BYTE hi_op; /* 0x17 Modem Output Signal */
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BYTE hi_ip; /* 0x18 Modem Input Signal */
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BYTE hi_state; /* 0x19 Channel status */
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BYTE hi_prtcl; /* 0x1A Channel protocol (flow control) */
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BYTE hi_txon; /* 0x1B Transmit XON character */
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BYTE hi_txoff; /* 0x1C Transmit XOFF character */
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BYTE hi_rxon; /* 0x1D Receive XON character */
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BYTE hi_rxoff; /* 0x1E Receive XOFF character */
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BYTE close_prev; /* 0x1F INTERNAL channel previously closed flag */
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BYTE hi_break; /* 0x20 Break and error control */
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BYTE break_state; /* 0x21 INTERNAL copy of hi_break */
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BYTE hi_mask; /* 0x22 Mask for received data */
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BYTE mask; /* 0x23 INTERNAL copy of hi_mask */
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BYTE mod_type; /* 0x24 MTA/SXDC hardware module type */
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BYTE ccr_state; /* 0x25 INTERNAL MTA/SXDC state of CCR register */
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BYTE ip_mask; /* 0x26 Input handshake mask */
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BYTE hi_parallel; /* 0x27 Parallel port flag */
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BYTE par_error; /* 0x28 Error code for parallel loopback test */
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BYTE any_sent; /* 0x29 INTERNAL data sent flag */
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BYTE asic_txfifo_size; /* 0x2A INTERNAL SXDC transmit FIFO size */
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BYTE rfu1[2]; /* 0x2B Reserved */
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BYTE csr; /* 0x2D INTERNAL copy of hi_csr */
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#ifdef DOWNLOAD
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PCHAN nextp; /* 0x2E Offset from window base of next channel structure */
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#else
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WORD nextp; /* 0x2E Define as WORD if not compiling into download */
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#endif
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BYTE prtcl; /* 0x30 INTERNAL copy of hi_prtcl */
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BYTE mr1; /* 0x31 INTERNAL copy of hi_mr1 */
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BYTE mr2; /* 0x32 INTERNAL copy of hi_mr2 */
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BYTE hi_txbaud; /* 0x33 Extended transmit baud rate (SXDC only if((hi_csr&0x0F)==0x0F) */
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BYTE hi_rxbaud; /* 0x34 Extended receive baud rate (SXDC only if((hi_csr&0xF0)==0xF0) */
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BYTE txbreak_state; /* 0x35 INTERNAL MTA/SXDC transmit break state */
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BYTE txbaud; /* 0x36 INTERNAL copy of hi_txbaud */
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BYTE rxbaud; /* 0x37 INTERNAL copy of hi_rxbaud */
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WORD err_framing; /* 0x38 Count of receive framing errors */
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WORD err_parity; /* 0x3A Count of receive parity errors */
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WORD err_overrun; /* 0x3C Count of receive overrun errors */
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WORD err_overflow; /* 0x3E Count of receive buffer overflow errors */
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BYTE rfu2[TX_BUFF_OFFSET - 0x40]; /* 0x40 Reserved until hi_txbuf */
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BYTE hi_txbuf[BUFFER_SIZE]; /* 0x060 Transmit buffer */
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BYTE hi_rxbuf[BUFFER_SIZE]; /* 0x160 Receive buffer */
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BYTE rfu3[0x300 - 0x260]; /* 0x260 Reserved until 768 bytes (0x300) */
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} SXCHANNEL;
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/* SXCHANNEL.addr_uart definitions... */
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#define FASTPATH 0x1000 /* Set to indicate fast rx/tx processing (TA only) */
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/* SXCHANNEL.xc_status definitions... */
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#define X_TANY 0x0001 /* XON is any character (TA only) */
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#define X_TION 0x0001 /* Tx interrupts on (MTA only) */
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#define X_TXEN 0x0002 /* Tx XON/XOFF enabled (TA only) */
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#define X_RTSEN 0x0002 /* RTS FLOW enabled (MTA only) */
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#define X_TXRC 0x0004 /* XOFF received (TA only) */
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#define X_RTSLOW 0x0004 /* RTS dropped (MTA only) */
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#define X_RXEN 0x0008 /* Rx XON/XOFF enabled */
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#define X_ANYXO 0x0010 /* XOFF pending/sent or RTS dropped */
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#define X_RXSE 0x0020 /* Rx XOFF sent */
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#define X_NPEND 0x0040 /* Rx XON pending or XOFF pending */
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#define X_FPEND 0x0080 /* Rx XOFF pending */
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#define C_CRSE 0x0100 /* Carriage return sent (TA only) */
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#define C_TEMR 0x0100 /* Tx empty requested (MTA only) */
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#define C_TEMA 0x0200 /* Tx empty acked (MTA only) */
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#define C_ANYP 0x0200 /* Any protocol bar tx XON/XOFF (TA only) */
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#define C_EN 0x0400 /* Cooking enabled (on MTA means port is also || */
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#define C_HIGH 0x0800 /* Buffer previously hit high water */
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#define C_CTSEN 0x1000 /* CTS automatic flow-control enabled */
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#define C_DCDEN 0x2000 /* DCD/DTR checking enabled */
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#define C_BREAK 0x4000 /* Break detected */
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#define C_RTSEN 0x8000 /* RTS automatic flow control enabled (MTA only) */
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#define C_PARITY 0x8000 /* Parity checking enabled (TA only) */
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/* SXCHANNEL.hi_hstat definitions... */
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#define HS_IDLE_OPEN 0x00 /* Channel open state */
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#define HS_LOPEN 0x02 /* Local open command (no modem monitoring) */
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#define HS_MOPEN 0x04 /* Modem open command (wait for DCD signal) */
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#define HS_IDLE_MPEND 0x06 /* Waiting for DCD signal state */
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#define HS_CONFIG 0x08 /* Configuration command */
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#define HS_CLOSE 0x0A /* Close command */
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#define HS_START 0x0C /* Start transmit break command */
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#define HS_STOP 0x0E /* Stop transmit break command */
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#define HS_IDLE_CLOSED 0x10 /* Closed channel state */
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#define HS_IDLE_BREAK 0x12 /* Transmit break state */
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#define HS_FORCE_CLOSED 0x14 /* Force close command */
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#define HS_RESUME 0x16 /* Clear pending XOFF command */
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#define HS_WFLUSH 0x18 /* Flush transmit buffer command */
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#define HS_RFLUSH 0x1A /* Flush receive buffer command */
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#define HS_SUSPEND 0x1C /* Suspend output command (like XOFF received) */
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#define PARALLEL 0x1E /* Parallel port loopback test command (Diagnostics Only) */
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#define ENABLE_RX_INTS 0x20 /* Enable receive interrupts command (Diagnostics Only) */
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#define ENABLE_TX_INTS 0x22 /* Enable transmit interrupts command (Diagnostics Only) */
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#define ENABLE_MDM_INTS 0x24 /* Enable modem interrupts command (Diagnostics Only) */
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#define DISABLE_INTS 0x26 /* Disable interrupts command (Diagnostics Only) */
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/* SXCHANNEL.hi_mr1 definitions... */
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#define MR1_BITS 0x03 /* Data bits mask */
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#define MR1_5_BITS 0x00 /* 5 data bits */
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#define MR1_6_BITS 0x01 /* 6 data bits */
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#define MR1_7_BITS 0x02 /* 7 data bits */
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#define MR1_8_BITS 0x03 /* 8 data bits */
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#define MR1_PARITY 0x1C /* Parity mask */
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#define MR1_ODD 0x04 /* Odd parity */
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#define MR1_EVEN 0x00 /* Even parity */
|
| 277 |
|
|
#define MR1_WITH 0x00 /* Parity enabled */
|
| 278 |
|
|
#define MR1_FORCE 0x08 /* Force parity */
|
| 279 |
|
|
#define MR1_NONE 0x10 /* No parity */
|
| 280 |
|
|
#define MR1_NOPARITY MR1_NONE /* No parity */
|
| 281 |
|
|
#define MR1_ODDPARITY (MR1_WITH|MR1_ODD) /* Odd parity */
|
| 282 |
|
|
#define MR1_EVENPARITY (MR1_WITH|MR1_EVEN) /* Even parity */
|
| 283 |
|
|
#define MR1_MARKPARITY (MR1_FORCE|MR1_ODD) /* Mark parity */
|
| 284 |
|
|
#define MR1_SPACEPARITY (MR1_FORCE|MR1_EVEN) /* Space parity */
|
| 285 |
|
|
#define MR1_RTS_RXFLOW 0x80 /* RTS receive flow control */
|
| 286 |
|
|
|
| 287 |
|
|
/* SXCHANNEL.hi_mr2 definitions... */
|
| 288 |
|
|
#define MR2_STOP 0x0F /* Stop bits mask */
|
| 289 |
|
|
#define MR2_1_STOP 0x07 /* 1 stop bit */
|
| 290 |
|
|
#define MR2_2_STOP 0x0F /* 2 stop bits */
|
| 291 |
|
|
#define MR2_CTS_TXFLOW 0x10 /* CTS transmit flow control */
|
| 292 |
|
|
#define MR2_RTS_TOGGLE 0x20 /* RTS toggle on transmit */
|
| 293 |
|
|
#define MR2_NORMAL 0x00 /* Normal mode */
|
| 294 |
|
|
#define MR2_AUTO 0x40 /* Auto-echo mode (TA only) */
|
| 295 |
|
|
#define MR2_LOCAL 0x80 /* Local echo mode */
|
| 296 |
|
|
#define MR2_REMOTE 0xC0 /* Remote echo mode (TA only) */
|
| 297 |
|
|
|
| 298 |
|
|
/* SXCHANNEL.hi_csr definitions... */
|
| 299 |
|
|
#define CSR_75 0x0 /* 75 baud */
|
| 300 |
|
|
#define CSR_110 0x1 /* 110 baud (TA), 115200 (MTA/SXDC) */
|
| 301 |
|
|
#define CSR_38400 0x2 /* 38400 baud */
|
| 302 |
|
|
#define CSR_150 0x3 /* 150 baud */
|
| 303 |
|
|
#define CSR_300 0x4 /* 300 baud */
|
| 304 |
|
|
#define CSR_600 0x5 /* 600 baud */
|
| 305 |
|
|
#define CSR_1200 0x6 /* 1200 baud */
|
| 306 |
|
|
#define CSR_2000 0x7 /* 2000 baud */
|
| 307 |
|
|
#define CSR_2400 0x8 /* 2400 baud */
|
| 308 |
|
|
#define CSR_4800 0x9 /* 4800 baud */
|
| 309 |
|
|
#define CSR_1800 0xA /* 1800 baud */
|
| 310 |
|
|
#define CSR_9600 0xB /* 9600 baud */
|
| 311 |
|
|
#define CSR_19200 0xC /* 19200 baud */
|
| 312 |
|
|
#define CSR_57600 0xD /* 57600 baud */
|
| 313 |
|
|
#define CSR_EXTBAUD 0xF /* Extended baud rate (hi_txbaud/hi_rxbaud) */
|
| 314 |
|
|
|
| 315 |
|
|
/* SXCHANNEL.hi_op definitions... */
|
| 316 |
|
|
#define OP_RTS 0x01 /* RTS modem output signal */
|
| 317 |
|
|
#define OP_DTR 0x02 /* DTR modem output signal */
|
| 318 |
|
|
|
| 319 |
|
|
/* SXCHANNEL.hi_ip definitions... */
|
| 320 |
|
|
#define IP_CTS 0x02 /* CTS modem input signal */
|
| 321 |
|
|
#define IP_DCD 0x04 /* DCD modem input signal */
|
| 322 |
|
|
#define IP_DSR 0x20 /* DTR modem input signal */
|
| 323 |
|
|
#define IP_RI 0x40 /* RI modem input signal */
|
| 324 |
|
|
|
| 325 |
|
|
/* SXCHANNEL.hi_state definitions... */
|
| 326 |
|
|
#define ST_BREAK 0x01 /* Break received (clear with config) */
|
| 327 |
|
|
#define ST_DCD 0x02 /* DCD signal changed state */
|
| 328 |
|
|
|
| 329 |
|
|
/* SXCHANNEL.hi_prtcl definitions... */
|
| 330 |
|
|
#define SP_TANY 0x01 /* Transmit XON/XANY (if SP_TXEN enabled) */
|
| 331 |
|
|
#define SP_TXEN 0x02 /* Transmit XON/XOFF flow control */
|
| 332 |
|
|
#define SP_CEN 0x04 /* Cooking enabled */
|
| 333 |
|
|
#define SP_RXEN 0x08 /* Rx XON/XOFF enabled */
|
| 334 |
|
|
#define SP_DCEN 0x20 /* DCD / DTR check */
|
| 335 |
|
|
#define SP_DTR_RXFLOW 0x40 /* DTR receive flow control */
|
| 336 |
|
|
#define SP_PAEN 0x80 /* Parity checking enabled */
|
| 337 |
|
|
|
| 338 |
|
|
/* SXCHANNEL.hi_break definitions... */
|
| 339 |
|
|
#define BR_IGN 0x01 /* Ignore any received breaks */
|
| 340 |
|
|
#define BR_INT 0x02 /* Interrupt on received break */
|
| 341 |
|
|
#define BR_PARMRK 0x04 /* Enable parmrk parity error processing */
|
| 342 |
|
|
#define BR_PARIGN 0x08 /* Ignore chars with parity errors */
|
| 343 |
|
|
#define BR_ERRINT 0x80 /* Treat parity/framing/overrun errors as exceptions */
|
| 344 |
|
|
|
| 345 |
|
|
/* SXCHANNEL.par_error definitions.. */
|
| 346 |
|
|
#define DIAG_IRQ_RX 0x01 /* Indicate serial receive interrupt (diags only) */
|
| 347 |
|
|
#define DIAG_IRQ_TX 0x02 /* Indicate serial transmit interrupt (diags only) */
|
| 348 |
|
|
#define DIAG_IRQ_MD 0x04 /* Indicate serial modem interrupt (diags only) */
|
| 349 |
|
|
|
| 350 |
|
|
/* SXCHANNEL.hi_txbaud/hi_rxbaud definitions... (SXDC only) */
|
| 351 |
|
|
#define BAUD_75 0x00 /* 75 baud */
|
| 352 |
|
|
#define BAUD_115200 0x01 /* 115200 baud */
|
| 353 |
|
|
#define BAUD_38400 0x02 /* 38400 baud */
|
| 354 |
|
|
#define BAUD_150 0x03 /* 150 baud */
|
| 355 |
|
|
#define BAUD_300 0x04 /* 300 baud */
|
| 356 |
|
|
#define BAUD_600 0x05 /* 600 baud */
|
| 357 |
|
|
#define BAUD_1200 0x06 /* 1200 baud */
|
| 358 |
|
|
#define BAUD_2000 0x07 /* 2000 baud */
|
| 359 |
|
|
#define BAUD_2400 0x08 /* 2400 baud */
|
| 360 |
|
|
#define BAUD_4800 0x09 /* 4800 baud */
|
| 361 |
|
|
#define BAUD_1800 0x0A /* 1800 baud */
|
| 362 |
|
|
#define BAUD_9600 0x0B /* 9600 baud */
|
| 363 |
|
|
#define BAUD_19200 0x0C /* 19200 baud */
|
| 364 |
|
|
#define BAUD_57600 0x0D /* 57600 baud */
|
| 365 |
|
|
#define BAUD_230400 0x0E /* 230400 baud */
|
| 366 |
|
|
#define BAUD_460800 0x0F /* 460800 baud */
|
| 367 |
|
|
#define BAUD_921600 0x10 /* 921600 baud */
|
| 368 |
|
|
#define BAUD_50 0x11 /* 50 baud */
|
| 369 |
|
|
#define BAUD_110 0x12 /* 110 baud */
|
| 370 |
|
|
#define BAUD_134_5 0x13 /* 134.5 baud */
|
| 371 |
|
|
#define BAUD_200 0x14 /* 200 baud */
|
| 372 |
|
|
#define BAUD_7200 0x15 /* 7200 baud */
|
| 373 |
|
|
#define BAUD_56000 0x16 /* 56000 baud */
|
| 374 |
|
|
#define BAUD_64000 0x17 /* 64000 baud */
|
| 375 |
|
|
#define BAUD_76800 0x18 /* 76800 baud */
|
| 376 |
|
|
#define BAUD_128000 0x19 /* 128000 baud */
|
| 377 |
|
|
#define BAUD_150000 0x1A /* 150000 baud */
|
| 378 |
|
|
#define BAUD_14400 0x1B /* 14400 baud */
|
| 379 |
|
|
#define BAUD_256000 0x1C /* 256000 baud */
|
| 380 |
|
|
#define BAUD_28800 0x1D /* 28800 baud */
|
| 381 |
|
|
|
| 382 |
|
|
/* SXCHANNEL.txbreak_state definiions... */
|
| 383 |
|
|
#define TXBREAK_OFF 0 /* Not sending break */
|
| 384 |
|
|
#define TXBREAK_START 1 /* Begin sending break */
|
| 385 |
|
|
#define TXBREAK_START1 2 /* Begin sending break, part 1 */
|
| 386 |
|
|
#define TXBREAK_ON 3 /* Sending break */
|
| 387 |
|
|
#define TXBREAK_STOP 4 /* Stop sending break */
|
| 388 |
|
|
#define TXBREAK_STOP1 5 /* Stop sending break, part 1 */
|
| 389 |
|
|
|
| 390 |
|
|
#endif /* _sxwindow_h */
|
| 391 |
|
|
|
| 392 |
|
|
/* End of SXWINDOW.H */
|
| 393 |
|
|
|
