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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [ide/] [pci/] [it8172.c] - Blame information for rev 1765

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/*
 *
 * BRIEF MODULE DESCRIPTION
 *      IT8172 IDE controller support
 *
 * Copyright 2000 MontaVista Software Inc.
 * Author: MontaVista Software, Inc.
 *              stevel@mvista.com or source@mvista.com
 *
 *  This program is free software; you can redistribute  it and/or modify it
 *  under  the terms of  the GNU General  Public License as published by the
 *  Free Software Foundation;  either version 2 of the  License, or (at your
 *  option) any later version.
 *
 *  THIS  SOFTWARE  IS PROVIDED   ``AS  IS'' AND   ANY  EXPRESS OR IMPLIED
 *  WARRANTIES,   INCLUDING, BUT NOT  LIMITED  TO, THE IMPLIED WARRANTIES OF
 *  MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.  IN
 *  NO  EVENT  SHALL   THE AUTHOR  BE    LIABLE FOR ANY   DIRECT, INDIRECT,
 *  INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT
 *  NOT LIMITED   TO, PROCUREMENT OF  SUBSTITUTE GOODS  OR SERVICES; LOSS OF
 *  USE, DATA,  OR PROFITS; OR  BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON
 *  ANY THEORY OF LIABILITY, WHETHER IN  CONTRACT, STRICT LIABILITY, OR TORT
 *  (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF
 *  THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 *
 *  You should have received a copy of the  GNU General Public License along
 *  with this program; if not, write  to the Free Software Foundation, Inc.,
 *  675 Mass Ave, Cambridge, MA 02139, USA.
 */
 
#include <linux/config.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/kernel.h>
#include <linux/ioport.h>
#include <linux/pci.h>
#include <linux/hdreg.h>
#include <linux/ide.h>
#include <linux/delay.h>
#include <linux/init.h>
 
#include <asm/io.h>
#include <asm/it8172/it8172_int.h>
 
#include "ide_modes.h"
#include "it8172.h"
 
/*
 * Prototypes
 */
static u8 it8172_ratemask (ide_drive_t *drive)
{
        return 1;
}
 
static void it8172_tune_drive (ide_drive_t *drive, u8 pio)
{
        ide_hwif_t *hwif        = HWIF(drive);
        struct pci_dev *dev     = hwif->pci_dev;
        int is_slave            = (hwif->drives[1] == drive);
        unsigned long flags;
        u16 drive_enables;
        u32 drive_timing;
 
        pio = ide_get_best_pio_mode(drive, pio, 4, NULL);
        spin_lock_irqsave(&ide_lock, flags);
        pci_read_config_word(dev, 0x40, &drive_enables);
        pci_read_config_dword(dev, 0x44, &drive_timing);
 
        /*
         * FIX! The DIOR/DIOW pulse width and recovery times in port 0x44
         * are being left at the default values of 8 PCI clocks (242 nsec
         * for a 33 MHz clock). These can be safely shortened at higher
         * PIO modes. The DIOR/DIOW pulse width and recovery times only
         * apply to PIO modes, not to the DMA modes.
         */
 
        /*
         * Enable port 0x44. The IT8172G spec is confused; it calls
         * this register the "Slave IDE Timing Register", but in fact,
         * it controls timing for both master and slave drives.
         */
        drive_enables |= 0x4000;
 
        if (is_slave) {
                drive_enables &= 0xc006;
                if (pio > 1)
                        /* enable prefetch and IORDY sample-point */
                        drive_enables |= 0x0060;
        } else {
                drive_enables &= 0xc060;
                if (pio > 1)
                        /* enable prefetch and IORDY sample-point */
                        drive_enables |= 0x0006;
        }
 
        pci_write_config_word(dev, 0x40, drive_enables);
        spin_unlock_irqrestore(&ide_lock, flags)
}
 
static u8 it8172_dma_2_pio (u8 xfer_rate)
{
        switch(xfer_rate) {
                case XFER_UDMA_5:
                case XFER_UDMA_4:
                case XFER_UDMA_3:
                case XFER_UDMA_2:
                case XFER_UDMA_1:
                case XFER_UDMA_0:
                case XFER_MW_DMA_2:
                case XFER_PIO_4:
                        return 4;
                case XFER_MW_DMA_1:
                case XFER_PIO_3:
                        return 3;
                case XFER_SW_DMA_2:
                case XFER_PIO_2:
                        return 2;
                case XFER_MW_DMA_0:
                case XFER_SW_DMA_1:
                case XFER_SW_DMA_0:
                case XFER_PIO_1:
                case XFER_PIO_0:
                case XFER_PIO_SLOW:
                default:
                        return 0;
        }
}
 
static int it8172_tune_chipset (ide_drive_t *drive, u8 xferspeed)
{
        ide_hwif_t *hwif        = HWIF(drive);
        struct pci_dev *dev     = hwif->pci_dev;
        u8 speed        = ide_rate_filter(it8172_ratemask(drive), xferspeed);
        int a_speed             = 3 << (drive->dn * 4);
        int u_flag              = 1 << drive->dn;
        int u_speed             = 0;
        u8 reg48, reg4a;
 
        pci_read_config_byte(dev, 0x48, &reg48);
        pci_read_config_byte(dev, 0x4a, &reg4a);
 
    /*
     * Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec
     * at 33 MHz PCI clock) seems to cause BadCRC errors during DMA
     * transfers on some drives, even though both numbers meet the minimum
     * ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.
     * So the faster times are just commented out here. The good news is
     * that the slower cycle time has very little affect on transfer
     * performance.
     */
 
        switch(speed) {
                case XFER_UDMA_4:
                case XFER_UDMA_2:       //u_speed = 2 << (drive->dn * 4); break;
                case XFER_UDMA_5:
                case XFER_UDMA_3:
                case XFER_UDMA_1:       //u_speed = 1 << (drive->dn * 4); break;
                case XFER_UDMA_0:       u_speed = 0 << (drive->dn * 4); break;
                case XFER_MW_DMA_2:
                case XFER_MW_DMA_1:
                case XFER_MW_DMA_0:
                case XFER_SW_DMA_2:     break;
                case XFER_PIO_4:
                case XFER_PIO_3:
                case XFER_PIO_2:
                case XFER_PIO_0:        break;
                default:                return -1;
        }
 
        if (speed >= XFER_UDMA_0) {
                pci_write_config_byte(dev, 0x48, reg48 | u_flag);
                reg4a &= ~a_speed;
                pci_write_config_byte(dev, 0x4a, reg4a | u_speed);
        } else {
                pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);
                pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);
        }
 
        it8172_tune_drive(drive, it8172_dma_2_pio(speed));
        return (ide_config_drive_speed(drive, speed));
}
 
static int it8172_config_chipset_for_dma (ide_drive_t *drive)
{
        u8 speed = ide_dma_speed(drive, it8172_ratemask(drive));
 
        if (!(speed)) {
                u8 tspeed = ide_get_best_pio_mode(drive, 255, 4, NULL);
                speed = it8172_dma_2_pio(XFER_PIO_0 + tspeed);
        }
 
        (void) it8172_tune_chipset(drive, speed);
        return ide_dma_enable(drive);
}
 
static int it8172_config_drive_xfer_rate (ide_drive_t *drive)
{
        ide_hwif_t *hwif        = HWIF(drive);
        struct hd_driveid *id   = drive->id;
 
        drive->init_speed = 0;
 
        if ((id->capability & 1) && drive->autodma) {
                /* Consult the list of known "bad" drives */
                if (hwif->ide_dma_bad_drive(drive))
                        goto fast_ata_pio;
                if (id->field_valid & 4) {
                        if (id->dma_ultra & hwif->ultra_mask) {
                                /* Force if Capable UltraDMA */
                                int dma = it8172_config_chipset_for_dma(drive);
                                if ((id->field_valid & 2) && !dma)
                                        goto try_dma_modes;
                        }
                } else if (id->field_valid & 2) {
try_dma_modes:
                        if ((id->dma_mword & hwif->mwdma_mask) ||
                            (id->dma_1word & hwif->swdma_mask)) {
                                /* Force if Capable regular DMA modes */
                                if (!it8172_config_chipset_for_dma(drive))
                                        goto no_dma_set;
                        }
                } else if (hwif->ide_dma_good_drive(drive) &&
                           (id->eide_dma_time < 150)) {
                        /* Consult the list of known "good" drives */
                        if (!it8172_config_chipset_for_dma(drive))
                                goto no_dma_set;
                } else {
                        goto fast_ata_pio;
                }
        } else if ((id->capability & 8) || (id->field_valid & 2)) {
fast_ata_pio:
no_dma_set:
                it8172_tune_drive(drive, 5);
                return hwif->ide_dma_off_quietly(drive);
        }
        return hwif->ide_dma_on(drive);
}
 
static unsigned int __init init_chipset_it8172 (struct pci_dev *dev, const char *name)
{
        unsigned char progif;
 
        /*
         * Place both IDE interfaces into PCI "native" mode
         */
        pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);
        pci_write_config_byte(dev, PCI_CLASS_PROG, progif | 0x05);
 
        return IT8172_IDE_IRQ;
}
 
 
static void __init init_hwif_it8172 (ide_hwif_t *hwif)
{
        struct pci_dev* dev = hwif->pci_dev;
        unsigned long cmdBase, ctrlBase;
 
        hwif->autodma = 0;
        hwif->tuneproc = &it8172_tune_drive;
        hwif->speedproc = &it8172_tune_chipset;
 
        cmdBase = dev->resource[0].start;
        ctrlBase = dev->resource[1].start;
 
        ide_init_hwif_ports(&hwif->hw, cmdBase, ctrlBase | 2, NULL);
        memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));
        hwif->noprobe = 0;
 
        if (!hwif->dma_base) {
                hwif->drives[0].autotune = 1;
                hwif->drives[1].autotune = 1;
                return;
        }
 
        hwif->atapi_dma = 1;
        hwif->ultra_mask = 0x07;
        hwif->mwdma_mask = 0x06;
        hwif->swdma_mask = 0x04;
 
        hwif->ide_dma_check = &it8172_config_drive_xfer_rate;
        if (!noautodma)
                hwif->autodma = 1;
        hwif->drives[0].autodma = hwif->autodma;
        hwif->drives[1].autodma = hwif->autodma;
}
 
static void __init init_dma_it8172 (ide_hwif_t *hwif, unsigned long dmabase)
{
        ide_setup_dma(hwif, dmabase, 8);
}
 
extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
 
static int __devinit it8172_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
        ide_pci_device_t *d = &it8172_chipsets[id->driver_data];
        if ((!(PCI_FUNC(dev->devfn) & 1) ||
            (!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))
                return 1; /* IT8172 is more than only a IDE controller */
        ide_setup_pci_device(dev, d);
        MOD_INC_USE_COUNT;
        return 0;
}
 
static struct pci_device_id it8172_pci_tbl[] __devinitdata = {
        { PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
        { 0, },
};
 
static struct pci_driver driver = {
        .name           = "IT8172IDE",
        .id_table       = it8172_pci_tbl,
        .probe          = it8172_init_one,
};
 
static int it8172_ide_init(void)
{
        return ide_pci_register_driver(&driver);
}
 
static void it8172_ide_exit(void)
{
        ide_pci_unregister_driver(&driver);
}
 
module_init(it8172_ide_init);
module_exit(it8172_ide_exit);
 
MODULE_AUTHOR("SteveL@mvista.com");
MODULE_DESCRIPTION("PCI driver module for ITE 8172 IDE");
MODULE_LICENSE("GPL");
 
EXPORT_NO_SYMBOLS;

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [ide/] [pci/] [it8172.c] - Blame information for rev 1765

Line No.	Rev	Author	Line
1	1275	phoenix	`/*`
2			`*`
3			`* BRIEF MODULE DESCRIPTION`
4			`* IT8172 IDE controller support`
5			`*`
6			`* Copyright 2000 MontaVista Software Inc.`
7			`* Author: MontaVista Software, Inc.`
8			`* stevel@mvista.com or source@mvista.com`
9			`*`
10			`* This program is free software; you can redistribute it and/or modify it`
11			`* under the terms of the GNU General Public License as published by the`
12			`* Free Software Foundation; either version 2 of the License, or (at your`
13			`* option) any later version.`
14			`*`
15			* THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED
16			`* WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF`
17			`* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN`
18			`* NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT,`
19			`* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT`
20			`* NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF`
21			`* USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON`
22			`* ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT`
23			`* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF`
24			`* THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.`
25			`*`
26			`* You should have received a copy of the GNU General Public License along`
27			`* with this program; if not, write to the Free Software Foundation, Inc.,`
28			`* 675 Mass Ave, Cambridge, MA 02139, USA.`
29			`*/`
30
31			`#include <linux/config.h>`
32			`#include <linux/module.h>`
33			`#include <linux/types.h>`
34			`#include <linux/kernel.h>`
35			`#include <linux/ioport.h>`
36			`#include <linux/pci.h>`
37			`#include <linux/hdreg.h>`
38			`#include <linux/ide.h>`
39			`#include <linux/delay.h>`
40			`#include <linux/init.h>`
41
42			`#include <asm/io.h>`
43			`#include <asm/it8172/it8172_int.h>`
44
45			`#include "ide_modes.h"`
46			`#include "it8172.h"`
47
48			`/*`
49			`* Prototypes`
50			`*/`
51			`static u8 it8172_ratemask (ide_drive_t *drive)`
52			`{`
53			`return 1;`
54			`}`
55
56			`static void it8172_tune_drive (ide_drive_t *drive, u8 pio)`
57			`{`
58			`ide_hwif_t *hwif = HWIF(drive);`
59			`struct pci_dev *dev = hwif->pci_dev;`
60			`int is_slave = (hwif->drives[1] == drive);`
61			`unsigned long flags;`
62			`u16 drive_enables;`
63			`u32 drive_timing;`
64
65			`pio = ide_get_best_pio_mode(drive, pio, 4, NULL);`
66			`spin_lock_irqsave(&ide_lock, flags);`
67			`pci_read_config_word(dev, 0x40, &drive_enables);`
68			`pci_read_config_dword(dev, 0x44, &drive_timing);`
69
70			`/*`
71			`* FIX! The DIOR/DIOW pulse width and recovery times in port 0x44`
72			`* are being left at the default values of 8 PCI clocks (242 nsec`
73			`* for a 33 MHz clock). These can be safely shortened at higher`
74			`* PIO modes. The DIOR/DIOW pulse width and recovery times only`
75			`* apply to PIO modes, not to the DMA modes.`
76			`*/`
77
78			`/*`
79			`* Enable port 0x44. The IT8172G spec is confused; it calls`
80			`* this register the "Slave IDE Timing Register", but in fact,`
81			`* it controls timing for both master and slave drives.`
82			`*/`
83			`drive_enables \|= 0x4000;`
84
85			`if (is_slave) {`
86			`drive_enables &= 0xc006;`
87			`if (pio > 1)`
88			`/* enable prefetch and IORDY sample-point */`
89			`drive_enables \|= 0x0060;`
90			`} else {`
91			`drive_enables &= 0xc060;`
92			`if (pio > 1)`
93			`/* enable prefetch and IORDY sample-point */`
94			`drive_enables \|= 0x0006;`
95			`}`
96
97			`pci_write_config_word(dev, 0x40, drive_enables);`
98			`spin_unlock_irqrestore(&ide_lock, flags)`
99			`}`
100
101			`static u8 it8172_dma_2_pio (u8 xfer_rate)`
102			`{`
103			`switch(xfer_rate) {`
104			`case XFER_UDMA_5:`
105			`case XFER_UDMA_4:`
106			`case XFER_UDMA_3:`
107			`case XFER_UDMA_2:`
108			`case XFER_UDMA_1:`
109			`case XFER_UDMA_0:`
110			`case XFER_MW_DMA_2:`
111			`case XFER_PIO_4:`
112			`return 4;`
113			`case XFER_MW_DMA_1:`
114			`case XFER_PIO_3:`
115			`return 3;`
116			`case XFER_SW_DMA_2:`
117			`case XFER_PIO_2:`
118			`return 2;`
119			`case XFER_MW_DMA_0:`
120			`case XFER_SW_DMA_1:`
121			`case XFER_SW_DMA_0:`
122			`case XFER_PIO_1:`
123			`case XFER_PIO_0:`
124			`case XFER_PIO_SLOW:`
125			`default:`
126			`return 0;`
127			`}`
128			`}`
129
130			`static int it8172_tune_chipset (ide_drive_t *drive, u8 xferspeed)`
131			`{`
132			`ide_hwif_t *hwif = HWIF(drive);`
133			`struct pci_dev *dev = hwif->pci_dev;`
134			`u8 speed = ide_rate_filter(it8172_ratemask(drive), xferspeed);`
135			`int a_speed = 3 << (drive->dn * 4);`
136			`int u_flag = 1 << drive->dn;`
137			`int u_speed = 0;`
138			`u8 reg48, reg4a;`
139
140			`pci_read_config_byte(dev, 0x48, &reg48);`
141			`pci_read_config_byte(dev, 0x4a, &reg4a);`
142
143			`/*`
144			`* Setting the DMA cycle time to 2 or 3 PCI clocks (60 and 91 nsec`
145			`* at 33 MHz PCI clock) seems to cause BadCRC errors during DMA`
146			`* transfers on some drives, even though both numbers meet the minimum`
147			`* ATAPI-4 spec of 73 and 54 nsec for UDMA 1 and 2 respectively.`
148			`* So the faster times are just commented out here. The good news is`
149			`* that the slower cycle time has very little affect on transfer`
150			`* performance.`
151			`*/`
152
153			`switch(speed) {`
154			`case XFER_UDMA_4:`
155			`case XFER_UDMA_2: //u_speed = 2 << (drive->dn * 4); break;`
156			`case XFER_UDMA_5:`
157			`case XFER_UDMA_3:`
158			`case XFER_UDMA_1: //u_speed = 1 << (drive->dn * 4); break;`
159			`case XFER_UDMA_0: u_speed = 0 << (drive->dn * 4); break;`
160			`case XFER_MW_DMA_2:`
161			`case XFER_MW_DMA_1:`
162			`case XFER_MW_DMA_0:`
163			`case XFER_SW_DMA_2: break;`
164			`case XFER_PIO_4:`
165			`case XFER_PIO_3:`
166			`case XFER_PIO_2:`
167			`case XFER_PIO_0: break;`
168			`default: return -1;`
169			`}`
170
171			`if (speed >= XFER_UDMA_0) {`
172			`pci_write_config_byte(dev, 0x48, reg48 \| u_flag);`
173			`reg4a &= ~a_speed;`
174			`pci_write_config_byte(dev, 0x4a, reg4a \| u_speed);`
175			`} else {`
176			`pci_write_config_byte(dev, 0x48, reg48 & ~u_flag);`
177			`pci_write_config_byte(dev, 0x4a, reg4a & ~a_speed);`
178			`}`
179
180			`it8172_tune_drive(drive, it8172_dma_2_pio(speed));`
181			`return (ide_config_drive_speed(drive, speed));`
182			`}`
183
184			`static int it8172_config_chipset_for_dma (ide_drive_t *drive)`
185			`{`
186			`u8 speed = ide_dma_speed(drive, it8172_ratemask(drive));`
187
188			`if (!(speed)) {`
189			`u8 tspeed = ide_get_best_pio_mode(drive, 255, 4, NULL);`
190			`speed = it8172_dma_2_pio(XFER_PIO_0 + tspeed);`
191			`}`
192
193			`(void) it8172_tune_chipset(drive, speed);`
194			`return ide_dma_enable(drive);`
195			`}`
196
197			`static int it8172_config_drive_xfer_rate (ide_drive_t *drive)`
198			`{`
199			`ide_hwif_t *hwif = HWIF(drive);`
200			`struct hd_driveid *id = drive->id;`
201
202			`drive->init_speed = 0;`
203
204			`if ((id->capability & 1) && drive->autodma) {`
205			`/* Consult the list of known "bad" drives */`
206			`if (hwif->ide_dma_bad_drive(drive))`
207			`goto fast_ata_pio;`
208			`if (id->field_valid & 4) {`
209			`if (id->dma_ultra & hwif->ultra_mask) {`
210			`/* Force if Capable UltraDMA */`
211			`int dma = it8172_config_chipset_for_dma(drive);`
212			`if ((id->field_valid & 2) && !dma)`
213			`goto try_dma_modes;`
214			`}`
215			`} else if (id->field_valid & 2) {`
216			`try_dma_modes:`
217			`if ((id->dma_mword & hwif->mwdma_mask) \|\|`
218			`(id->dma_1word & hwif->swdma_mask)) {`
219			`/* Force if Capable regular DMA modes */`
220			`if (!it8172_config_chipset_for_dma(drive))`
221			`goto no_dma_set;`
222			`}`
223			`} else if (hwif->ide_dma_good_drive(drive) &&`
224			`(id->eide_dma_time < 150)) {`
225			`/* Consult the list of known "good" drives */`
226			`if (!it8172_config_chipset_for_dma(drive))`
227			`goto no_dma_set;`
228			`} else {`
229			`goto fast_ata_pio;`
230			`}`
231			`} else if ((id->capability & 8) \|\| (id->field_valid & 2)) {`
232			`fast_ata_pio:`
233			`no_dma_set:`
234			`it8172_tune_drive(drive, 5);`
235			`return hwif->ide_dma_off_quietly(drive);`
236			`}`
237			`return hwif->ide_dma_on(drive);`
238			`}`
239
240			`static unsigned int __init init_chipset_it8172 (struct pci_dev dev, const char name)`
241			`{`
242			`unsigned char progif;`
243
244			`/*`
245			`* Place both IDE interfaces into PCI "native" mode`
246			`*/`
247			`pci_read_config_byte(dev, PCI_CLASS_PROG, &progif);`
248			`pci_write_config_byte(dev, PCI_CLASS_PROG, progif \| 0x05);`
249
250			`return IT8172_IDE_IRQ;`
251			`}`
252
253
254			`static void __init init_hwif_it8172 (ide_hwif_t *hwif)`
255			`{`
256			`struct pci_dev* dev = hwif->pci_dev;`
257			`unsigned long cmdBase, ctrlBase;`
258
259			`hwif->autodma = 0;`
260			`hwif->tuneproc = &it8172_tune_drive;`
261			`hwif->speedproc = &it8172_tune_chipset;`
262
263			`cmdBase = dev->resource[0].start;`
264			`ctrlBase = dev->resource[1].start;`
265
266			`ide_init_hwif_ports(&hwif->hw, cmdBase, ctrlBase \| 2, NULL);`
267			`memcpy(hwif->io_ports, hwif->hw.io_ports, sizeof(hwif->io_ports));`
268			`hwif->noprobe = 0;`
269
270			`if (!hwif->dma_base) {`
271			`hwif->drives[0].autotune = 1;`
272			`hwif->drives[1].autotune = 1;`
273			`return;`
274			`}`
275
276			`hwif->atapi_dma = 1;`
277			`hwif->ultra_mask = 0x07;`
278			`hwif->mwdma_mask = 0x06;`
279			`hwif->swdma_mask = 0x04;`
280
281			`hwif->ide_dma_check = &it8172_config_drive_xfer_rate;`
282			`if (!noautodma)`
283			`hwif->autodma = 1;`
284			`hwif->drives[0].autodma = hwif->autodma;`
285			`hwif->drives[1].autodma = hwif->autodma;`
286			`}`
287
288			`static void __init init_dma_it8172 (ide_hwif_t *hwif, unsigned long dmabase)`
289			`{`
290			`ide_setup_dma(hwif, dmabase, 8);`
291			`}`
292
293			`extern void ide_setup_pci_device(struct pci_dev , ide_pci_device_t );`
294
295			`static int __devinit it8172_init_one(struct pci_dev dev, const struct pci_device_id id)`
296			`{`
297			`ide_pci_device_t *d = &it8172_chipsets[id->driver_data];`
298			`if ((!(PCI_FUNC(dev->devfn) & 1) \|\|`
299			`(!((dev->class >> 8) == PCI_CLASS_STORAGE_IDE))))`
300			`return 1; /* IT8172 is more than only a IDE controller */`
301			`ide_setup_pci_device(dev, d);`
302			`MOD_INC_USE_COUNT;`
303			`return 0;`
304			`}`
305
306			`static struct pci_device_id it8172_pci_tbl[] __devinitdata = {`
307			`{ PCI_VENDOR_ID_ITE, PCI_DEVICE_ID_ITE_IT8172G, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},`
308			`{ 0, },`
309			`};`
310
311			`static struct pci_driver driver = {`
312			`.name = "IT8172IDE",`
313			`.id_table = it8172_pci_tbl,`
314			`.probe = it8172_init_one,`
315			`};`
316
317			`static int it8172_ide_init(void)`
318			`{`
319			`return ide_pci_register_driver(&driver);`
320			`}`
321
322			`static void it8172_ide_exit(void)`
323			`{`
324			`ide_pci_unregister_driver(&driver);`
325			`}`
326
327			`module_init(it8172_ide_init);`
328			`module_exit(it8172_ide_exit);`
329
330			`MODULE_AUTHOR("SteveL@mvista.com");`
331			`MODULE_DESCRIPTION("PCI driver module for ITE 8172 IDE");`
332			`MODULE_LICENSE("GPL");`
333
334			`EXPORT_NO_SYMBOLS;`