1 |
1275 |
phoenix |
#ifndef PDC202XX_H
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#define PDC202XX_H
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#include <linux/config.h>
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#include <linux/pci.h>
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#include <linux/ide.h>
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#define DISPLAY_PDC202XX_TIMINGS
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#ifndef SPLIT_BYTE
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#define SPLIT_BYTE(B,H,L) ((H)=(B>>4), (L)=(B-((B>>4)<<4)))
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#endif
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#define PDC202XX_DEBUG_DRIVE_INFO 0
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#define PDC202XX_DECODE_REGISTER_INFO 0
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const static char *pdc_quirk_drives[] = {
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"QUANTUM FIREBALLlct08 08",
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"QUANTUM FIREBALLP KA6.4",
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"QUANTUM FIREBALLP KA9.1",
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"QUANTUM FIREBALLP LM20.4",
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"QUANTUM FIREBALLP KX13.6",
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"QUANTUM FIREBALLP KX20.5",
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"QUANTUM FIREBALLP KX27.3",
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"QUANTUM FIREBALLP LM20.5",
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NULL
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};
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/* A Register */
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#define SYNC_ERRDY_EN 0xC0
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#define SYNC_IN 0x80 /* control bit, different for master vs. slave drives */
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#define ERRDY_EN 0x40 /* control bit, different for master vs. slave drives */
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#define IORDY_EN 0x20 /* PIO: IOREADY */
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#define PREFETCH_EN 0x10 /* PIO: PREFETCH */
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#define PA3 0x08 /* PIO"A" timing */
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#define PA2 0x04 /* PIO"A" timing */
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#define PA1 0x02 /* PIO"A" timing */
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#define PA0 0x01 /* PIO"A" timing */
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/* B Register */
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#define MB2 0x80 /* DMA"B" timing */
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#define MB1 0x40 /* DMA"B" timing */
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#define MB0 0x20 /* DMA"B" timing */
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#define PB4 0x10 /* PIO_FORCE 1:0 */
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#define PB3 0x08 /* PIO"B" timing */ /* PIO flow Control mode */
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#define PB2 0x04 /* PIO"B" timing */ /* PIO 4 */
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#define PB1 0x02 /* PIO"B" timing */ /* PIO 3 half */
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#define PB0 0x01 /* PIO"B" timing */ /* PIO 3 other half */
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/* C Register */
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#define IORDYp_NO_SPEED 0x4F
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#define SPEED_DIS 0x0F
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#define DMARQp 0x80
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#define IORDYp 0x40
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#define DMAR_EN 0x20
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#define DMAW_EN 0x10
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#define MC3 0x08 /* DMA"C" timing */
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#define MC2 0x04 /* DMA"C" timing */
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#define MC1 0x02 /* DMA"C" timing */
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#define MC0 0x01 /* DMA"C" timing */
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#if PDC202XX_DECODE_REGISTER_INFO
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#define REG_A 0x01
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#define REG_B 0x02
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#define REG_C 0x04
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#define REG_D 0x08
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static void decode_registers (u8 registers, u8 value)
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{
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u8 bit = 0, bit1 = 0, bit2 = 0;
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switch(registers) {
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case REG_A:
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bit2 = 0;
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printk("A Register ");
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if (value & 0x80) printk("SYNC_IN ");
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if (value & 0x40) printk("ERRDY_EN ");
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if (value & 0x20) printk("IORDY_EN ");
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if (value & 0x10) printk("PREFETCH_EN ");
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if (value & 0x08) { printk("PA3 ");bit2 |= 0x08; }
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if (value & 0x04) { printk("PA2 ");bit2 |= 0x04; }
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if (value & 0x02) { printk("PA1 ");bit2 |= 0x02; }
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if (value & 0x01) { printk("PA0 ");bit2 |= 0x01; }
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printk("PIO(A) = %d ", bit2);
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break;
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case REG_B:
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bit1 = 0;bit2 = 0;
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printk("B Register ");
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if (value & 0x80) { printk("MB2 ");bit1 |= 0x80; }
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if (value & 0x40) { printk("MB1 ");bit1 |= 0x40; }
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if (value & 0x20) { printk("MB0 ");bit1 |= 0x20; }
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printk("DMA(B) = %d ", bit1 >> 5);
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if (value & 0x10) printk("PIO_FORCED/PB4 ");
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if (value & 0x08) { printk("PB3 ");bit2 |= 0x08; }
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if (value & 0x04) { printk("PB2 ");bit2 |= 0x04; }
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if (value & 0x02) { printk("PB1 ");bit2 |= 0x02; }
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if (value & 0x01) { printk("PB0 ");bit2 |= 0x01; }
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printk("PIO(B) = %d ", bit2);
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break;
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case REG_C:
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bit2 = 0;
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printk("C Register ");
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if (value & 0x80) printk("DMARQp ");
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if (value & 0x40) printk("IORDYp ");
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if (value & 0x20) printk("DMAR_EN ");
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if (value & 0x10) printk("DMAW_EN ");
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if (value & 0x08) { printk("MC3 ");bit2 |= 0x08; }
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if (value & 0x04) { printk("MC2 ");bit2 |= 0x04; }
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if (value & 0x02) { printk("MC1 ");bit2 |= 0x02; }
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if (value & 0x01) { printk("MC0 ");bit2 |= 0x01; }
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printk("DMA(C) = %d ", bit2);
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break;
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case REG_D:
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printk("D Register ");
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break;
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default:
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return;
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}
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printk("\n %s ", (registers & REG_D) ? "DP" :
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(registers & REG_C) ? "CP" :
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(registers & REG_B) ? "BP" :
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(registers & REG_A) ? "AP" : "ERROR");
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for (bit=128;bit>0;bit/=2)
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printk("%s", (value & bit) ? "1" : "0");
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printk("\n");
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}
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#endif /* PDC202XX_DECODE_REGISTER_INFO */
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#define set_2regs(a, b) \
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do { \
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hwif->OUTB((a + adj), indexreg); \
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hwif->OUTB(b, datareg); \
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} while(0)
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#define set_ultra(a, b, c) \
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do { \
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set_2regs(0x10,(a)); \
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set_2regs(0x11,(b)); \
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set_2regs(0x12,(c)); \
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} while(0)
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#define set_ata2(a, b) \
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do { \
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set_2regs(0x0e,(a)); \
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set_2regs(0x0f,(b)); \
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} while(0)
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#define set_pio(a, b, c) \
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do { \
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set_2regs(0x0c,(a)); \
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set_2regs(0x0d,(b)); \
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set_2regs(0x13,(c)); \
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} while(0)
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#define DISPLAY_PDC202XX_TIMINGS
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#if defined(DISPLAY_PDC202XX_TIMINGS) && defined(CONFIG_PROC_FS)
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#include <linux/stat.h>
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#include <linux/proc_fs.h>
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static u8 pdcnew_proc;
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static int pdcnew_get_info(char *, char **, off_t, int);
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static ide_pci_host_proc_t pdcnew_procs[] __initdata = {
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{
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.name = "pdcnew",
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.set = 1,
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.get_info = pdcnew_get_info,
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.parent = NULL,
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},
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};
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#endif /* DISPLAY_PDC202XX_TIMINGS && CONFIG_PROC_FS */
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static void init_setup_pdcnew(struct pci_dev *, ide_pci_device_t *);
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static void init_setup_pdc20270(struct pci_dev *, ide_pci_device_t *);
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static void init_setup_pdc20276(struct pci_dev *dev, ide_pci_device_t *d);
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static unsigned int init_chipset_pdcnew(struct pci_dev *, const char *);
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static void init_hwif_pdc202new(ide_hwif_t *);
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static void init_dma_pdc202new(ide_hwif_t *, unsigned long);
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static ide_pci_device_t pdcnew_chipsets[] __devinitdata = {
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{ /* 0 */
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.vendor = PCI_VENDOR_ID_PROMISE,
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.device = PCI_DEVICE_ID_PROMISE_20268,
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.name = "PDC20268",
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.init_setup = init_setup_pdcnew,
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.init_chipset = init_chipset_pdcnew,
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.init_iops = NULL,
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.init_hwif = init_hwif_pdc202new,
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.init_dma = init_dma_pdc202new,
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
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.bootable = OFF_BOARD,
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.extra = 0,
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},{ /* 1 */
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.vendor = PCI_VENDOR_ID_PROMISE,
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.device = PCI_DEVICE_ID_PROMISE_20269,
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.name = "PDC20269",
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.init_setup = init_setup_pdcnew,
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.init_chipset = init_chipset_pdcnew,
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.init_iops = NULL,
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.init_hwif = init_hwif_pdc202new,
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.init_dma = init_dma_pdc202new,
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
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.bootable = OFF_BOARD,
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.extra = 0,
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},{ /* 2 */
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.vendor = PCI_VENDOR_ID_PROMISE,
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.device = PCI_DEVICE_ID_PROMISE_20270,
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.name = "PDC20270",
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.init_setup = init_setup_pdc20270,
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.init_chipset = init_chipset_pdcnew,
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.init_iops = NULL,
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.init_hwif = init_hwif_pdc202new,
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.init_dma = init_dma_pdc202new,
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.channels = 2,
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.autodma = AUTODMA,
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#ifdef CONFIG_PDC202XX_FORCE
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.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
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#else /* !CONFIG_PDC202XX_FORCE */
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.enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
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#endif
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.bootable = OFF_BOARD,
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.extra = 0,
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},{ /* 3 */
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.vendor = PCI_VENDOR_ID_PROMISE,
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.device = PCI_DEVICE_ID_PROMISE_20271,
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.name = "PDC20271",
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.init_setup = init_setup_pdcnew,
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.init_chipset = init_chipset_pdcnew,
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.init_iops = NULL,
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.init_hwif = init_hwif_pdc202new,
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.init_dma = init_dma_pdc202new,
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
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.bootable = OFF_BOARD,
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.extra = 0,
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},{ /* 4 */
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.vendor = PCI_VENDOR_ID_PROMISE,
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.device = PCI_DEVICE_ID_PROMISE_20275,
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.name = "PDC20275",
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.init_setup = init_setup_pdc20276,
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.init_chipset = init_chipset_pdcnew,
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.init_iops = NULL,
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.init_hwif = init_hwif_pdc202new,
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.init_dma = init_dma_pdc202new,
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
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.bootable = OFF_BOARD,
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.extra = 0,
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},{ /* 5 */
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.vendor = PCI_VENDOR_ID_PROMISE,
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.device = PCI_DEVICE_ID_PROMISE_20276,
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.name = "PDC20276",
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.init_setup = init_setup_pdc20276,
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.init_chipset = init_chipset_pdcnew,
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.init_iops = NULL,
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.init_hwif = init_hwif_pdc202new,
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.init_dma = init_dma_pdc202new,
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.channels = 2,
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.autodma = AUTODMA,
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#ifdef CONFIG_PDC202XX_FORCE
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.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
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#else /* !CONFIG_PDC202XX_FORCE */
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.enablebits = {{0x50,0x02,0x02}, {0x50,0x04,0x04}},
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#endif
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.bootable = OFF_BOARD,
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.extra = 0,
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},{ /* 6 */
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.vendor = PCI_VENDOR_ID_PROMISE,
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.device = PCI_DEVICE_ID_PROMISE_20277,
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.name = "PDC20277",
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.init_setup = init_setup_pdc20276,
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291 |
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.init_chipset = init_chipset_pdcnew,
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.init_iops = NULL,
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293 |
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.init_hwif = init_hwif_pdc202new,
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294 |
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.init_dma = init_dma_pdc202new,
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295 |
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.channels = 2,
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.autodma = AUTODMA,
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.enablebits = {{0x00,0x00,0x00}, {0x00,0x00,0x00}},
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.bootable = OFF_BOARD,
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.extra = 0,
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},{
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.vendor = 0,
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.device = 0,
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.channels = 0,
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.bootable = EOL,
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}
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};
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308 |
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#endif /* PDC202XX_H */
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