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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [ide/] [pci/] [trm290.c] - Blame information for rev 1765

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1 1275 phoenix
/*
2
 *  linux/drivers/ide/pci/trm290.c              Version 1.02    Mar. 18, 2000
3
 *
4
 *  Copyright (c) 1997-1998  Mark Lord
5
 *  May be copied or modified under the terms of the GNU General Public License
6
 */
7
 
8
/*
9
 * This module provides support for the bus-master IDE DMA function
10
 * of the Tekram TRM290 chip, used on a variety of PCI IDE add-on boards,
11
 * including a "Precision Instruments" board.  The TRM290 pre-dates
12
 * the sff-8038 standard (ide-dma.c) by a few months, and differs
13
 * significantly enough to warrant separate routines for some functions,
14
 * while re-using others from ide-dma.c.
15
 *
16
 * EXPERIMENTAL!  It works for me (a sample of one).
17
 *
18
 * Works reliably for me in DMA mode (READs only),
19
 * DMA WRITEs are disabled by default (see #define below);
20
 *
21
 * DMA is not enabled automatically for this chipset,
22
 * but can be turned on manually (with "hdparm -d1") at run time.
23
 *
24
 * I need volunteers with "spare" drives for further testing
25
 * and development, and maybe to help figure out the peculiarities.
26
 * Even knowing the registers (below), some things behave strangely.
27
 */
28
 
29
#define TRM290_NO_DMA_WRITES    /* DMA writes seem unreliable sometimes */
30
 
31
/*
32
 * TRM-290 PCI-IDE2 Bus Master Chip
33
 * ================================
34
 * The configuration registers are addressed in normal I/O port space
35
 * and are used as follows:
36
 *
37
 * trm290_base depends on jumper settings, and is probed for by ide-dma.c
38
 *
39
 * trm290_base+2 when WRITTEN: chiptest register (byte, write-only)
40
 *      bit7 must always be written as "1"
41
 *      bits6-2 undefined
42
 *      bit1 1=legacy_compatible_mode, 0=native_pci_mode
43
 *      bit0 1=test_mode, 0=normal(default)
44
 *
45
 * trm290_base+2 when READ: status register (byte, read-only)
46
 *      bits7-2 undefined
47
 *      bit1 channel0 busmaster interrupt status 0=none, 1=asserted
48
 *      bit0 channel0 interrupt status 0=none, 1=asserted
49
 *
50
 * trm290_base+3 Interrupt mask register
51
 *      bits7-5 undefined
52
 *      bit4 legacy_header: 1=present, 0=absent
53
 *      bit3 channel1 busmaster interrupt status 0=none, 1=asserted (read only)
54
 *      bit2 channel1 interrupt status 0=none, 1=asserted (read only)
55
 *      bit1 channel1 interrupt mask: 1=masked, 0=unmasked(default)
56
 *      bit0 channel0 interrupt mask: 1=masked, 0=unmasked(default)
57
 *
58
 * trm290_base+1 "CPR" Config Pointer Register (byte)
59
 *      bit7 1=autoincrement CPR bits 2-0 after each access of CDR
60
 *      bit6 1=min. 1 wait-state posted write cycle (default), 0=0 wait-state
61
 *      bit5 0=enabled master burst access (default), 1=disable  (write only)
62
 *      bit4 PCI DEVSEL# timing select: 1=medium(default), 0=fast
63
 *      bit3 0=primary IDE channel, 1=secondary IDE channel
64
 *      bits2-0 register index for accesses through CDR port
65
 *
66
 * trm290_base+0 "CDR" Config Data Register (word)
67
 *      two sets of seven config registers,
68
 *      selected by CPR bit 3 (channel) and CPR bits 2-0 (index 0 to 6),
69
 *      each index defined below:
70
 *
71
 * Index-0 Base address register for command block (word)
72
 *      defaults: 0x1f0 for primary, 0x170 for secondary
73
 *
74
 * Index-1 general config register (byte)
75
 *      bit7 1=DMA enable, 0=DMA disable
76
 *      bit6 1=activate IDE_RESET, 0=no action (default)
77
 *      bit5 1=enable IORDY, 0=disable IORDY (default)
78
 *      bit4 0=16-bit data port(default), 1=8-bit (XT) data port
79
 *      bit3 interrupt polarity: 1=active_low, 0=active_high(default)
80
 *      bit2 power-saving-mode(?): 1=enable, 0=disable(default) (write only)
81
 *      bit1 bus_master_mode(?): 1=enable, 0=disable(default)
82
 *      bit0 enable_io_ports: 1=enable(default), 0=disable
83
 *
84
 * Index-2 read-ahead counter preload bits 0-7 (byte, write only)
85
 *      bits7-0 bits7-0 of readahead count
86
 *
87
 * Index-3 read-ahead config register (byte, write only)
88
 *      bit7 1=enable_readahead, 0=disable_readahead(default)
89
 *      bit6 1=clear_FIFO, 0=no_action
90
 *      bit5 undefined
91
 *      bit4 mode4 timing control: 1=enable, 0=disable(default)
92
 *      bit3 undefined
93
 *      bit2 undefined
94
 *      bits1-0 bits9-8 of read-ahead count
95
 *
96
 * Index-4 base address register for control block (word)
97
 *      defaults: 0x3f6 for primary, 0x376 for secondary
98
 *
99
 * Index-5 data port timings (shared by both drives) (byte)
100
 *      standard PCI "clk" (clock) counts, default value = 0xf5
101
 *
102
 *      bits7-6 setup time:  00=1clk, 01=2clk, 10=3clk, 11=4clk
103
 *      bits5-3 hold time:      000=1clk, 001=2clk, 010=3clk,
104
 *                              011=4clk, 100=5clk, 101=6clk,
105
 *                              110=8clk, 111=12clk
106
 *      bits2-0 active time:    000=2clk, 001=3clk, 010=4clk,
107
 *                              011=5clk, 100=6clk, 101=8clk,
108
 *                              110=12clk, 111=16clk
109
 *
110
 * Index-6 command/control port timings (shared by both drives) (byte)
111
 *      same layout as Index-5, default value = 0xde
112
 *
113
 * Suggested CDR programming for PIO mode0 (600ns):
114
 *      0x01f0,0x21,0xff,0x80,0x03f6,0xf5,0xde  ; primary
115
 *      0x0170,0x21,0xff,0x80,0x0376,0xf5,0xde  ; secondary
116
 *
117
 * Suggested CDR programming for PIO mode3 (180ns):
118
 *      0x01f0,0x21,0xff,0x80,0x03f6,0x09,0xde  ; primary
119
 *      0x0170,0x21,0xff,0x80,0x0376,0x09,0xde  ; secondary
120
 *
121
 * Suggested CDR programming for PIO mode4 (120ns):
122
 *      0x01f0,0x21,0xff,0x80,0x03f6,0x00,0xde  ; primary
123
 *      0x0170,0x21,0xff,0x80,0x0376,0x00,0xde  ; secondary
124
 *
125
 */
126
 
127
#include <linux/config.h>
128
#include <linux/types.h>
129
#include <linux/module.h>
130
#include <linux/kernel.h>
131
#include <linux/mm.h>
132
#include <linux/ioport.h>
133
#include <linux/interrupt.h>
134
#include <linux/blkdev.h>
135
#include <linux/init.h>
136
#include <linux/hdreg.h>
137
#include <linux/pci.h>
138
#include <linux/delay.h>
139
#include <linux/ide.h>
140
 
141
#include <asm/io.h>
142
 
143
#include "trm290.h"
144
 
145
static void trm290_prepare_drive (ide_drive_t *drive, unsigned int use_dma)
146
{
147
        ide_hwif_t *hwif = HWIF(drive);
148
        u16 reg = 0;
149
        unsigned long flags;
150
 
151
        /* select PIO or DMA */
152
        reg = use_dma ? (0x21 | 0x82) : (0x21 & ~0x82);
153
 
154
        local_irq_save(flags);
155
 
156
        if (reg != hwif->select_data) {
157
                hwif->select_data = reg;
158
                /* set PIO/DMA */
159
                hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
160
                hwif->OUTW(reg & 0xff, hwif->config_data);
161
        }
162
 
163
        /* enable IRQ if not probing */
164
        if (drive->present) {
165
                reg = hwif->INW(hwif->config_data + 3);
166
                reg &= 0x13;
167
                reg &= ~(1 << hwif->channel);
168
                hwif->OUTW(reg, hwif->config_data+3);
169
        }
170
 
171
        local_irq_restore(flags);
172
}
173
 
174
static void trm290_selectproc (ide_drive_t *drive)
175
{
176
        trm290_prepare_drive(drive, drive->using_dma);
177
}
178
 
179
#ifdef CONFIG_BLK_DEV_IDEDMA
180
static int trm290_ide_dma_write (ide_drive_t *drive /*, struct request *rq */)
181
{
182
        ide_hwif_t *hwif        = HWIF(drive);
183
        struct request *rq      = HWGROUP(drive)->rq;
184
//      ide_task_t *args        = rq->special;
185
        task_ioreg_t command    = WIN_NOP;
186
        unsigned int count, reading = 2, writing = 0;
187
 
188
        reading = 0;
189
        writing = 1;
190
#ifdef TRM290_NO_DMA_WRITES
191
        /* always use PIO for writes */
192
        trm290_prepare_drive(drive, 0);  /* select PIO xfer */
193
        return 1;
194
#endif
195
        if (!(count = ide_build_dmatable(drive, rq, PCI_DMA_TODEVICE))) {
196
                /* try PIO instead of DMA */
197
                trm290_prepare_drive(drive, 0); /* select PIO xfer */
198
                return 1;
199
        }
200
        /* select DMA xfer */
201
        trm290_prepare_drive(drive, 1);
202
        hwif->OUTL(hwif->dmatable_dma|reading|writing, hwif->dma_command);
203
        drive->waiting_for_dma = 1;
204
        /* start DMA */
205
        hwif->OUTW((count * 2) - 1, hwif->dma_status);
206
        if (drive->media != ide_disk)
207
                return 0;
208
        if (HWGROUP(drive)->handler != NULL)    /* paranoia check */
209
                BUG();
210
        ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
211
        /*
212
         * FIX ME to use only ACB ide_task_t args Struct
213
         */
214
#if 0
215
        {
216
                ide_task_t *args = rq->special;
217
                command = args->tfRegister[IDE_COMMAND_OFFSET];
218
        }
219
#else
220
        command = /* (lba48) ? WIN_READDMA_EXT : */ WIN_READDMA;
221
        if (rq->cmd == IDE_DRIVE_TASKFILE) {
222
                ide_task_t *args = rq->special;
223
                command = args->tfRegister[IDE_COMMAND_OFFSET];
224
        }
225
#endif
226
        /* issue cmd to drive */
227
        hwif->OUTB(command, IDE_COMMAND_REG);
228
        return HWIF(drive)->ide_dma_count(drive);
229
}
230
 
231
static int trm290_ide_dma_read (ide_drive_t *drive  /*, struct request *rq */)
232
{
233
        ide_hwif_t *hwif        = HWIF(drive);
234
        struct request *rq      = HWGROUP(drive)->rq;
235
//      ide_task_t *args        = rq->special;
236
        task_ioreg_t command    = WIN_NOP;
237
        unsigned int count, reading = 2, writing = 0;
238
 
239
        if (!(count = ide_build_dmatable(drive, rq, PCI_DMA_FROMDEVICE))) {
240
                /* try PIO instead of DMA */
241
                trm290_prepare_drive(drive, 0); /* select PIO xfer */
242
                return 1;
243
        }
244
        /* select DMA xfer */
245
        trm290_prepare_drive(drive, 1);
246
        hwif->OUTL(hwif->dmatable_dma|reading|writing, hwif->dma_command);
247
        drive->waiting_for_dma = 1;
248
        /* start DMA */
249
        hwif->OUTW((count * 2) - 1, hwif->dma_status);
250
        if (drive->media != ide_disk)
251
                return 0;
252
        if (HWGROUP(drive)->handler != NULL)    /* paranoia check */
253
                BUG();
254
        ide_set_handler(drive, &ide_dma_intr, WAIT_CMD, NULL);
255
        /*
256
         * FIX ME to use only ACB ide_task_t args Struct
257
         */
258
#if 0
259
        {
260
                ide_task_t *args = rq->special;
261
                command = args->tfRegister[IDE_COMMAND_OFFSET];
262
        }
263
#else
264
        command = /* (lba48) ? WIN_WRITEDMA_EXT : */ WIN_WRITEDMA;
265
        if (rq->cmd == IDE_DRIVE_TASKFILE) {
266
                ide_task_t *args = rq->special;
267
                command = args->tfRegister[IDE_COMMAND_OFFSET];
268
        }
269
#endif
270
        /* issue cmd to drive */
271
        hwif->OUTB(command, IDE_COMMAND_REG);
272
        return HWIF(drive)->ide_dma_count(drive);
273
}
274
 
275
static int trm290_ide_dma_begin (ide_drive_t *drive)
276
{
277
        return 0;
278
}
279
 
280
static int trm290_ide_dma_end (ide_drive_t *drive)
281
{
282
        ide_hwif_t *hwif = HWIF(drive);
283
        u16 status = 0;;
284
 
285
        drive->waiting_for_dma = 0;
286
        /* purge DMA mappings */
287
        ide_destroy_dmatable(drive);
288
        status = hwif->INW(hwif->dma_status);
289
        return (status != 0x00ff);
290
}
291
 
292
static int trm290_ide_dma_test_irq (ide_drive_t *drive)
293
{
294
        ide_hwif_t *hwif = HWIF(drive);
295
        u16 status = 0;
296
 
297
        status = hwif->INW(hwif->dma_status);
298
        return (status == 0x00ff);
299
}
300
#endif /* CONFIG_BLK_DEV_IDEDMA */
301
 
302
/*
303
 * Invoked from ide-dma.c at boot time.
304
 */
305
void __init init_hwif_trm290 (ide_hwif_t *hwif)
306
{
307
        unsigned int cfgbase = 0;
308
        unsigned long flags;
309
        u8 reg = 0;
310
        struct pci_dev *dev = hwif->pci_dev;
311
 
312
        hwif->addressing = 1;
313
        hwif->chipset = ide_trm290;
314
        cfgbase = pci_resource_start(dev, 4);
315
        if ((dev->class & 5) && cfgbase) {
316
                hwif->config_data = cfgbase;
317
                printk(KERN_INFO "TRM290: chip config base at 0x%04lx\n",
318
                        hwif->config_data);
319
        } else {
320
                hwif->config_data = 0x3df0;
321
                printk(KERN_INFO "TRM290: using default config base at 0x%04lx\n",
322
                        hwif->config_data);
323
        }
324
 
325
        local_irq_save(flags);
326
        /* put config reg into first byte of hwif->select_data */
327
        hwif->OUTB(0x51|(hwif->channel<<3), hwif->config_data+1);
328
        /* select PIO as default */
329
        hwif->select_data = 0x21;
330
        hwif->OUTB(hwif->select_data, hwif->config_data);
331
        /* get IRQ info */
332
        reg = hwif->INB(hwif->config_data+3);
333
        /* mask IRQs for both ports */
334
        reg = (reg & 0x10) | 0x03;
335
        hwif->OUTB(reg, hwif->config_data+3);
336
        local_irq_restore(flags);
337
 
338
        if ((reg & 0x10))
339
                /* legacy mode */
340
                hwif->irq = hwif->channel ? 15 : 14;
341
        else if (!hwif->irq && hwif->mate && hwif->mate->irq)
342
                /* sharing IRQ with mate */
343
                hwif->irq = hwif->mate->irq;
344
 
345
        ide_setup_dma(hwif, (hwif->config_data + 4) ^ (hwif->channel ? 0x0080 : 0x0000), 3);
346
 
347
#ifdef CONFIG_BLK_DEV_IDEDMA
348
        hwif->ide_dma_write = &trm290_ide_dma_write;
349
        hwif->ide_dma_read = &trm290_ide_dma_read;
350
        hwif->ide_dma_begin = &trm290_ide_dma_begin;
351
        hwif->ide_dma_end = &trm290_ide_dma_end;
352
        hwif->ide_dma_test_irq = &trm290_ide_dma_test_irq;
353
#endif /* CONFIG_BLK_DEV_IDEDMA */
354
 
355
        hwif->selectproc = &trm290_selectproc;
356
        hwif->autodma = 0;               /* play it safe for now */
357
        hwif->drives[0].autodma = hwif->autodma;
358
        hwif->drives[1].autodma = hwif->autodma;
359
#if 1
360
        {
361
        /*
362
         * My trm290-based card doesn't seem to work with all possible values
363
         * for the control basereg, so this kludge ensures that we use only
364
         * values that are known to work.  Ugh.         -ml
365
         */
366
                u16 new, old, compat = hwif->channel ? 0x374 : 0x3f4;
367
                static u16 next_offset = 0;
368
                u8 old_mask;
369
 
370
                hwif->OUTB(0x54|(hwif->channel<<3), hwif->config_data+1);
371
                old = hwif->INW(hwif->config_data);
372
                old &= ~1;
373
                old_mask = hwif->INB(old+2);
374
                if (old != compat && old_mask == 0xff) {
375
                        /* leave lower 10 bits untouched */
376
                        compat += (next_offset += 0x400);
377
#  if 1
378
                        if (check_region(compat + 2, 1))
379
                                printk(KERN_ERR "%s: check_region failure at 0x%04x\n",
380
                                        hwif->name, (compat + 2));
381
                        /*
382
                         * The region check is not needed; however.........
383
                         * Since this is the checked in ide-probe.c,
384
                         * this is only an assignment.
385
                         */
386
#  endif
387
                        hwif->io_ports[IDE_CONTROL_OFFSET] = compat + 2;
388
                        hwif->OUTW(compat|1, hwif->config_data);
389
                        new = hwif->INW(hwif->config_data);
390
                        printk(KERN_INFO "%s: control basereg workaround: "
391
                                "old=0x%04x, new=0x%04x\n",
392
                                hwif->name, old, new & ~1);
393
                }
394
        }
395
#endif
396
}
397
 
398
extern void ide_setup_pci_device(struct pci_dev *, ide_pci_device_t *);
399
 
400
static int __devinit trm290_init_one(struct pci_dev *dev, const struct pci_device_id *id)
401
{
402
        ide_pci_device_t *d = &trm290_chipsets[id->driver_data];
403
        if (dev->device != d->device)
404
                BUG();
405
        ide_setup_pci_device(dev, d);
406
        MOD_INC_USE_COUNT;
407
        return 0;
408
}
409
 
410
/**
411
 *      trm290_remove_one       -       called when an trm290 is unplugged
412
 *      @dev: the device that was removed
413
 *
414
 *      Disconnect a trm290 device that has been unplugged either by hotplug
415
 *      or by a more civilized notification scheme. Not yet supported.
416
 */
417
 
418
static void trm290_remove_one(struct pci_dev *dev)
419
{
420
        printk("trm290 removal not yet supported.\n");
421
}
422
 
423
static struct pci_device_id trm290_pci_tbl[] __devinitdata = {
424
        { PCI_VENDOR_ID_TEKRAM, PCI_DEVICE_ID_TEKRAM_DC290, PCI_ANY_ID, PCI_ANY_ID, 0, 0, 0},
425
        { 0, },
426
};
427
 
428
static struct pci_driver driver = {
429
        name:           "TRM290 IDE",
430
        id_table:       trm290_pci_tbl,
431
        probe:          trm290_init_one,
432
        remove:         __devexit_p(trm290_remove_one),
433
};
434
 
435
static int trm290_ide_init(void)
436
{
437
        return ide_pci_register_driver(&driver);
438
}
439
 
440
static void trm290_ide_exit(void)
441
{
442
        ide_pci_unregister_driver(&driver);
443
}
444
 
445
module_init(trm290_ide_init);
446
module_exit(trm290_ide_exit);
447
 
448
MODULE_AUTHOR("Mark Lord");
449
MODULE_DESCRIPTION("PCI driver module for Tekram TRM290 IDE");
450
MODULE_LICENSE("GPL");
451
 
452
EXPORT_NO_SYMBOLS;

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