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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [ieee1394/] [pcilynx.h] - Blame information for rev 1765

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1 1275 phoenix
#include <linux/config.h>
2
 
3
#define PCILYNX_DRIVER_NAME      "pcilynx"
4
#define PCILYNX_MAJOR            177
5
 
6
#define PCILYNX_MINOR_AUX_START  0
7
#define PCILYNX_MINOR_ROM_START  16
8
#define PCILYNX_MINOR_RAM_START  32
9
 
10
#define PCILYNX_MAX_REGISTER     0xfff
11
#define PCILYNX_MAX_MEMORY       0xffff
12
 
13
#define PCI_DEVICE_ID_TI_PCILYNX 0x8000
14
#define MAX_PCILYNX_CARDS        4
15
#define LOCALRAM_SIZE            4096
16
 
17
#define NUM_ISORCV_PCL           4
18
#define MAX_ISORCV_SIZE          2048
19
#define ISORCV_PER_PAGE          (PAGE_SIZE / MAX_ISORCV_SIZE)
20
#define ISORCV_PAGES             (NUM_ISORCV_PCL / ISORCV_PER_PAGE)
21
 
22
#define CHANNEL_LOCALBUS         0
23
#define CHANNEL_ASYNC_RCV        1
24
#define CHANNEL_ISO_RCV          2
25
#define CHANNEL_ASYNC_SEND       3
26
#define CHANNEL_ISO_SEND         4
27
 
28
#define PCILYNX_CONFIG_ROM_LENGTH   1024
29
 
30
typedef int pcl_t;
31
 
32
struct ti_lynx {
33
        int id; /* sequential card number */
34
 
35
        spinlock_t lock;
36
 
37
        struct pci_dev *dev;
38
 
39
        struct {
40
                unsigned reg_1394a:1;
41
                u32 vendor;
42
                u32 product;
43
        } phyic;
44
 
45
        enum { clear, have_intr, have_aux_buf, have_pcl_mem,
46
               have_1394_buffers, have_iomappings, is_host } state;
47
 
48
        /* remapped memory spaces */
49
        void *registers;
50
        void *local_rom;
51
        void *local_ram;
52
        void *aux_port;
53
        quadlet_t config_rom[PCILYNX_CONFIG_ROM_LENGTH/4];
54
 
55
#ifdef CONFIG_IEEE1394_PCILYNX_PORTS
56
        atomic_t aux_intr_seen;
57
        wait_queue_head_t aux_intr_wait;
58
 
59
        void *mem_dma_buffer;
60
        dma_addr_t mem_dma_buffer_dma;
61
        struct semaphore mem_dma_mutex;
62
        wait_queue_head_t mem_dma_intr_wait;
63
#endif
64
 
65
        /*
66
         * use local RAM of LOCALRAM_SIZE bytes for PCLs, which allows for
67
         * LOCALRAM_SIZE * 8 PCLs (each sized 128 bytes);
68
         * the following is an allocation bitmap
69
         */
70
        u8 pcl_bmap[LOCALRAM_SIZE / 1024];
71
 
72
#ifndef CONFIG_IEEE1394_PCILYNX_LOCALRAM
73
        /* point to PCLs memory area if needed */
74
        void *pcl_mem;
75
        dma_addr_t pcl_mem_dma;
76
#endif
77
 
78
        /* PCLs for local mem / aux transfers */
79
        pcl_t dmem_pcl;
80
 
81
        /* IEEE-1394 part follows */
82
        struct hpsb_host *host;
83
 
84
        int phyid, isroot;
85
        int selfid_size;
86
        int phy_reg0;
87
 
88
        spinlock_t phy_reg_lock;
89
 
90
        pcl_t rcv_pcl_start, rcv_pcl;
91
        void *rcv_page;
92
        dma_addr_t rcv_page_dma;
93
        int rcv_active;
94
 
95
        struct lynx_send_data {
96
                pcl_t pcl_start, pcl;
97
                struct list_head queue;
98
                struct list_head pcl_queue; /* this queue contains at most one packet */
99
                spinlock_t queue_lock;
100
                dma_addr_t header_dma, data_dma;
101
                int channel;
102
        } async, iso_send;
103
 
104
        struct {
105
                pcl_t pcl[NUM_ISORCV_PCL];
106
                u32 stat[NUM_ISORCV_PCL];
107
                void *page[ISORCV_PAGES];
108
                dma_addr_t page_dma[ISORCV_PAGES];
109
                pcl_t pcl_start;
110
                int chan_count;
111
                int next, last, used, running;
112
                struct tasklet_struct tq;
113
                spinlock_t lock;
114
        } iso_rcv;
115
 
116
        u32 i2c_driven_state; /* the state we currently drive the Serial EEPROM Control register */
117
};
118
 
119
/* the per-file data structure for mem space access */
120
struct memdata {
121
        struct ti_lynx *lynx;
122
        int cid;
123
        atomic_t aux_intr_last_seen;
124
        /* enum values are the same as LBUS_ADDR_SEL_* values below */
125
        enum { rom = 0x10000, aux = 0x20000, ram = 0 } type;
126
};
127
 
128
 
129
 
130
/*
131
 * Register read and write helper functions.
132
 */
133
static inline void reg_write(const struct ti_lynx *lynx, int offset, u32 data)
134
{
135
        writel(data, lynx->registers + offset);
136
}
137
 
138
static inline u32 reg_read(const struct ti_lynx *lynx, int offset)
139
{
140
        return readl(lynx->registers + offset);
141
}
142
 
143
static inline void reg_set_bits(const struct ti_lynx *lynx, int offset,
144
                                u32 mask)
145
{
146
        reg_write(lynx, offset, (reg_read(lynx, offset) | mask));
147
}
148
 
149
static inline void reg_clear_bits(const struct ti_lynx *lynx, int offset,
150
                                  u32 mask)
151
{
152
        reg_write(lynx, offset, (reg_read(lynx, offset) & ~mask));
153
}
154
 
155
 
156
 
157
/* chip register definitions follow */
158
 
159
#define PCI_LATENCY_CACHELINE             0x0c
160
 
161
#define MISC_CONTROL                      0x40
162
#define MISC_CONTROL_SWRESET              (1<<0)
163
 
164
#define SERIAL_EEPROM_CONTROL             0x44
165
 
166
#define PCI_INT_STATUS                    0x48
167
#define PCI_INT_ENABLE                    0x4c               
168
/* status and enable have identical bit numbers */
169
#define PCI_INT_INT_PEND                  (1<<31)
170
#define PCI_INT_FORCED_INT                (1<<30)
171
#define PCI_INT_SLV_ADR_PERR              (1<<28)
172
#define PCI_INT_SLV_DAT_PERR              (1<<27)
173
#define PCI_INT_MST_DAT_PERR              (1<<26)
174
#define PCI_INT_MST_DEV_TIMEOUT           (1<<25)
175
#define PCI_INT_INTERNAL_SLV_TIMEOUT      (1<<23)
176
#define PCI_INT_AUX_TIMEOUT               (1<<18)
177
#define PCI_INT_AUX_INT                   (1<<17)
178
#define PCI_INT_1394                      (1<<16)
179
#define PCI_INT_DMA4_PCL                  (1<<9)
180
#define PCI_INT_DMA4_HLT                  (1<<8)
181
#define PCI_INT_DMA3_PCL                  (1<<7)
182
#define PCI_INT_DMA3_HLT                  (1<<6)
183
#define PCI_INT_DMA2_PCL                  (1<<5)
184
#define PCI_INT_DMA2_HLT                  (1<<4)
185
#define PCI_INT_DMA1_PCL                  (1<<3)
186
#define PCI_INT_DMA1_HLT                  (1<<2)
187
#define PCI_INT_DMA0_PCL                  (1<<1)
188
#define PCI_INT_DMA0_HLT                  (1<<0)
189
/* all DMA interrupts combined: */
190
#define PCI_INT_DMA_ALL                   0x3ff
191
 
192
#define PCI_INT_DMA_HLT(chan)             (1 << (chan * 2))
193
#define PCI_INT_DMA_PCL(chan)             (1 << (chan * 2 + 1))
194
 
195
#define LBUS_ADDR                         0xb4
196
#define LBUS_ADDR_SEL_RAM                 (0x0<<16)
197
#define LBUS_ADDR_SEL_ROM                 (0x1<<16)
198
#define LBUS_ADDR_SEL_AUX                 (0x2<<16)
199
#define LBUS_ADDR_SEL_ZV                  (0x3<<16)       
200
 
201
#define GPIO_CTRL_A                       0xb8
202
#define GPIO_CTRL_B                       0xbc
203
#define GPIO_DATA_BASE                    0xc0
204
 
205
#define DMA_BREG(base, chan)              (base + chan * 0x20)
206
#define DMA_SREG(base, chan)              (base + chan * 0x10)
207
 
208
#define DMA0_PREV_PCL                     0x100               
209
#define DMA1_PREV_PCL                     0x120
210
#define DMA2_PREV_PCL                     0x140
211
#define DMA3_PREV_PCL                     0x160
212
#define DMA4_PREV_PCL                     0x180
213
#define DMA_PREV_PCL(chan)                (DMA_BREG(DMA0_PREV_PCL, chan))
214
 
215
#define DMA0_CURRENT_PCL                  0x104            
216
#define DMA1_CURRENT_PCL                  0x124
217
#define DMA2_CURRENT_PCL                  0x144
218
#define DMA3_CURRENT_PCL                  0x164
219
#define DMA4_CURRENT_PCL                  0x184
220
#define DMA_CURRENT_PCL(chan)             (DMA_BREG(DMA0_CURRENT_PCL, chan))
221
 
222
#define DMA0_CHAN_STAT                    0x10c
223
#define DMA1_CHAN_STAT                    0x12c
224
#define DMA2_CHAN_STAT                    0x14c
225
#define DMA3_CHAN_STAT                    0x16c
226
#define DMA4_CHAN_STAT                    0x18c
227
#define DMA_CHAN_STAT(chan)               (DMA_BREG(DMA0_CHAN_STAT, chan))
228
/* CHAN_STATUS registers share bits */
229
#define DMA_CHAN_STAT_SELFID              (1<<31)
230
#define DMA_CHAN_STAT_ISOPKT              (1<<30)
231
#define DMA_CHAN_STAT_PCIERR              (1<<29)
232
#define DMA_CHAN_STAT_PKTERR              (1<<28)
233
#define DMA_CHAN_STAT_PKTCMPL             (1<<27)
234
#define DMA_CHAN_STAT_SPECIALACK          (1<<14)
235
 
236
 
237
#define DMA0_CHAN_CTRL                    0x110              
238
#define DMA1_CHAN_CTRL                    0x130
239
#define DMA2_CHAN_CTRL                    0x150
240
#define DMA3_CHAN_CTRL                    0x170
241
#define DMA4_CHAN_CTRL                    0x190
242
#define DMA_CHAN_CTRL(chan)               (DMA_BREG(DMA0_CHAN_CTRL, chan))
243
/* CHAN_CTRL registers share bits */
244
#define DMA_CHAN_CTRL_ENABLE              (1<<31)      
245
#define DMA_CHAN_CTRL_BUSY                (1<<30)
246
#define DMA_CHAN_CTRL_LINK                (1<<29)
247
 
248
#define DMA0_READY                        0x114
249
#define DMA1_READY                        0x134
250
#define DMA2_READY                        0x154
251
#define DMA3_READY                        0x174
252
#define DMA4_READY                        0x194
253
#define DMA_READY(chan)                   (DMA_BREG(DMA0_READY, chan))
254
 
255
#define DMA_GLOBAL_REGISTER               0x908
256
 
257
#define FIFO_SIZES                        0xa00
258
 
259
#define FIFO_CONTROL                      0xa10
260
#define FIFO_CONTROL_GRF_FLUSH            (1<<4)
261
#define FIFO_CONTROL_ITF_FLUSH            (1<<3)
262
#define FIFO_CONTROL_ATF_FLUSH            (1<<2)
263
 
264
#define FIFO_XMIT_THRESHOLD               0xa14
265
 
266
#define DMA0_WORD0_CMP_VALUE              0xb00
267
#define DMA1_WORD0_CMP_VALUE              0xb10
268
#define DMA2_WORD0_CMP_VALUE              0xb20
269
#define DMA3_WORD0_CMP_VALUE              0xb30
270
#define DMA4_WORD0_CMP_VALUE              0xb40
271
#define DMA_WORD0_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD0_CMP_VALUE, chan))
272
 
273
#define DMA0_WORD0_CMP_ENABLE             0xb04
274
#define DMA1_WORD0_CMP_ENABLE             0xb14
275
#define DMA2_WORD0_CMP_ENABLE             0xb24
276
#define DMA3_WORD0_CMP_ENABLE             0xb34
277
#define DMA4_WORD0_CMP_ENABLE             0xb44
278
#define DMA_WORD0_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD0_CMP_ENABLE,chan))
279
 
280
#define DMA0_WORD1_CMP_VALUE              0xb08
281
#define DMA1_WORD1_CMP_VALUE              0xb18
282
#define DMA2_WORD1_CMP_VALUE              0xb28
283
#define DMA3_WORD1_CMP_VALUE              0xb38
284
#define DMA4_WORD1_CMP_VALUE              0xb48
285
#define DMA_WORD1_CMP_VALUE(chan)         (DMA_SREG(DMA0_WORD1_CMP_VALUE, chan))
286
 
287
#define DMA0_WORD1_CMP_ENABLE             0xb0c
288
#define DMA1_WORD1_CMP_ENABLE             0xb1c
289
#define DMA2_WORD1_CMP_ENABLE             0xb2c
290
#define DMA3_WORD1_CMP_ENABLE             0xb3c
291
#define DMA4_WORD1_CMP_ENABLE             0xb4c
292
#define DMA_WORD1_CMP_ENABLE(chan)        (DMA_SREG(DMA0_WORD1_CMP_ENABLE,chan))
293
/* word 1 compare enable flags */
294
#define DMA_WORD1_CMP_MATCH_OTHERBUS      (1<<15)
295
#define DMA_WORD1_CMP_MATCH_BROADCAST     (1<<14)
296
#define DMA_WORD1_CMP_MATCH_BUS_BCAST     (1<<13)
297
#define DMA_WORD1_CMP_MATCH_LOCAL_NODE    (1<<12)
298
#define DMA_WORD1_CMP_MATCH_EXACT         (1<<11)
299
#define DMA_WORD1_CMP_ENABLE_SELF_ID      (1<<10)
300
#define DMA_WORD1_CMP_ENABLE_MASTER       (1<<8)
301
 
302
#define LINK_ID                           0xf00
303
#define LINK_ID_BUS(id)                   (id<<22)
304
#define LINK_ID_NODE(id)                  (id<<16)
305
 
306
#define LINK_CONTROL                      0xf04
307
#define LINK_CONTROL_BUSY                 (1<<29)
308
#define LINK_CONTROL_TX_ISO_EN            (1<<26)
309
#define LINK_CONTROL_RX_ISO_EN            (1<<25)
310
#define LINK_CONTROL_TX_ASYNC_EN          (1<<24)
311
#define LINK_CONTROL_RX_ASYNC_EN          (1<<23)
312
#define LINK_CONTROL_RESET_TX             (1<<21)
313
#define LINK_CONTROL_RESET_RX             (1<<20)
314
#define LINK_CONTROL_CYCMASTER            (1<<11)
315
#define LINK_CONTROL_CYCSOURCE            (1<<10)
316
#define LINK_CONTROL_CYCTIMEREN           (1<<9)
317
#define LINK_CONTROL_RCV_CMP_VALID        (1<<7)
318
#define LINK_CONTROL_SNOOP_ENABLE         (1<<6)
319
 
320
#define CYCLE_TIMER                       0xf08
321
 
322
#define LINK_PHY                          0xf0c
323
#define LINK_PHY_READ                     (1<<31)
324
#define LINK_PHY_WRITE                    (1<<30)
325
#define LINK_PHY_ADDR(addr)               (addr<<24)
326
#define LINK_PHY_WDATA(data)              (data<<16)
327
#define LINK_PHY_RADDR(addr)              (addr<<8)
328
 
329
 
330
#define LINK_INT_STATUS                   0xf14
331
#define LINK_INT_ENABLE                   0xf18
332
/* status and enable have identical bit numbers */
333
#define LINK_INT_LINK_INT                 (1<<31)
334
#define LINK_INT_PHY_TIMEOUT              (1<<30)
335
#define LINK_INT_PHY_REG_RCVD             (1<<29)
336
#define LINK_INT_PHY_BUSRESET             (1<<28)
337
#define LINK_INT_TX_RDY                   (1<<26)
338
#define LINK_INT_RX_DATA_RDY              (1<<25)
339
#define LINK_INT_ISO_STUCK                (1<<20)
340
#define LINK_INT_ASYNC_STUCK              (1<<19)
341
#define LINK_INT_SENT_REJECT              (1<<17)
342
#define LINK_INT_HDR_ERR                  (1<<16)
343
#define LINK_INT_TX_INVALID_TC            (1<<15)
344
#define LINK_INT_CYC_SECOND               (1<<11)
345
#define LINK_INT_CYC_START                (1<<10)
346
#define LINK_INT_CYC_DONE                 (1<<9)
347
#define LINK_INT_CYC_PENDING              (1<<8)
348
#define LINK_INT_CYC_LOST                 (1<<7)
349
#define LINK_INT_CYC_ARB_FAILED           (1<<6)
350
#define LINK_INT_GRF_OVERFLOW             (1<<5)
351
#define LINK_INT_ITF_UNDERFLOW            (1<<4)
352
#define LINK_INT_ATF_UNDERFLOW            (1<<3)
353
#define LINK_INT_ISOARB_FAILED            (1<<0) 
354
 
355
/* PHY specifics */
356
#define PHY_VENDORID_TI                 0x800028
357
#define PHY_PRODUCTID_TSB41LV03         0x000000
358
 
359
 
360
/* this is the physical layout of a PCL, its size is 128 bytes */
361
struct ti_pcl {
362
        u32 next;
363
        u32 async_error_next;
364
        u32 user_data;
365
        u32 pcl_status;
366
        u32 remaining_transfer_count;
367
        u32 next_data_buffer;
368
        struct {
369
                u32 control;
370
                u32 pointer;
371
        } buffer[13] __attribute__ ((packed));
372
} __attribute__ ((packed));
373
 
374
#include <linux/stddef.h>
375
#define pcloffs(MEMBER) (offsetof(struct ti_pcl, MEMBER))
376
 
377
 
378
#ifdef CONFIG_IEEE1394_PCILYNX_LOCALRAM
379
 
380
static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
381
                           const struct ti_pcl *pcl)
382
{
383
        int i;
384
        u32 *in = (u32 *)pcl;
385
        u32 *out = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));
386
 
387
        for (i = 0; i < 32; i++, out++, in++) {
388
                writel(*in, out);
389
        }
390
}
391
 
392
static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
393
                           struct ti_pcl *pcl)
394
{
395
        int i;
396
        u32 *out = (u32 *)pcl;
397
        u32 *in = (u32 *)(lynx->local_ram + pclid * sizeof(struct ti_pcl));
398
 
399
        for (i = 0; i < 32; i++, out++, in++) {
400
                *out = readl(in);
401
        }
402
}
403
 
404
static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
405
{
406
        return pci_resource_start(lynx->dev, 1) + pclid * sizeof(struct ti_pcl);
407
}
408
 
409
#else /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */
410
 
411
static inline void put_pcl(const struct ti_lynx *lynx, pcl_t pclid,
412
                           const struct ti_pcl *pcl)
413
{
414
        memcpy_le32((u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
415
                    (u32 *)pcl, sizeof(struct ti_pcl));
416
}
417
 
418
static inline void get_pcl(const struct ti_lynx *lynx, pcl_t pclid,
419
                           struct ti_pcl *pcl)
420
{
421
        memcpy_le32((u32 *)pcl,
422
                    (u32 *)(lynx->pcl_mem + pclid * sizeof(struct ti_pcl)),
423
                    sizeof(struct ti_pcl));
424
}
425
 
426
static inline u32 pcl_bus(const struct ti_lynx *lynx, pcl_t pclid)
427
{
428
        return lynx->pcl_mem_dma + pclid * sizeof(struct ti_pcl);
429
}
430
 
431
#endif /* CONFIG_IEEE1394_PCILYNX_LOCALRAM */
432
 
433
 
434
#if defined (CONFIG_IEEE1394_PCILYNX_LOCALRAM) || defined (__BIG_ENDIAN)
435
typedef struct ti_pcl pcltmp_t;
436
 
437
static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
438
                                      pcltmp_t *tmp)
439
{
440
        get_pcl(lynx, pclid, tmp);
441
        return tmp;
442
}
443
 
444
static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
445
                              pcltmp_t *tmp)
446
{
447
        put_pcl(lynx, pclid, tmp);
448
}
449
 
450
#else
451
typedef int pcltmp_t; /* just a dummy */
452
 
453
static inline struct ti_pcl *edit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
454
                                      pcltmp_t *tmp)
455
{
456
        return lynx->pcl_mem + pclid * sizeof(struct ti_pcl);
457
}
458
 
459
static inline void commit_pcl(const struct ti_lynx *lynx, pcl_t pclid,
460
                              pcltmp_t *tmp)
461
{
462
}
463
#endif
464
 
465
 
466
static inline void run_sub_pcl(const struct ti_lynx *lynx, pcl_t pclid, int idx,
467
                               int dmachan)
468
{
469
        reg_write(lynx, DMA0_CURRENT_PCL + dmachan * 0x20,
470
                  pcl_bus(lynx, pclid) + idx * 4);
471
        reg_write(lynx, DMA0_CHAN_CTRL + dmachan * 0x20,
472
                  DMA_CHAN_CTRL_ENABLE | DMA_CHAN_CTRL_LINK);
473
}
474
 
475
static inline void run_pcl(const struct ti_lynx *lynx, pcl_t pclid, int dmachan)
476
{
477
        run_sub_pcl(lynx, pclid, 0, dmachan);
478
}
479
 
480
#define PCL_NEXT_INVALID (1<<0)
481
 
482
/* transfer commands */
483
#define PCL_CMD_RCV            (0x1<<24)
484
#define PCL_CMD_RCV_AND_UPDATE (0xa<<24)
485
#define PCL_CMD_XMT            (0x2<<24)
486
#define PCL_CMD_UNFXMT         (0xc<<24)
487
#define PCL_CMD_PCI_TO_LBUS    (0x8<<24)
488
#define PCL_CMD_LBUS_TO_PCI    (0x9<<24)
489
 
490
/* aux commands */
491
#define PCL_CMD_NOP            (0x0<<24)
492
#define PCL_CMD_LOAD           (0x3<<24)
493
#define PCL_CMD_STOREQ         (0x4<<24)
494
#define PCL_CMD_STORED         (0xb<<24)
495
#define PCL_CMD_STORE0         (0x5<<24)
496
#define PCL_CMD_STORE1         (0x6<<24)
497
#define PCL_CMD_COMPARE        (0xe<<24)
498
#define PCL_CMD_SWAP_COMPARE   (0xf<<24)
499
#define PCL_CMD_ADD            (0xd<<24)
500
#define PCL_CMD_BRANCH         (0x7<<24)
501
 
502
/* BRANCH condition codes */
503
#define PCL_COND_DMARDY_SET    (0x1<<20)
504
#define PCL_COND_DMARDY_CLEAR  (0x2<<20)
505
 
506
#define PCL_GEN_INTR           (1<<19)
507
#define PCL_LAST_BUFF          (1<<18)
508
#define PCL_LAST_CMD           (PCL_LAST_BUFF)
509
#define PCL_WAITSTAT           (1<<17)
510
#define PCL_BIGENDIAN          (1<<16)
511
#define PCL_ISOMODE            (1<<12)
512
 
513
 
514
#define _(x) (__constant_cpu_to_be32(x))
515
 
516
static quadlet_t lynx_csr_rom[] = {
517
/* bus info block     offset (hex) */
518
        _(0x04046aaf), /* info/CRC length, CRC              400  */
519
        _(0x31333934), /* 1394 magic number                 404  */
520
        _(0xf064a000), /* misc. settings                    408  */
521
        _(0x08002850), /* vendor ID, chip ID high           40c  */
522
        _(0x0000ffff), /* chip ID low                       410  */
523
/* root directory */
524
        _(0x00095778), /* directory length, CRC             414  */
525
        _(0x03080028), /* vendor ID (Texas Instr.)          418  */
526
        _(0x81000008), /* offset to textual ID              41c  */
527
        _(0x0c000200), /* node capabilities                 420  */
528
        _(0x8d00000e), /* offset to unique ID               424  */
529
        _(0xc7000010), /* offset to module independent info 428  */
530
        _(0x04000000), /* module hardware version           42c  */
531
        _(0x81000014), /* offset to textual ID              430  */
532
        _(0x09000000), /* node hardware version             434  */
533
        _(0x81000018), /* offset to textual ID              438  */
534
/* module vendor ID textual */
535
        _(0x00070812), /* CRC length, CRC                   43c  */
536
        _(0x00000000), /*                                   440  */
537
        _(0x00000000), /*                                   444  */
538
        _(0x54455841), /* "Texas Instruments"               448  */
539
        _(0x5320494e), /*                                   44c  */
540
        _(0x53545255), /*                                   450  */
541
        _(0x4d454e54), /*                                   454  */
542
        _(0x53000000), /*                                   458  */
543
/* node unique ID leaf */
544
        _(0x00022ead), /* CRC length, CRC                   45c  */
545
        _(0x08002850), /* vendor ID, chip ID high           460  */
546
        _(0x0000ffff), /* chip ID low                       464  */
547
/* module dependent info */
548
        _(0x0005d837), /* CRC length, CRC                   468  */
549
        _(0x81000012), /* offset to module textual ID       46c  */
550
        _(0x81000017), /* textual descriptor                470  */
551
        _(0x39010000), /* SRAM size                         474  */
552
        _(0x3a010000), /* AUXRAM size                       478  */
553
        _(0x3b000000), /* AUX device                        47c  */
554
/* module textual ID */
555
        _(0x000594df), /* CRC length, CRC                   480  */
556
        _(0x00000000), /*                                   484  */
557
        _(0x00000000), /*                                   488  */
558
        _(0x54534231), /* "TSB12LV21"                       48c  */
559
        _(0x324c5632), /*                                   490  */
560
        _(0x31000000), /*                                   494  */
561
/* part number */
562
        _(0x00068405), /* CRC length, CRC                   498  */
563
        _(0x00000000), /*                                   49c  */
564
        _(0x00000000), /*                                   4a0  */
565
        _(0x39383036), /* "9806000-0001"                    4a4  */
566
        _(0x3030302d), /*                                   4a8  */
567
        _(0x30303031), /*                                   4ac  */
568
        _(0x20000001), /*                                   4b0  */
569
/* module hardware version textual */
570
        _(0x00056501), /* CRC length, CRC                   4b4  */
571
        _(0x00000000), /*                                   4b8  */
572
        _(0x00000000), /*                                   4bc  */
573
        _(0x5453424b), /* "TSBKPCITST"                      4c0  */
574
        _(0x50434954), /*                                   4c4  */
575
        _(0x53540000), /*                                   4c8  */
576
/* node hardware version textual */
577
        _(0x0005d805), /* CRC length, CRC                   4d0  */
578
        _(0x00000000), /*                                   4d4  */
579
        _(0x00000000), /*                                   4d8  */
580
        _(0x54534232), /* "TSB21LV03"                       4dc  */
581
        _(0x314c5630), /*                                   4e0  */
582
        _(0x33000000)  /*                                   4e4  */
583
};
584
 
585
#undef _

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