OpenCores
URL https://opencores.org/ocsvn/or1k/or1k/trunk

Subversion Repositories or1k

[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [media/] [video/] [saa7196.h] - Blame information for rev 1774

Go to most recent revision | Details | Compare with Previous | View Log

Line No. Rev Author Line
1 1275 phoenix
/*
2
    Definitions for the Philips SAA7196 digital video decoder,
3
    scaler, and clock generator circuit (DESCpro), as used in
4
    the PlanB video input of the Powermac 7x00/8x00 series.
5
 
6
    Copyright (C) 1998 - 2002 Michel Lanners <mailto:mlan@cpu.lu>
7
 
8
    The register defines are shamelessly copied from the meteor
9
    driver out of FreeBSD (with permission),
10
    and are copyrighted (c) 1995 Mark Tinguely and Jim Lowe
11
    (Thanks !)
12
 
13
    The default values used for PlanB are my mistakes.
14
*/
15
 
16
/* $Id: saa7196.h,v 1.1.1.1 2004-04-15 02:19:21 phoenix Exp $ */
17
 
18
#ifndef _SAA7196_H_
19
#define _SAA7196_H_
20
 
21
#define SAA7196_NUMREGS 0x31    /* Number of registers (used)*/
22
#define NUM_SUPPORTED_NORM 3    /* Number of supported norms by PlanB */
23
 
24
/* Decoder part: */
25
#define SAA7196_IDEL    0x00    /* Increment delay */
26
#define SAA7196_HSB5    0x01    /* H-sync begin; 50 hz */
27
#define SAA7196_HSS5    0x02    /* H-sync stop; 50 hz */
28
#define SAA7196_HCB5    0x03    /* H-clamp begin; 50 hz */
29
#define SAA7196_HCS5    0x04    /* H-clamp stop; 50 hz */
30
#define SAA7196_HSP5    0x05    /* H-sync after PHI1; 50 hz */
31
#define SAA7196_LUMC    0x06    /* Luminance control */
32
#define SAA7196_HUEC    0x07    /* Hue control */
33
#define SAA7196_CKTQ    0x08    /* Colour Killer Threshold QAM (PAL, NTSC) */
34
#define SAA7196_CKTS    0x09    /* Colour Killer Threshold SECAM */
35
#define SAA7196_PALS    0x0a    /* PAL switch sensitivity */
36
#define SAA7196_SECAMS  0x0b    /* SECAM switch sensitivity */
37
#define SAA7196_CGAINC  0x0c    /* Chroma gain control */
38
#define SAA7196_STDC    0x0d    /* Standard/Mode control */
39
#define SAA7196_IOCC    0x0e    /* I/O and Clock Control */
40
#define SAA7196_CTRL1   0x0f    /* Control #1 */
41
#define SAA7196_CTRL2   0x10    /* Control #2 */
42
#define SAA7196_CGAINR  0x11    /* Chroma Gain Reference */
43
#define SAA7196_CSAT    0x12    /* Chroma Saturation */
44
#define SAA7196_CONT    0x13    /* Luminance Contrast */
45
#define SAA7196_HSB6    0x14    /* H-sync begin; 60 hz */
46
#define SAA7196_HSS6    0x15    /* H-sync stop; 60 hz */
47
#define SAA7196_HCB6    0x16    /* H-clamp begin; 60 hz */
48
#define SAA7196_HCS6    0x17    /* H-clamp stop; 60 hz */
49
#define SAA7196_HSP6    0x18    /* H-sync after PHI1; 60 hz */
50
#define SAA7196_BRIG    0x19    /* Luminance Brightness */
51
 
52
/* Scaler part: */
53
#define SAA7196_FMTS    0x20    /* Formats and sequence */
54
#define SAA7196_OUTPIX  0x21    /* Output data pixel/line */
55
#define SAA7196_INPIX   0x22    /* Input data pixel/line */
56
#define SAA7196_HWS     0x23    /* Horiz. window start */
57
#define SAA7196_HFILT   0x24    /* Horiz. filter */
58
#define SAA7196_OUTLINE 0x25    /* Output data lines/field */
59
#define SAA7196_INLINE  0x26    /* Input data lines/field */
60
#define SAA7196_VWS     0x27    /* Vertical window start */
61
#define SAA7196_VYP     0x28    /* AFS/vertical Y processing */
62
#define SAA7196_VBS     0x29    /* Vertical Bypass start */
63
#define SAA7196_VBCNT   0x2a    /* Vertical Bypass count */
64
#define SAA7196_VBP     0x2b    /* veritcal Bypass Polarity */
65
#define SAA7196_VLOW    0x2c    /* Colour-keying lower V limit */
66
#define SAA7196_VHIGH   0x2d    /* Colour-keying upper V limit */
67
#define SAA7196_ULOW    0x2e    /* Colour-keying lower U limit */
68
#define SAA7196_UHIGH   0x2f    /* Colour-keying upper U limit */
69
#define SAA7196_DPATH   0x30    /* Data path setting  */
70
 
71
/* Initialization default values: */
72
 
73
unsigned char saa_regs[NUM_SUPPORTED_NORM][SAA7196_NUMREGS] = {
74
 
75
/* PAL, 768x576 (no scaling), composite video-in */
76
/* Decoder: */
77
      { 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x63, 0xff,
78
        0xfe, 0xf0, 0xfe, 0xe0, 0x20, 0x06, 0x3b, 0x98,
79
        0x00, 0x59, 0x41, 0x45, 0x34, 0x0a, 0xf4, 0xd2,
80
        0xe9, 0xa2,
81
/* Padding */
82
                    0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
83
/* Scaler: */
84
        0x72, 0x80, 0x00, 0x03, 0x8d, 0x20, 0x20, 0x12,
85
        0xa5, 0x12, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
86
        0x87 },
87
 
88
/* NTSC, 640x480? (no scaling), composite video-in */
89
/* Decoder: */
90
      { 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x50, 0x00,
91
        0xf8, 0xf0, 0xfe, 0xe0, 0x00, 0x06, 0x3b, 0x98,
92
        0x00, 0x2c, 0x3d, 0x40, 0x34, 0x0a, 0xf4, 0xd2,
93
        0xe9, 0x98,
94
/* Padding */
95
                    0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
96
/* Scaler: */
97
        0x72, 0x80, 0x80, 0x03, 0x89, 0xf0, 0xf0, 0x0d,
98
        0xa0, 0x0d, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
99
        0x87 },
100
 
101
/* SECAM, 768x576 (no scaling), composite video-in */
102
/* Decoder: */
103
      { 0x50, 0x30, 0x00, 0xe8, 0xb6, 0xe5, 0x63, 0xff,
104
        0xfe, 0xf0, 0xfe, 0xe0, 0x20, 0x07, 0x3b, 0x98,
105
        0x00, 0x59, 0x41, 0x45, 0x34, 0x0a, 0xf4, 0xd2,
106
        0xe9, 0xa2,
107
/* Padding */
108
                    0x80, 0x80, 0x80, 0x80, 0x80, 0x80,
109
/* Scaler: */
110
        0x72, 0x80, 0x00, 0x03, 0x8d, 0x20, 0x20, 0x12,
111
        0xa5, 0x12, 0x00, 0x00, 0x04, 0x00, 0x04, 0x00,
112
        0x87 }
113
        };
114
 
115
#endif /* _SAA7196_H_ */

powered by: WebSVN 2.1.0

© copyright 1999-2024 OpenCores.org, equivalent to Oliscience, all rights reserved. OpenCores®, registered trademark.