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phoenix |
/************************************************************************/
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/* */
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/* es4h.h: Hardware definition of the ES/4h Ethernet Switch, from */
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/* both the host and the 3051's point of view. */
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/* NOTE: this name is a misnomer now that there is a PCI */
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/* board. Everything that says "es4h" should really be */
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/* "se4". But we'll keep the old name for now. */
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/* */
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/* $Id: dgrs_es4h.h,v 1.1.1.1 2004-04-15 01:40:44 phoenix Exp $ */
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/* */
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/************************************************************************/
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/************************************************************************/
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/* */
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/* EISA I/O Registers. These are located at 0x1000 * slot-number */
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/* plus the indicated address. I.E. 0x4000-0x4009 for slot 4. */
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/* */
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/************************************************************************/
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#define ES4H_MANUFmsb 0x00 /* Read-only */
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#define ES4H_MANUFlsb 0x01 /* Read-only */
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# define ES4H_MANUF_CODE 0x1049 /* = "DBI" */
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#define ES4H_PRODUCT 0x02 /* Read-only */
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# define ES4H_PRODUCT_CODE 0x0A
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# define EPC_PRODUCT_CODE 0x03
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#define ES4H_REVISION 0x03 /* Read-only */
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# define ES4H_REVISION_CODE 0x01
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#define ES4H_EC 0x04 /* EISA Control */
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# define ES4H_EC_RESET 0x04 /* WO, EISA reset */
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# define ES4H_EC_ENABLE 0x01 /* RW, EISA enable - set to */
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/* 1 before memory enable */
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#define ES4H_PC 0x05 /* Processor Control */
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# define ES4H_PC_RESET 0x04 /* RW, 3051 reset */
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# define ES4H_PC_INT 0x08 /* WO, assert 3051 intr. 3 */
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#define ES4H_MW 0x06 /* Memory Window select and enable */
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# define ES4H_MW_ENABLE 0x80 /* WO, enable memory */
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# define ES4H_MW_SELECT_MASK 0x1f /* WO, 32k window selected */
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#define ES4H_IS 0x07 /* Interrupt, addr select */
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# define ES4H_IS_INTMASK 0x07 /* WO, interrupt select */
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# define ES4H_IS_INTOFF 0x00 /* No IRQ */
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# define ES4H_IS_INT3 0x03 /* IRQ 3 */
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# define ES4H_IS_INT5 0x02 /* IRQ 5 */
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# define ES4H_IS_INT7 0x01 /* IRQ 7 */
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# define ES4H_IS_INT10 0x04 /* IRQ 10 */
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# define ES4H_IS_INT11 0x05 /* IRQ 11 */
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# define ES4H_IS_INT12 0x06 /* IRQ 12 */
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# define ES4H_IS_INT15 0x07 /* IRQ 15 */
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# define ES4H_IS_INTACK 0x10 /* WO, interrupt ack */
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# define ES4H_IS_INTPEND 0x10 /* RO, interrupt pending */
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# define ES4H_IS_LINEAR 0x40 /* WO, no memory windowing */
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# define ES4H_IS_AS15 0x80 /* RW, address select bit 15 */
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#define ES4H_AS_23_16 0x08 /* Address select bits 23-16 */
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#define ES4H_AS_31_24 0x09 /* Address select bits 31-24 */
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#define ES4H_IO_MAX 0x09 /* Size of I/O space */
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/*
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* PCI
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*/
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#define SE6_RESET PLX_USEROUT
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/************************************************************************/
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/* */
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/* 3051 Memory Map */
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/* */
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/* Note: 3051 has 4K I-cache, 2K D-cache. 1 cycle is 50 nsec. */
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/* */
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/************************************************************************/
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#define SE4_NPORTS 4 /* # of ethernet ports */
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#define SE6_NPORTS 6 /* # of ethernet ports */
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#define SE_NPORTS 6 /* Max # of ethernet ports */
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#define ES4H_RAM_BASE 0x83000000 /* Base address of RAM */
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#define ES4H_RAM_SIZE 0x00200000 /* Size of RAM (2MB) */
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#define ES4H_RAM_INTBASE 0x83800000 /* Base of int-on-write RAM */
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/* a.k.a. PKT RAM */
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/* Ethernet controllers */
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/* See: i82596.h */
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#define ES4H_ETHER0_PORT 0xA2000000
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#define ES4H_ETHER0_CMD 0xA2000100
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#define ES4H_ETHER1_PORT 0xA2000200
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#define ES4H_ETHER1_CMD 0xA2000300
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#define ES4H_ETHER2_PORT 0xA2000400
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#define ES4H_ETHER2_CMD 0xA2000500
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#define ES4H_ETHER3_PORT 0xA2000600
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#define ES4H_ETHER3_CMD 0xA2000700
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#define ES4H_ETHER4_PORT 0xA2000800 /* RS SE-6 only */
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#define ES4H_ETHER4_CMD 0xA2000900 /* RS SE-6 only */
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#define ES4H_ETHER5_PORT 0xA2000A00 /* RS SE-6 only */
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#define ES4H_ETHER5_CMD 0xA2000B00 /* RS SE-6 only */
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#define ES4H_I8254 0xA2040000 /* 82C54 timers */
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/* See: i8254.h */
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#define SE4_I8254_HZ (23000000/4) /* EISA clock input freq. */
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#define SE4_IDT_HZ (46000000) /* EISA CPU freq. */
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#define SE6_I8254_HZ (20000000/4) /* PCI clock input freq. */
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#define SE6_IDT_HZ (50000000) /* PCI CPU freq. */
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#define ES4H_I8254_HZ (23000000/4) /* EISA clock input freq. */
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#define ES4H_GPP 0xA2050000 /* General purpose port */
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/*
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* SE-4 (EISA) GPP bits
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*/
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# define ES4H_GPP_C0_100 0x0001 /* WO, Chan 0: 100 ohm TP */
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# define ES4H_GPP_C0_SQE 0x0002 /* WO, Chan 0: normal squelch */
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# define ES4H_GPP_C1_100 0x0004 /* WO, Chan 1: 100 ohm TP */
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# define ES4H_GPP_C1_SQE 0x0008 /* WO, Chan 1: normal squelch */
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# define ES4H_GPP_C2_100 0x0010 /* WO, Chan 2: 100 ohm TP */
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# define ES4H_GPP_C2_SQE 0x0020 /* WO, Chan 2: normal squelch */
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# define ES4H_GPP_C3_100 0x0040 /* WO, Chan 3: 100 ohm TP */
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# define ES4H_GPP_C3_SQE 0x0080 /* WO, Chan 3: normal squelch */
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# define ES4H_GPP_SQE 0x00AA /* WO, All: normal squelch */
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# define ES4H_GPP_100 0x0055 /* WO, All: 100 ohm TP */
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# define ES4H_GPP_HOSTINT 0x0100 /* RO, cause intr. to host */
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/* Hold high > 250 nsec */
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# define SE4_GPP_EED 0x0200 /* RW, EEPROM data bit */
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# define SE4_GPP_EECS 0x0400 /* RW, EEPROM chip select */
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# define SE4_GPP_EECK 0x0800 /* RW, EEPROM clock */
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/*
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* SE-6 (PCI) GPP bits
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*/
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# define SE6_GPP_EED 0x0001 /* RW, EEPROM data bit */
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# define SE6_GPP_EECS 0x0002 /* RW, EEPROM chip select */
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# define SE6_GPP_EECK 0x0004 /* RW, EEPROM clock */
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# define SE6_GPP_LINK 0x00fc /* R, Link status LEDs */
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#define ES4H_INTVEC 0xA2060000 /* RO: Interrupt Vector */
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# define ES4H_IV_DMA0 0x01 /* Chan 0 DMA interrupt */
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# define ES4H_IV_PKT0 0x02 /* Chan 0 PKT interrupt */
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# define ES4H_IV_DMA1 0x04 /* Chan 1 DMA interrupt */
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# define ES4H_IV_PKT1 0x08 /* Chan 1 PKT interrupt */
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# define ES4H_IV_DMA2 0x10 /* Chan 2 DMA interrupt */
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# define ES4H_IV_PKT2 0x20 /* Chan 2 PKT interrupt */
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# define ES4H_IV_DMA3 0x40 /* Chan 3 DMA interrupt */
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# define ES4H_IV_PKT3 0x80 /* Chan 3 PKT interrupt */
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#define ES4H_INTACK 0xA2060000 /* WO: Interrupt Ack */
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# define ES4H_INTACK_8254 0x01 /* Real Time Clock (int 0) */
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# define ES4H_INTACK_HOST 0x02 /* Host (int 1) */
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# define ES4H_INTACK_PKT0 0x04 /* Chan 0 Pkt (int 2) */
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# define ES4H_INTACK_PKT1 0x08 /* Chan 1 Pkt (int 3) */
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# define ES4H_INTACK_PKT2 0x10 /* Chan 2 Pkt (int 4) */
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# define ES4H_INTACK_PKT3 0x20 /* Chan 3 Pkt (int 5) */
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#define SE6_PLX 0xA2070000 /* PLX 9060, SE-6 (PCI) only */
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/* see plx9060.h */
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#define SE6_PCI_VENDOR_ID 0x114F /* Digi PCI vendor ID */
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#define SE6_PCI_DEVICE_ID 0x0003 /* RS SE-6 device ID */
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#define SE6_PCI_ID ((SE6_PCI_DEVICE_ID<<16) | SE6_PCI_VENDOR_ID)
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/*
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* IDT Interrupts
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*/
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#define ES4H_INT_8254 IDT_INT0
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#define ES4H_INT_HOST IDT_INT1
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#define ES4H_INT_ETHER0 IDT_INT2
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#define ES4H_INT_ETHER1 IDT_INT3
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#define ES4H_INT_ETHER2 IDT_INT4
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#define ES4H_INT_ETHER3 IDT_INT5
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/*
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* Because there are differences between the SE-4 and the SE-6,
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* we assume that the following globals will be set up at init
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* time in main.c to containt the appropriate constants from above
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*/
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extern ushort Gpp; /* Softcopy of GPP register */
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extern ushort EEck; /* Clock bit */
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extern ushort EEcs; /* CS bit */
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extern ushort EEd; /* Data bit */
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extern ulong I8254_Hz; /* i8254 input frequency */
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extern ulong IDT_Hz; /* IDT CPU frequency */
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extern int Nports; /* Number of ethernet controllers */
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extern int Nchan; /* Nports+1 */
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