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1275 |
phoenix |
/*
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A Davicom DM9102/DM9102A/DM9102A+DM9801/DM9102A+DM9802 NIC fast
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ethernet driver for Linux.
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Copyright (C) 1997 Sten Wang
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This program is free software; you can redistribute it and/or
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modify it under the terms of the GNU General Public License
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as published by the Free Software Foundation; either version 2
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of the License, or (at your option) any later version.
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This program is distributed in the hope that it will be useful,
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but WITHOUT ANY WARRANTY; without even the implied warranty of
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MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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GNU General Public License for more details.
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DAVICOM Web-Site: www.davicom.com.tw
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Author: Sten Wang, 886-3-5798797-8517, E-mail: sten_wang@davicom.com.tw
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Maintainer: Tobias Ringstrom <tori@unhappy.mine.nu>
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(C)Copyright 1997-1998 DAVICOM Semiconductor,Inc. All Rights Reserved.
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Marcelo Tosatti <marcelo@conectiva.com.br> :
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Made it compile in 2.3 (device to net_device)
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Alan Cox <alan@redhat.com> :
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Cleaned up for kernel merge.
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Removed the back compatibility support
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Reformatted, fixing spelling etc as I went
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Removed IRQ 0-15 assumption
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Jeff Garzik <jgarzik@pobox.com> :
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Updated to use new PCI driver API.
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Resource usage cleanups.
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Report driver version to user.
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Tobias Ringstrom <tori@unhappy.mine.nu> :
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Cleaned up and added SMP safety. Thanks go to Jeff Garzik,
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Andrew Morton and Frank Davis for the SMP safety fixes.
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Vojtech Pavlik <vojtech@suse.cz> :
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Cleaned up pointer arithmetics.
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Fixed a lot of 64bit issues.
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Cleaned up printk()s a bit.
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Fixed some obvious big endian problems.
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Tobias Ringstrom <tori@unhappy.mine.nu> :
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Use time_after for jiffies calculation. Added ethtool
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support. Updated PCI resource allocation. Do not
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forget to unmap PCI mapped skbs.
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Alan Cox <alan@redhat.com>
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Added new PCI identifiers provided by Clear Zhang at ALi
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for their 1563 ethernet device.
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TODO
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Implement pci_driver::suspend() and pci_driver::resume()
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power management methods.
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Check on 64 bit boxes.
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Check and fix on big endian boxes.
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Test and make sure PCI latency is now correct for all cases.
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*/
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#define DRV_NAME "dmfe"
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#define DRV_VERSION "1.36.4"
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#define DRV_RELDATE "2002-01-17"
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/string.h>
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#include <linux/timer.h>
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#include <linux/ptrace.h>
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#include <linux/errno.h>
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#include <linux/ioport.h>
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#include <linux/slab.h>
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#include <linux/interrupt.h>
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#include <linux/pci.h>
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#include <linux/init.h>
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#include <linux/version.h>
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#include <linux/netdevice.h>
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#include <linux/etherdevice.h>
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#include <linux/ethtool.h>
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#include <linux/skbuff.h>
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#include <linux/delay.h>
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#include <linux/spinlock.h>
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#include <linux/crc32.h>
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#include <asm/processor.h>
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#include <asm/bitops.h>
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#include <asm/io.h>
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#include <asm/dma.h>
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#include <asm/uaccess.h>
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/* Board/System/Debug information/definition ---------------- */
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#define PCI_DM9132_ID 0x91321282 /* Davicom DM9132 ID */
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#define PCI_DM9102_ID 0x91021282 /* Davicom DM9102 ID */
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#define PCI_DM9100_ID 0x91001282 /* Davicom DM9100 ID */
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#define PCI_DM9009_ID 0x90091282 /* Davicom DM9009 ID */
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#define DM9102_IO_SIZE 0x80
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#define DM9102A_IO_SIZE 0x100
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#define TX_MAX_SEND_CNT 0x1 /* Maximum tx packet per time */
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#define TX_DESC_CNT 0x10 /* Allocated Tx descriptors */
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#define RX_DESC_CNT 0x20 /* Allocated Rx descriptors */
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#define TX_FREE_DESC_CNT (TX_DESC_CNT - 2) /* Max TX packet count */
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#define TX_WAKE_DESC_CNT (TX_DESC_CNT - 3) /* TX wakeup count */
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#define DESC_ALL_CNT (TX_DESC_CNT + RX_DESC_CNT)
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#define TX_BUF_ALLOC 0x600
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#define RX_ALLOC_SIZE 0x620
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#define DM910X_RESET 1
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#define CR0_DEFAULT 0x00E00000 /* TX & RX burst mode */
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#define CR6_DEFAULT 0x00080000 /* HD */
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#define CR7_DEFAULT 0x180c1
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#define CR15_DEFAULT 0x06 /* TxJabber RxWatchdog */
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#define TDES0_ERR_MASK 0x4302 /* TXJT, LC, EC, FUE */
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#define MAX_PACKET_SIZE 1514
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#define DMFE_MAX_MULTICAST 14
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#define RX_COPY_SIZE 100
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#define MAX_CHECK_PACKET 0x8000
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#define DM9801_NOISE_FLOOR 8
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#define DM9802_NOISE_FLOOR 5
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#define DMFE_10MHF 0
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#define DMFE_100MHF 1
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#define DMFE_10MFD 4
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#define DMFE_100MFD 5
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#define DMFE_AUTO 8
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#define DMFE_1M_HPNA 0x10
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#define DMFE_TXTH_72 0x400000 /* TX TH 72 byte */
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#define DMFE_TXTH_96 0x404000 /* TX TH 96 byte */
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#define DMFE_TXTH_128 0x0000 /* TX TH 128 byte */
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#define DMFE_TXTH_256 0x4000 /* TX TH 256 byte */
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#define DMFE_TXTH_512 0x8000 /* TX TH 512 byte */
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#define DMFE_TXTH_1K 0xC000 /* TX TH 1K byte */
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#define DMFE_TIMER_WUT (jiffies + HZ * 1)/* timer wakeup time : 1 second */
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#define DMFE_TX_TIMEOUT ((3*HZ)/2) /* tx packet time-out time 1.5 s" */
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#define DMFE_TX_KICK (HZ/2) /* tx packet Kick-out time 0.5 s" */
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#define DMFE_DBUG(dbug_now, msg, value) if (dmfe_debug || (dbug_now)) printk(KERN_ERR DRV_NAME ": %s %lx\n", (msg), (long) (value))
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#define SHOW_MEDIA_TYPE(mode) printk(KERN_ERR DRV_NAME ": Change Speed to %sMhz %s duplex\n",mode & 1 ?"100":"10", mode & 4 ? "full":"half");
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/* CR9 definition: SROM/MII */
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#define CR9_SROM_READ 0x4800
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#define CR9_SRCS 0x1
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#define CR9_SRCLK 0x2
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#define CR9_CRDOUT 0x8
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#define SROM_DATA_0 0x0
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#define SROM_DATA_1 0x4
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#define PHY_DATA_1 0x20000
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#define PHY_DATA_0 0x00000
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#define MDCLKH 0x10000
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#define PHY_POWER_DOWN 0x800
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#define SROM_V41_CODE 0x14
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#define SROM_CLK_WRITE(data, ioaddr) outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS|CR9_SRCLK,ioaddr);udelay(5);outl(data|CR9_SROM_READ|CR9_SRCS,ioaddr);udelay(5);
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#define __CHK_IO_SIZE(pci_id, dev_rev) ( ((pci_id)==PCI_DM9132_ID) || ((dev_rev) >= 0x02000030) ) ? DM9102A_IO_SIZE: DM9102_IO_SIZE
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#define CHK_IO_SIZE(pci_dev, dev_rev) __CHK_IO_SIZE(((pci_dev)->device << 16) | (pci_dev)->vendor, dev_rev)
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/* Sten Check */
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#define DEVICE net_device
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/* Structure/enum declaration ------------------------------- */
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struct tx_desc {
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u32 tdes0, tdes1, tdes2, tdes3; /* Data for the card */
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char *tx_buf_ptr; /* Data for us */
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struct tx_desc *next_tx_desc;
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} __attribute__(( aligned(32) ));
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struct rx_desc {
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u32 rdes0, rdes1, rdes2, rdes3; /* Data for the card */
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struct sk_buff *rx_skb_ptr; /* Data for us */
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struct rx_desc *next_rx_desc;
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} __attribute__(( aligned(32) ));
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struct dmfe_board_info {
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u32 chip_id; /* Chip vendor/Device ID */
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u32 chip_revision; /* Chip revision */
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struct DEVICE *next_dev; /* next device */
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struct pci_dev *pdev; /* PCI device */
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spinlock_t lock;
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long ioaddr; /* I/O base address */
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u32 cr0_data;
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u32 cr5_data;
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u32 cr6_data;
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u32 cr7_data;
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u32 cr15_data;
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/* pointer for memory physical address */
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dma_addr_t buf_pool_dma_ptr; /* Tx buffer pool memory */
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dma_addr_t buf_pool_dma_start; /* Tx buffer pool align dword */
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dma_addr_t desc_pool_dma_ptr; /* descriptor pool memory */
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dma_addr_t first_tx_desc_dma;
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dma_addr_t first_rx_desc_dma;
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/* descriptor pointer */
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unsigned char *buf_pool_ptr; /* Tx buffer pool memory */
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unsigned char *buf_pool_start; /* Tx buffer pool align dword */
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unsigned char *desc_pool_ptr; /* descriptor pool memory */
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struct tx_desc *first_tx_desc;
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struct tx_desc *tx_insert_ptr;
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struct tx_desc *tx_remove_ptr;
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struct rx_desc *first_rx_desc;
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struct rx_desc *rx_insert_ptr;
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struct rx_desc *rx_ready_ptr; /* packet come pointer */
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unsigned long tx_packet_cnt; /* transmitted packet count */
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unsigned long tx_queue_cnt; /* wait to send packet count */
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unsigned long rx_avail_cnt; /* available rx descriptor count */
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unsigned long interval_rx_cnt; /* rx packet count a callback time */
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u16 HPNA_command; /* For HPNA register 16 */
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u16 HPNA_timer; /* For HPNA remote device check */
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u16 dbug_cnt;
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u16 NIC_capability; /* NIC media capability */
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u16 PHY_reg4; /* Saved Phyxcer register 4 value */
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u8 HPNA_present; /* 0:none, 1:DM9801, 2:DM9802 */
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u8 chip_type; /* Keep DM9102A chip type */
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u8 media_mode; /* user specify media mode */
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u8 op_mode; /* real work media mode */
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u8 phy_addr;
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u8 link_failed; /* Ever link failed */
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u8 wait_reset; /* Hardware failed, need to reset */
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u8 dm910x_chk_mode; /* Operating mode check */
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u8 first_in_callback; /* Flag to record state */
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struct timer_list timer;
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/* System defined statistic counter */
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struct net_device_stats stats;
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/* Driver defined statistic counter */
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unsigned long tx_fifo_underrun;
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unsigned long tx_loss_carrier;
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unsigned long tx_no_carrier;
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unsigned long tx_late_collision;
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unsigned long tx_excessive_collision;
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unsigned long tx_jabber_timeout;
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unsigned long reset_count;
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unsigned long reset_cr8;
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unsigned long reset_fatal;
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unsigned long reset_TXtimeout;
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/* NIC SROM data */
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unsigned char srom[128];
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};
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enum dmfe_offsets {
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DCR0 = 0x00, DCR1 = 0x08, DCR2 = 0x10, DCR3 = 0x18, DCR4 = 0x20,
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DCR5 = 0x28, DCR6 = 0x30, DCR7 = 0x38, DCR8 = 0x40, DCR9 = 0x48,
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DCR10 = 0x50, DCR11 = 0x58, DCR12 = 0x60, DCR13 = 0x68, DCR14 = 0x70,
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DCR15 = 0x78
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};
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enum dmfe_CR6_bits {
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CR6_RXSC = 0x2, CR6_PBF = 0x8, CR6_PM = 0x40, CR6_PAM = 0x80,
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CR6_FDM = 0x200, CR6_TXSC = 0x2000, CR6_STI = 0x100000,
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CR6_SFT = 0x200000, CR6_RXA = 0x40000000, CR6_NO_PURGE = 0x20000000
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};
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| 273 |
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/* Global variable declaration ----------------------------- */
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static int __devinitdata printed_version;
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static char version[] __devinitdata =
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KERN_INFO DRV_NAME ": Davicom DM9xxx net driver, version "
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DRV_VERSION " (" DRV_RELDATE ")\n";
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static int dmfe_debug;
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static unsigned char dmfe_media_mode = DMFE_AUTO;
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static u32 dmfe_cr6_user_set;
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| 283 |
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/* For module input parameter */
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| 284 |
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static int debug;
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| 285 |
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static u32 cr6set;
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static unsigned char mode = 8;
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static u8 chkmode = 1;
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| 288 |
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static u8 HPNA_mode; /* Default: Low Power/High Speed */
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| 289 |
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static u8 HPNA_rx_cmd; /* Default: Disable Rx remote command */
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static u8 HPNA_tx_cmd; /* Default: Don't issue remote command */
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static u8 HPNA_NoiseFloor; /* Default: HPNA NoiseFloor */
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static u8 SF_mode; /* Special Function: 1:VLAN, 2:RX Flow Control
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4: TX pause packet */
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/* function declaration ------------------------------------- */
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static int dmfe_open(struct DEVICE *);
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static int dmfe_start_xmit(struct sk_buff *, struct DEVICE *);
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static int dmfe_stop(struct DEVICE *);
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static struct net_device_stats * dmfe_get_stats(struct DEVICE *);
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static void dmfe_set_filter_mode(struct DEVICE *);
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static struct ethtool_ops netdev_ethtool_ops;
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static u16 read_srom_word(long ,int);
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|
|
static void dmfe_interrupt(int , void *, struct pt_regs *);
|
| 305 |
|
|
static void dmfe_descriptor_init(struct dmfe_board_info *, unsigned long);
|
| 306 |
|
|
static void allocate_rx_buffer(struct dmfe_board_info *);
|
| 307 |
|
|
static void update_cr6(u32, unsigned long);
|
| 308 |
|
|
static void send_filter_frame(struct DEVICE * ,int);
|
| 309 |
|
|
static void dm9132_id_table(struct DEVICE * ,int);
|
| 310 |
|
|
static u16 phy_read(unsigned long, u8, u8, u32);
|
| 311 |
|
|
static void phy_write(unsigned long, u8, u8, u16, u32);
|
| 312 |
|
|
static void phy_write_1bit(unsigned long, u32);
|
| 313 |
|
|
static u16 phy_read_1bit(unsigned long);
|
| 314 |
|
|
static u8 dmfe_sense_speed(struct dmfe_board_info *);
|
| 315 |
|
|
static void dmfe_process_mode(struct dmfe_board_info *);
|
| 316 |
|
|
static void dmfe_timer(unsigned long);
|
| 317 |
|
|
static void dmfe_rx_packet(struct DEVICE *, struct dmfe_board_info *);
|
| 318 |
|
|
static void dmfe_free_tx_pkt(struct DEVICE *, struct dmfe_board_info *);
|
| 319 |
|
|
static void dmfe_reuse_skb(struct dmfe_board_info *, struct sk_buff *);
|
| 320 |
|
|
static void dmfe_dynamic_reset(struct DEVICE *);
|
| 321 |
|
|
static void dmfe_free_rxbuffer(struct dmfe_board_info *);
|
| 322 |
|
|
static void dmfe_init_dm910x(struct DEVICE *);
|
| 323 |
|
|
static inline u32 cal_CRC(unsigned char *, unsigned int, u8);
|
| 324 |
|
|
static void dmfe_parse_srom(struct dmfe_board_info *);
|
| 325 |
|
|
static void dmfe_program_DM9801(struct dmfe_board_info *, int);
|
| 326 |
|
|
static void dmfe_program_DM9802(struct dmfe_board_info *);
|
| 327 |
|
|
static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * );
|
| 328 |
|
|
static void dmfe_set_phyxcer(struct dmfe_board_info *);
|
| 329 |
|
|
|
| 330 |
|
|
/* DM910X network baord routine ---------------------------- */
|
| 331 |
|
|
|
| 332 |
|
|
/*
|
| 333 |
|
|
* Search DM910X board ,allocate space and register it
|
| 334 |
|
|
*/
|
| 335 |
|
|
|
| 336 |
|
|
static int __devinit dmfe_init_one (struct pci_dev *pdev,
|
| 337 |
|
|
const struct pci_device_id *ent)
|
| 338 |
|
|
{
|
| 339 |
|
|
struct dmfe_board_info *db; /* board information structure */
|
| 340 |
|
|
struct net_device *dev;
|
| 341 |
|
|
u32 dev_rev, pci_pmr;
|
| 342 |
|
|
int i, err;
|
| 343 |
|
|
|
| 344 |
|
|
DMFE_DBUG(0, "dmfe_init_one()", 0);
|
| 345 |
|
|
|
| 346 |
|
|
if (!printed_version++)
|
| 347 |
|
|
printk(version);
|
| 348 |
|
|
|
| 349 |
|
|
/* Init network device */
|
| 350 |
|
|
dev = alloc_etherdev(sizeof(*db));
|
| 351 |
|
|
if (dev == NULL)
|
| 352 |
|
|
return -ENOMEM;
|
| 353 |
|
|
SET_MODULE_OWNER(dev);
|
| 354 |
|
|
|
| 355 |
|
|
if (pci_set_dma_mask(pdev, 0xffffffff)) {
|
| 356 |
|
|
printk(KERN_WARNING DRV_NAME ": 32-bit PCI DMA not available.\n");
|
| 357 |
|
|
err = -ENODEV;
|
| 358 |
|
|
goto err_out_free;
|
| 359 |
|
|
}
|
| 360 |
|
|
|
| 361 |
|
|
/* Enable Master/IO access, Disable memory access */
|
| 362 |
|
|
err = pci_enable_device(pdev);
|
| 363 |
|
|
if (err)
|
| 364 |
|
|
goto err_out_free;
|
| 365 |
|
|
|
| 366 |
|
|
if (!pci_resource_start(pdev, 0)) {
|
| 367 |
|
|
printk(KERN_ERR DRV_NAME ": I/O base is zero\n");
|
| 368 |
|
|
err = -ENODEV;
|
| 369 |
|
|
goto err_out_disable;
|
| 370 |
|
|
}
|
| 371 |
|
|
|
| 372 |
|
|
/* Read Chip revision */
|
| 373 |
|
|
pci_read_config_dword(pdev, PCI_REVISION_ID, &dev_rev);
|
| 374 |
|
|
|
| 375 |
|
|
if (pci_resource_len(pdev, 0) < (CHK_IO_SIZE(pdev, dev_rev)) ) {
|
| 376 |
|
|
printk(KERN_ERR DRV_NAME ": Allocated I/O size too small\n");
|
| 377 |
|
|
err = -ENODEV;
|
| 378 |
|
|
goto err_out_disable;
|
| 379 |
|
|
}
|
| 380 |
|
|
|
| 381 |
|
|
#if 0 /* pci_{enable_device,set_master} sets minimum latency for us now */
|
| 382 |
|
|
|
| 383 |
|
|
/* Set Latency Timer 80h */
|
| 384 |
|
|
/* FIXME: setting values > 32 breaks some SiS 559x stuff.
|
| 385 |
|
|
Need a PCI quirk.. */
|
| 386 |
|
|
|
| 387 |
|
|
pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80);
|
| 388 |
|
|
#endif
|
| 389 |
|
|
|
| 390 |
|
|
if (pci_request_regions(pdev, DRV_NAME)) {
|
| 391 |
|
|
printk(KERN_ERR DRV_NAME ": Failed to request PCI regions\n");
|
| 392 |
|
|
err = -ENODEV;
|
| 393 |
|
|
goto err_out_disable;
|
| 394 |
|
|
}
|
| 395 |
|
|
|
| 396 |
|
|
/* Init system & device */
|
| 397 |
|
|
db = dev->priv;
|
| 398 |
|
|
|
| 399 |
|
|
/* Allocate Tx/Rx descriptor memory */
|
| 400 |
|
|
db->desc_pool_ptr = pci_alloc_consistent(pdev, sizeof(struct tx_desc) * DESC_ALL_CNT + 0x20, &db->desc_pool_dma_ptr);
|
| 401 |
|
|
db->buf_pool_ptr = pci_alloc_consistent(pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4, &db->buf_pool_dma_ptr);
|
| 402 |
|
|
|
| 403 |
|
|
db->first_tx_desc = (struct tx_desc *) db->desc_pool_ptr;
|
| 404 |
|
|
db->first_tx_desc_dma = db->desc_pool_dma_ptr;
|
| 405 |
|
|
db->buf_pool_start = db->buf_pool_ptr;
|
| 406 |
|
|
db->buf_pool_dma_start = db->buf_pool_dma_ptr;
|
| 407 |
|
|
|
| 408 |
|
|
db->chip_id = ent->driver_data;
|
| 409 |
|
|
db->ioaddr = pci_resource_start(pdev, 0);
|
| 410 |
|
|
db->chip_revision = dev_rev;
|
| 411 |
|
|
|
| 412 |
|
|
db->pdev = pdev;
|
| 413 |
|
|
|
| 414 |
|
|
dev->base_addr = db->ioaddr;
|
| 415 |
|
|
dev->irq = pdev->irq;
|
| 416 |
|
|
pci_set_drvdata(pdev, dev);
|
| 417 |
|
|
dev->open = &dmfe_open;
|
| 418 |
|
|
dev->hard_start_xmit = &dmfe_start_xmit;
|
| 419 |
|
|
dev->stop = &dmfe_stop;
|
| 420 |
|
|
dev->get_stats = &dmfe_get_stats;
|
| 421 |
|
|
dev->set_multicast_list = &dmfe_set_filter_mode;
|
| 422 |
|
|
dev->ethtool_ops = &netdev_ethtool_ops;
|
| 423 |
|
|
spin_lock_init(&db->lock);
|
| 424 |
|
|
|
| 425 |
|
|
pci_read_config_dword(pdev, 0x50, &pci_pmr);
|
| 426 |
|
|
pci_pmr &= 0x70000;
|
| 427 |
|
|
if ( (pci_pmr == 0x10000) && (dev_rev == 0x02000031) )
|
| 428 |
|
|
db->chip_type = 1; /* DM9102A E3 */
|
| 429 |
|
|
else
|
| 430 |
|
|
db->chip_type = 0;
|
| 431 |
|
|
|
| 432 |
|
|
/* read 64 word srom data */
|
| 433 |
|
|
for (i = 0; i < 64; i++)
|
| 434 |
|
|
((u16 *) db->srom)[i] = cpu_to_le16(read_srom_word(db->ioaddr, i));
|
| 435 |
|
|
|
| 436 |
|
|
/* Set Node address */
|
| 437 |
|
|
for (i = 0; i < 6; i++)
|
| 438 |
|
|
dev->dev_addr[i] = db->srom[20 + i];
|
| 439 |
|
|
|
| 440 |
|
|
err = register_netdev (dev);
|
| 441 |
|
|
if (err)
|
| 442 |
|
|
goto err_out_res;
|
| 443 |
|
|
|
| 444 |
|
|
printk(KERN_INFO "%s: Davicom DM%04lx at pci%s,",
|
| 445 |
|
|
dev->name,
|
| 446 |
|
|
ent->driver_data >> 16,
|
| 447 |
|
|
pdev->slot_name);
|
| 448 |
|
|
for (i = 0; i < 6; i++)
|
| 449 |
|
|
printk("%c%02x", i ? ':' : ' ', dev->dev_addr[i]);
|
| 450 |
|
|
printk(", irq %d.\n", dev->irq);
|
| 451 |
|
|
|
| 452 |
|
|
pci_set_master(pdev);
|
| 453 |
|
|
|
| 454 |
|
|
return 0;
|
| 455 |
|
|
|
| 456 |
|
|
err_out_res:
|
| 457 |
|
|
pci_release_regions(pdev);
|
| 458 |
|
|
err_out_disable:
|
| 459 |
|
|
pci_disable_device(pdev);
|
| 460 |
|
|
err_out_free:
|
| 461 |
|
|
pci_set_drvdata(pdev, NULL);
|
| 462 |
|
|
kfree(dev);
|
| 463 |
|
|
|
| 464 |
|
|
return err;
|
| 465 |
|
|
}
|
| 466 |
|
|
|
| 467 |
|
|
|
| 468 |
|
|
static void __devexit dmfe_remove_one (struct pci_dev *pdev)
|
| 469 |
|
|
{
|
| 470 |
|
|
struct net_device *dev = pci_get_drvdata(pdev);
|
| 471 |
|
|
struct dmfe_board_info *db = dev->priv;
|
| 472 |
|
|
|
| 473 |
|
|
DMFE_DBUG(0, "dmfe_remove_one()", 0);
|
| 474 |
|
|
|
| 475 |
|
|
if (dev) {
|
| 476 |
|
|
pci_free_consistent(db->pdev, sizeof(struct tx_desc) *
|
| 477 |
|
|
DESC_ALL_CNT + 0x20, db->desc_pool_ptr,
|
| 478 |
|
|
db->desc_pool_dma_ptr);
|
| 479 |
|
|
pci_free_consistent(db->pdev, TX_BUF_ALLOC * TX_DESC_CNT + 4,
|
| 480 |
|
|
db->buf_pool_ptr, db->buf_pool_dma_ptr);
|
| 481 |
|
|
unregister_netdev(dev);
|
| 482 |
|
|
pci_release_regions(pdev);
|
| 483 |
|
|
kfree(dev); /* free board information */
|
| 484 |
|
|
pci_set_drvdata(pdev, NULL);
|
| 485 |
|
|
}
|
| 486 |
|
|
|
| 487 |
|
|
DMFE_DBUG(0, "dmfe_remove_one() exit", 0);
|
| 488 |
|
|
}
|
| 489 |
|
|
|
| 490 |
|
|
|
| 491 |
|
|
/*
|
| 492 |
|
|
* Open the interface.
|
| 493 |
|
|
* The interface is opened whenever "ifconfig" actives it.
|
| 494 |
|
|
*/
|
| 495 |
|
|
|
| 496 |
|
|
static int dmfe_open(struct DEVICE *dev)
|
| 497 |
|
|
{
|
| 498 |
|
|
int ret;
|
| 499 |
|
|
struct dmfe_board_info *db = dev->priv;
|
| 500 |
|
|
|
| 501 |
|
|
DMFE_DBUG(0, "dmfe_open", 0);
|
| 502 |
|
|
|
| 503 |
|
|
ret = request_irq(dev->irq, &dmfe_interrupt, SA_SHIRQ, dev->name, dev);
|
| 504 |
|
|
if (ret)
|
| 505 |
|
|
return ret;
|
| 506 |
|
|
|
| 507 |
|
|
/* system variable init */
|
| 508 |
|
|
db->cr6_data = CR6_DEFAULT | dmfe_cr6_user_set;
|
| 509 |
|
|
db->tx_packet_cnt = 0;
|
| 510 |
|
|
db->tx_queue_cnt = 0;
|
| 511 |
|
|
db->rx_avail_cnt = 0;
|
| 512 |
|
|
db->link_failed = 1;
|
| 513 |
|
|
db->wait_reset = 0;
|
| 514 |
|
|
|
| 515 |
|
|
db->first_in_callback = 0;
|
| 516 |
|
|
db->NIC_capability = 0xf; /* All capability*/
|
| 517 |
|
|
db->PHY_reg4 = 0x1e0;
|
| 518 |
|
|
|
| 519 |
|
|
/* CR6 operation mode decision */
|
| 520 |
|
|
if ( !chkmode || (db->chip_id == PCI_DM9132_ID) ||
|
| 521 |
|
|
(db->chip_revision >= 0x02000030) ) {
|
| 522 |
|
|
db->cr6_data |= DMFE_TXTH_256;
|
| 523 |
|
|
db->cr0_data = CR0_DEFAULT;
|
| 524 |
|
|
db->dm910x_chk_mode=4; /* Enter the normal mode */
|
| 525 |
|
|
} else {
|
| 526 |
|
|
db->cr6_data |= CR6_SFT; /* Store & Forward mode */
|
| 527 |
|
|
db->cr0_data = 0;
|
| 528 |
|
|
db->dm910x_chk_mode = 1; /* Enter the check mode */
|
| 529 |
|
|
}
|
| 530 |
|
|
|
| 531 |
|
|
/* Initilize DM910X board */
|
| 532 |
|
|
dmfe_init_dm910x(dev);
|
| 533 |
|
|
|
| 534 |
|
|
/* Active System Interface */
|
| 535 |
|
|
netif_wake_queue(dev);
|
| 536 |
|
|
|
| 537 |
|
|
/* set and active a timer process */
|
| 538 |
|
|
init_timer(&db->timer);
|
| 539 |
|
|
db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
|
| 540 |
|
|
db->timer.data = (unsigned long)dev;
|
| 541 |
|
|
db->timer.function = &dmfe_timer;
|
| 542 |
|
|
add_timer(&db->timer);
|
| 543 |
|
|
|
| 544 |
|
|
return 0;
|
| 545 |
|
|
}
|
| 546 |
|
|
|
| 547 |
|
|
|
| 548 |
|
|
/* Initilize DM910X board
|
| 549 |
|
|
* Reset DM910X board
|
| 550 |
|
|
* Initilize TX/Rx descriptor chain structure
|
| 551 |
|
|
* Send the set-up frame
|
| 552 |
|
|
* Enable Tx/Rx machine
|
| 553 |
|
|
*/
|
| 554 |
|
|
|
| 555 |
|
|
static void dmfe_init_dm910x(struct DEVICE *dev)
|
| 556 |
|
|
{
|
| 557 |
|
|
struct dmfe_board_info *db = dev->priv;
|
| 558 |
|
|
unsigned long ioaddr = db->ioaddr;
|
| 559 |
|
|
|
| 560 |
|
|
DMFE_DBUG(0, "dmfe_init_dm910x()", 0);
|
| 561 |
|
|
|
| 562 |
|
|
/* Reset DM910x MAC controller */
|
| 563 |
|
|
outl(DM910X_RESET, ioaddr + DCR0); /* RESET MAC */
|
| 564 |
|
|
udelay(100);
|
| 565 |
|
|
outl(db->cr0_data, ioaddr + DCR0);
|
| 566 |
|
|
udelay(5);
|
| 567 |
|
|
|
| 568 |
|
|
/* Phy addr : DM910(A)2/DM9132/9801, phy address = 1 */
|
| 569 |
|
|
db->phy_addr = 1;
|
| 570 |
|
|
|
| 571 |
|
|
/* Parser SROM and media mode */
|
| 572 |
|
|
dmfe_parse_srom(db);
|
| 573 |
|
|
db->media_mode = dmfe_media_mode;
|
| 574 |
|
|
|
| 575 |
|
|
/* RESET Phyxcer Chip by GPR port bit 7 */
|
| 576 |
|
|
outl(0x180, ioaddr + DCR12); /* Let bit 7 output port */
|
| 577 |
|
|
if (db->chip_id == PCI_DM9009_ID) {
|
| 578 |
|
|
outl(0x80, ioaddr + DCR12); /* Issue RESET signal */
|
| 579 |
|
|
mdelay(300); /* Delay 300 ms */
|
| 580 |
|
|
}
|
| 581 |
|
|
outl(0x0, ioaddr + DCR12); /* Clear RESET signal */
|
| 582 |
|
|
|
| 583 |
|
|
/* Process Phyxcer Media Mode */
|
| 584 |
|
|
if ( !(db->media_mode & 0x10) ) /* Force 1M mode */
|
| 585 |
|
|
dmfe_set_phyxcer(db);
|
| 586 |
|
|
|
| 587 |
|
|
/* Media Mode Process */
|
| 588 |
|
|
if ( !(db->media_mode & DMFE_AUTO) )
|
| 589 |
|
|
db->op_mode = db->media_mode; /* Force Mode */
|
| 590 |
|
|
|
| 591 |
|
|
/* Initiliaze Transmit/Receive decriptor and CR3/4 */
|
| 592 |
|
|
dmfe_descriptor_init(db, ioaddr);
|
| 593 |
|
|
|
| 594 |
|
|
/* Init CR6 to program DM910x operation */
|
| 595 |
|
|
update_cr6(db->cr6_data, ioaddr);
|
| 596 |
|
|
|
| 597 |
|
|
/* Send setup frame */
|
| 598 |
|
|
if (db->chip_id == PCI_DM9132_ID)
|
| 599 |
|
|
dm9132_id_table(dev, dev->mc_count); /* DM9132 */
|
| 600 |
|
|
else
|
| 601 |
|
|
send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
|
| 602 |
|
|
|
| 603 |
|
|
/* Init CR7, interrupt active bit */
|
| 604 |
|
|
db->cr7_data = CR7_DEFAULT;
|
| 605 |
|
|
outl(db->cr7_data, ioaddr + DCR7);
|
| 606 |
|
|
|
| 607 |
|
|
/* Init CR15, Tx jabber and Rx watchdog timer */
|
| 608 |
|
|
outl(db->cr15_data, ioaddr + DCR15);
|
| 609 |
|
|
|
| 610 |
|
|
/* Enable DM910X Tx/Rx function */
|
| 611 |
|
|
db->cr6_data |= CR6_RXSC | CR6_TXSC | 0x40000;
|
| 612 |
|
|
update_cr6(db->cr6_data, ioaddr);
|
| 613 |
|
|
}
|
| 614 |
|
|
|
| 615 |
|
|
|
| 616 |
|
|
/*
|
| 617 |
|
|
* Hardware start transmission.
|
| 618 |
|
|
* Send a packet to media from the upper layer.
|
| 619 |
|
|
*/
|
| 620 |
|
|
|
| 621 |
|
|
static int dmfe_start_xmit(struct sk_buff *skb, struct DEVICE *dev)
|
| 622 |
|
|
{
|
| 623 |
|
|
struct dmfe_board_info *db = dev->priv;
|
| 624 |
|
|
struct tx_desc *txptr;
|
| 625 |
|
|
unsigned long flags;
|
| 626 |
|
|
|
| 627 |
|
|
DMFE_DBUG(0, "dmfe_start_xmit", 0);
|
| 628 |
|
|
|
| 629 |
|
|
/* Resource flag check */
|
| 630 |
|
|
netif_stop_queue(dev);
|
| 631 |
|
|
|
| 632 |
|
|
/* Too large packet check */
|
| 633 |
|
|
if (skb->len > MAX_PACKET_SIZE) {
|
| 634 |
|
|
printk(KERN_ERR DRV_NAME ": big packet = %d\n", (u16)skb->len);
|
| 635 |
|
|
dev_kfree_skb(skb);
|
| 636 |
|
|
return 0;
|
| 637 |
|
|
}
|
| 638 |
|
|
|
| 639 |
|
|
spin_lock_irqsave(&db->lock, flags);
|
| 640 |
|
|
|
| 641 |
|
|
/* No Tx resource check, it never happen nromally */
|
| 642 |
|
|
if (db->tx_queue_cnt >= TX_FREE_DESC_CNT) {
|
| 643 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 644 |
|
|
printk(KERN_ERR DRV_NAME ": No Tx resource %ld\n", db->tx_queue_cnt);
|
| 645 |
|
|
return 1;
|
| 646 |
|
|
}
|
| 647 |
|
|
|
| 648 |
|
|
/* Disable NIC interrupt */
|
| 649 |
|
|
outl(0, dev->base_addr + DCR7);
|
| 650 |
|
|
|
| 651 |
|
|
/* transmit this packet */
|
| 652 |
|
|
txptr = db->tx_insert_ptr;
|
| 653 |
|
|
memcpy(txptr->tx_buf_ptr, skb->data, skb->len);
|
| 654 |
|
|
txptr->tdes1 = cpu_to_le32(0xe1000000 | skb->len);
|
| 655 |
|
|
|
| 656 |
|
|
/* Point to next transmit free descriptor */
|
| 657 |
|
|
db->tx_insert_ptr = txptr->next_tx_desc;
|
| 658 |
|
|
|
| 659 |
|
|
/* Transmit Packet Process */
|
| 660 |
|
|
if ( (!db->tx_queue_cnt) && (db->tx_packet_cnt < TX_MAX_SEND_CNT) ) {
|
| 661 |
|
|
txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
|
| 662 |
|
|
db->tx_packet_cnt++; /* Ready to send */
|
| 663 |
|
|
outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
|
| 664 |
|
|
dev->trans_start = jiffies; /* saved time stamp */
|
| 665 |
|
|
} else {
|
| 666 |
|
|
db->tx_queue_cnt++; /* queue TX packet */
|
| 667 |
|
|
outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
|
| 668 |
|
|
}
|
| 669 |
|
|
|
| 670 |
|
|
/* Tx resource check */
|
| 671 |
|
|
if ( db->tx_queue_cnt < TX_FREE_DESC_CNT )
|
| 672 |
|
|
netif_wake_queue(dev);
|
| 673 |
|
|
|
| 674 |
|
|
/* free this SKB */
|
| 675 |
|
|
dev_kfree_skb(skb);
|
| 676 |
|
|
|
| 677 |
|
|
/* Restore CR7 to enable interrupt */
|
| 678 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 679 |
|
|
outl(db->cr7_data, dev->base_addr + DCR7);
|
| 680 |
|
|
|
| 681 |
|
|
return 0;
|
| 682 |
|
|
}
|
| 683 |
|
|
|
| 684 |
|
|
|
| 685 |
|
|
/*
|
| 686 |
|
|
* Stop the interface.
|
| 687 |
|
|
* The interface is stopped when it is brought.
|
| 688 |
|
|
*/
|
| 689 |
|
|
|
| 690 |
|
|
static int dmfe_stop(struct DEVICE *dev)
|
| 691 |
|
|
{
|
| 692 |
|
|
struct dmfe_board_info *db = dev->priv;
|
| 693 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 694 |
|
|
|
| 695 |
|
|
DMFE_DBUG(0, "dmfe_stop", 0);
|
| 696 |
|
|
|
| 697 |
|
|
/* disable system */
|
| 698 |
|
|
netif_stop_queue(dev);
|
| 699 |
|
|
|
| 700 |
|
|
/* deleted timer */
|
| 701 |
|
|
del_timer_sync(&db->timer);
|
| 702 |
|
|
|
| 703 |
|
|
/* Reset & stop DM910X board */
|
| 704 |
|
|
outl(DM910X_RESET, ioaddr + DCR0);
|
| 705 |
|
|
udelay(5);
|
| 706 |
|
|
phy_write(db->ioaddr, db->phy_addr, 0, 0x8000, db->chip_id);
|
| 707 |
|
|
|
| 708 |
|
|
/* free interrupt */
|
| 709 |
|
|
free_irq(dev->irq, dev);
|
| 710 |
|
|
|
| 711 |
|
|
/* free allocated rx buffer */
|
| 712 |
|
|
dmfe_free_rxbuffer(db);
|
| 713 |
|
|
|
| 714 |
|
|
#if 0
|
| 715 |
|
|
/* show statistic counter */
|
| 716 |
|
|
printk(DRV_NAME ": FU:%lx EC:%lx LC:%lx NC:%lx LOC:%lx TXJT:%lx RESET:%lx RCR8:%lx FAL:%lx TT:%lx\n",
|
| 717 |
|
|
db->tx_fifo_underrun, db->tx_excessive_collision,
|
| 718 |
|
|
db->tx_late_collision, db->tx_no_carrier, db->tx_loss_carrier,
|
| 719 |
|
|
db->tx_jabber_timeout, db->reset_count, db->reset_cr8,
|
| 720 |
|
|
db->reset_fatal, db->reset_TXtimeout);
|
| 721 |
|
|
#endif
|
| 722 |
|
|
|
| 723 |
|
|
return 0;
|
| 724 |
|
|
}
|
| 725 |
|
|
|
| 726 |
|
|
|
| 727 |
|
|
/*
|
| 728 |
|
|
* DM9102 insterrupt handler
|
| 729 |
|
|
* receive the packet to upper layer, free the transmitted packet
|
| 730 |
|
|
*/
|
| 731 |
|
|
|
| 732 |
|
|
static void dmfe_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
| 733 |
|
|
{
|
| 734 |
|
|
struct DEVICE *dev = dev_id;
|
| 735 |
|
|
struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv;
|
| 736 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 737 |
|
|
unsigned long flags;
|
| 738 |
|
|
|
| 739 |
|
|
DMFE_DBUG(0, "dmfe_interrupt()", 0);
|
| 740 |
|
|
|
| 741 |
|
|
if (!dev) {
|
| 742 |
|
|
DMFE_DBUG(1, "dmfe_interrupt() without DEVICE arg", 0);
|
| 743 |
|
|
return;
|
| 744 |
|
|
}
|
| 745 |
|
|
|
| 746 |
|
|
spin_lock_irqsave(&db->lock, flags);
|
| 747 |
|
|
|
| 748 |
|
|
/* Got DM910X status */
|
| 749 |
|
|
db->cr5_data = inl(ioaddr + DCR5);
|
| 750 |
|
|
outl(db->cr5_data, ioaddr + DCR5);
|
| 751 |
|
|
if ( !(db->cr5_data & 0xc1) ) {
|
| 752 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 753 |
|
|
return;
|
| 754 |
|
|
}
|
| 755 |
|
|
|
| 756 |
|
|
/* Disable all interrupt in CR7 to solve the interrupt edge problem */
|
| 757 |
|
|
outl(0, ioaddr + DCR7);
|
| 758 |
|
|
|
| 759 |
|
|
/* Check system status */
|
| 760 |
|
|
if (db->cr5_data & 0x2000) {
|
| 761 |
|
|
/* system bus error happen */
|
| 762 |
|
|
DMFE_DBUG(1, "System bus error happen. CR5=", db->cr5_data);
|
| 763 |
|
|
db->reset_fatal++;
|
| 764 |
|
|
db->wait_reset = 1; /* Need to RESET */
|
| 765 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 766 |
|
|
return;
|
| 767 |
|
|
}
|
| 768 |
|
|
|
| 769 |
|
|
/* Received the coming packet */
|
| 770 |
|
|
if ( (db->cr5_data & 0x40) && db->rx_avail_cnt )
|
| 771 |
|
|
dmfe_rx_packet(dev, db);
|
| 772 |
|
|
|
| 773 |
|
|
/* reallocate rx descriptor buffer */
|
| 774 |
|
|
if (db->rx_avail_cnt<RX_DESC_CNT)
|
| 775 |
|
|
allocate_rx_buffer(db);
|
| 776 |
|
|
|
| 777 |
|
|
/* Free the transmitted descriptor */
|
| 778 |
|
|
if ( db->cr5_data & 0x01)
|
| 779 |
|
|
dmfe_free_tx_pkt(dev, db);
|
| 780 |
|
|
|
| 781 |
|
|
/* Mode Check */
|
| 782 |
|
|
if (db->dm910x_chk_mode & 0x2) {
|
| 783 |
|
|
db->dm910x_chk_mode = 0x4;
|
| 784 |
|
|
db->cr6_data |= 0x100;
|
| 785 |
|
|
update_cr6(db->cr6_data, db->ioaddr);
|
| 786 |
|
|
}
|
| 787 |
|
|
|
| 788 |
|
|
/* Restore CR7 to enable interrupt mask */
|
| 789 |
|
|
outl(db->cr7_data, ioaddr + DCR7);
|
| 790 |
|
|
|
| 791 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 792 |
|
|
}
|
| 793 |
|
|
|
| 794 |
|
|
|
| 795 |
|
|
/*
|
| 796 |
|
|
* Free TX resource after TX complete
|
| 797 |
|
|
*/
|
| 798 |
|
|
|
| 799 |
|
|
static void dmfe_free_tx_pkt(struct DEVICE *dev, struct dmfe_board_info * db)
|
| 800 |
|
|
{
|
| 801 |
|
|
struct tx_desc *txptr;
|
| 802 |
|
|
unsigned long ioaddr = dev->base_addr;
|
| 803 |
|
|
u32 tdes0;
|
| 804 |
|
|
|
| 805 |
|
|
txptr = db->tx_remove_ptr;
|
| 806 |
|
|
while(db->tx_packet_cnt) {
|
| 807 |
|
|
tdes0 = le32_to_cpu(txptr->tdes0);
|
| 808 |
|
|
/* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
|
| 809 |
|
|
if (tdes0 & 0x80000000)
|
| 810 |
|
|
break;
|
| 811 |
|
|
|
| 812 |
|
|
/* A packet sent completed */
|
| 813 |
|
|
db->tx_packet_cnt--;
|
| 814 |
|
|
db->stats.tx_packets++;
|
| 815 |
|
|
|
| 816 |
|
|
/* Transmit statistic counter */
|
| 817 |
|
|
if ( tdes0 != 0x7fffffff ) {
|
| 818 |
|
|
/* printk(DRV_NAME ": tdes0=%x\n", tdes0); */
|
| 819 |
|
|
db->stats.collisions += (tdes0 >> 3) & 0xf;
|
| 820 |
|
|
db->stats.tx_bytes += le32_to_cpu(txptr->tdes1) & 0x7ff;
|
| 821 |
|
|
if (tdes0 & TDES0_ERR_MASK) {
|
| 822 |
|
|
db->stats.tx_errors++;
|
| 823 |
|
|
|
| 824 |
|
|
if (tdes0 & 0x0002) { /* UnderRun */
|
| 825 |
|
|
db->tx_fifo_underrun++;
|
| 826 |
|
|
if ( !(db->cr6_data & CR6_SFT) ) {
|
| 827 |
|
|
db->cr6_data = db->cr6_data | CR6_SFT;
|
| 828 |
|
|
update_cr6(db->cr6_data, db->ioaddr);
|
| 829 |
|
|
}
|
| 830 |
|
|
}
|
| 831 |
|
|
if (tdes0 & 0x0100)
|
| 832 |
|
|
db->tx_excessive_collision++;
|
| 833 |
|
|
if (tdes0 & 0x0200)
|
| 834 |
|
|
db->tx_late_collision++;
|
| 835 |
|
|
if (tdes0 & 0x0400)
|
| 836 |
|
|
db->tx_no_carrier++;
|
| 837 |
|
|
if (tdes0 & 0x0800)
|
| 838 |
|
|
db->tx_loss_carrier++;
|
| 839 |
|
|
if (tdes0 & 0x4000)
|
| 840 |
|
|
db->tx_jabber_timeout++;
|
| 841 |
|
|
}
|
| 842 |
|
|
}
|
| 843 |
|
|
|
| 844 |
|
|
txptr = txptr->next_tx_desc;
|
| 845 |
|
|
}/* End of while */
|
| 846 |
|
|
|
| 847 |
|
|
/* Update TX remove pointer to next */
|
| 848 |
|
|
db->tx_remove_ptr = txptr;
|
| 849 |
|
|
|
| 850 |
|
|
/* Send the Tx packet in queue */
|
| 851 |
|
|
if ( (db->tx_packet_cnt < TX_MAX_SEND_CNT) && db->tx_queue_cnt ) {
|
| 852 |
|
|
txptr->tdes0 = cpu_to_le32(0x80000000); /* Set owner bit */
|
| 853 |
|
|
db->tx_packet_cnt++; /* Ready to send */
|
| 854 |
|
|
db->tx_queue_cnt--;
|
| 855 |
|
|
outl(0x1, ioaddr + DCR1); /* Issue Tx polling */
|
| 856 |
|
|
dev->trans_start = jiffies; /* saved time stamp */
|
| 857 |
|
|
}
|
| 858 |
|
|
|
| 859 |
|
|
/* Resource available check */
|
| 860 |
|
|
if ( db->tx_queue_cnt < TX_WAKE_DESC_CNT )
|
| 861 |
|
|
netif_wake_queue(dev); /* Active upper layer, send again */
|
| 862 |
|
|
}
|
| 863 |
|
|
|
| 864 |
|
|
|
| 865 |
|
|
/*
|
| 866 |
|
|
* Receive the come packet and pass to upper layer
|
| 867 |
|
|
*/
|
| 868 |
|
|
|
| 869 |
|
|
static void dmfe_rx_packet(struct DEVICE *dev, struct dmfe_board_info * db)
|
| 870 |
|
|
{
|
| 871 |
|
|
struct rx_desc *rxptr;
|
| 872 |
|
|
struct sk_buff *skb;
|
| 873 |
|
|
int rxlen;
|
| 874 |
|
|
u32 rdes0;
|
| 875 |
|
|
|
| 876 |
|
|
rxptr = db->rx_ready_ptr;
|
| 877 |
|
|
|
| 878 |
|
|
while(db->rx_avail_cnt) {
|
| 879 |
|
|
rdes0 = le32_to_cpu(rxptr->rdes0);
|
| 880 |
|
|
if (rdes0 & 0x80000000) /* packet owner check */
|
| 881 |
|
|
break;
|
| 882 |
|
|
|
| 883 |
|
|
db->rx_avail_cnt--;
|
| 884 |
|
|
db->interval_rx_cnt++;
|
| 885 |
|
|
|
| 886 |
|
|
pci_unmap_single(db->pdev, le32_to_cpu(rxptr->rdes2), RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE);
|
| 887 |
|
|
if ( (rdes0 & 0x300) != 0x300) {
|
| 888 |
|
|
/* A packet without First/Last flag */
|
| 889 |
|
|
/* reuse this SKB */
|
| 890 |
|
|
DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
|
| 891 |
|
|
dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
|
| 892 |
|
|
} else {
|
| 893 |
|
|
/* A packet with First/Last flag */
|
| 894 |
|
|
rxlen = ( (rdes0 >> 16) & 0x3fff) - 4;
|
| 895 |
|
|
|
| 896 |
|
|
/* error summary bit check */
|
| 897 |
|
|
if (rdes0 & 0x8000) {
|
| 898 |
|
|
/* This is a error packet */
|
| 899 |
|
|
//printk(DRV_NAME ": rdes0: %lx\n", rdes0);
|
| 900 |
|
|
db->stats.rx_errors++;
|
| 901 |
|
|
if (rdes0 & 1)
|
| 902 |
|
|
db->stats.rx_fifo_errors++;
|
| 903 |
|
|
if (rdes0 & 2)
|
| 904 |
|
|
db->stats.rx_crc_errors++;
|
| 905 |
|
|
if (rdes0 & 0x80)
|
| 906 |
|
|
db->stats.rx_length_errors++;
|
| 907 |
|
|
}
|
| 908 |
|
|
|
| 909 |
|
|
if ( !(rdes0 & 0x8000) ||
|
| 910 |
|
|
((db->cr6_data & CR6_PM) && (rxlen>6)) ) {
|
| 911 |
|
|
skb = rxptr->rx_skb_ptr;
|
| 912 |
|
|
|
| 913 |
|
|
/* Received Packet CRC check need or not */
|
| 914 |
|
|
if ( (db->dm910x_chk_mode & 1) &&
|
| 915 |
|
|
(cal_CRC(skb->tail, rxlen, 1) !=
|
| 916 |
|
|
(*(u32 *) (skb->tail+rxlen) ))) { /* FIXME (?) */
|
| 917 |
|
|
/* Found a error received packet */
|
| 918 |
|
|
dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
|
| 919 |
|
|
db->dm910x_chk_mode = 3;
|
| 920 |
|
|
} else {
|
| 921 |
|
|
/* Good packet, send to upper layer */
|
| 922 |
|
|
/* Shorst packet used new SKB */
|
| 923 |
|
|
if ( (rxlen < RX_COPY_SIZE) &&
|
| 924 |
|
|
( (skb = dev_alloc_skb(rxlen + 2) )
|
| 925 |
|
|
!= NULL) ) {
|
| 926 |
|
|
/* size less than COPY_SIZE, allocate a rxlen SKB */
|
| 927 |
|
|
skb->dev = dev;
|
| 928 |
|
|
skb_reserve(skb, 2); /* 16byte align */
|
| 929 |
|
|
memcpy(skb_put(skb, rxlen), rxptr->rx_skb_ptr->tail, rxlen);
|
| 930 |
|
|
dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
|
| 931 |
|
|
} else {
|
| 932 |
|
|
skb->dev = dev;
|
| 933 |
|
|
skb_put(skb, rxlen);
|
| 934 |
|
|
}
|
| 935 |
|
|
skb->protocol = eth_type_trans(skb, dev);
|
| 936 |
|
|
netif_rx(skb);
|
| 937 |
|
|
dev->last_rx = jiffies;
|
| 938 |
|
|
db->stats.rx_packets++;
|
| 939 |
|
|
db->stats.rx_bytes += rxlen;
|
| 940 |
|
|
}
|
| 941 |
|
|
} else {
|
| 942 |
|
|
/* Reuse SKB buffer when the packet is error */
|
| 943 |
|
|
DMFE_DBUG(0, "Reuse SK buffer, rdes0", rdes0);
|
| 944 |
|
|
dmfe_reuse_skb(db, rxptr->rx_skb_ptr);
|
| 945 |
|
|
}
|
| 946 |
|
|
}
|
| 947 |
|
|
|
| 948 |
|
|
rxptr = rxptr->next_rx_desc;
|
| 949 |
|
|
}
|
| 950 |
|
|
|
| 951 |
|
|
db->rx_ready_ptr = rxptr;
|
| 952 |
|
|
}
|
| 953 |
|
|
|
| 954 |
|
|
|
| 955 |
|
|
/*
|
| 956 |
|
|
* Get statistics from driver.
|
| 957 |
|
|
*/
|
| 958 |
|
|
|
| 959 |
|
|
static struct net_device_stats * dmfe_get_stats(struct DEVICE *dev)
|
| 960 |
|
|
{
|
| 961 |
|
|
struct dmfe_board_info *db = (struct dmfe_board_info *)dev->priv;
|
| 962 |
|
|
|
| 963 |
|
|
DMFE_DBUG(0, "dmfe_get_stats", 0);
|
| 964 |
|
|
return &db->stats;
|
| 965 |
|
|
}
|
| 966 |
|
|
|
| 967 |
|
|
|
| 968 |
|
|
/*
|
| 969 |
|
|
* Set DM910X multicast address
|
| 970 |
|
|
*/
|
| 971 |
|
|
|
| 972 |
|
|
static void dmfe_set_filter_mode(struct DEVICE * dev)
|
| 973 |
|
|
{
|
| 974 |
|
|
struct dmfe_board_info *db = dev->priv;
|
| 975 |
|
|
unsigned long flags;
|
| 976 |
|
|
|
| 977 |
|
|
DMFE_DBUG(0, "dmfe_set_filter_mode()", 0);
|
| 978 |
|
|
spin_lock_irqsave(&db->lock, flags);
|
| 979 |
|
|
|
| 980 |
|
|
if (dev->flags & IFF_PROMISC) {
|
| 981 |
|
|
DMFE_DBUG(0, "Enable PROM Mode", 0);
|
| 982 |
|
|
db->cr6_data |= CR6_PM | CR6_PBF;
|
| 983 |
|
|
update_cr6(db->cr6_data, db->ioaddr);
|
| 984 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 985 |
|
|
return;
|
| 986 |
|
|
}
|
| 987 |
|
|
|
| 988 |
|
|
if (dev->flags & IFF_ALLMULTI || dev->mc_count > DMFE_MAX_MULTICAST) {
|
| 989 |
|
|
DMFE_DBUG(0, "Pass all multicast address", dev->mc_count);
|
| 990 |
|
|
db->cr6_data &= ~(CR6_PM | CR6_PBF);
|
| 991 |
|
|
db->cr6_data |= CR6_PAM;
|
| 992 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 993 |
|
|
return;
|
| 994 |
|
|
}
|
| 995 |
|
|
|
| 996 |
|
|
DMFE_DBUG(0, "Set multicast address", dev->mc_count);
|
| 997 |
|
|
if (db->chip_id == PCI_DM9132_ID)
|
| 998 |
|
|
dm9132_id_table(dev, dev->mc_count); /* DM9132 */
|
| 999 |
|
|
else
|
| 1000 |
|
|
send_filter_frame(dev, dev->mc_count); /* DM9102/DM9102A */
|
| 1001 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 1002 |
|
|
}
|
| 1003 |
|
|
|
| 1004 |
|
|
|
| 1005 |
|
|
static void netdev_get_drvinfo(struct net_device *dev,
|
| 1006 |
|
|
struct ethtool_drvinfo *info)
|
| 1007 |
|
|
{
|
| 1008 |
|
|
struct dmfe_board_info *np = dev->priv;
|
| 1009 |
|
|
|
| 1010 |
|
|
strcpy(info->driver, DRV_NAME);
|
| 1011 |
|
|
strcpy(info->version, DRV_VERSION);
|
| 1012 |
|
|
if (np->pdev)
|
| 1013 |
|
|
strcpy(info->bus_info, pci_name(np->pdev));
|
| 1014 |
|
|
else
|
| 1015 |
|
|
sprintf(info->bus_info, "EISA 0x%lx %d",
|
| 1016 |
|
|
dev->base_addr, dev->irq);
|
| 1017 |
|
|
}
|
| 1018 |
|
|
|
| 1019 |
|
|
static struct ethtool_ops netdev_ethtool_ops = {
|
| 1020 |
|
|
.get_drvinfo = netdev_get_drvinfo,
|
| 1021 |
|
|
};
|
| 1022 |
|
|
|
| 1023 |
|
|
/*
|
| 1024 |
|
|
* A periodic timer routine
|
| 1025 |
|
|
* Dynamic media sense, allocate Rx buffer...
|
| 1026 |
|
|
*/
|
| 1027 |
|
|
|
| 1028 |
|
|
static void dmfe_timer(unsigned long data)
|
| 1029 |
|
|
{
|
| 1030 |
|
|
u32 tmp_cr8;
|
| 1031 |
|
|
unsigned char tmp_cr12;
|
| 1032 |
|
|
struct DEVICE *dev = (struct DEVICE *) data;
|
| 1033 |
|
|
struct dmfe_board_info *db = (struct dmfe_board_info *) dev->priv;
|
| 1034 |
|
|
unsigned long flags;
|
| 1035 |
|
|
|
| 1036 |
|
|
DMFE_DBUG(0, "dmfe_timer()", 0);
|
| 1037 |
|
|
spin_lock_irqsave(&db->lock, flags);
|
| 1038 |
|
|
|
| 1039 |
|
|
/* Media mode process when Link OK before enter this route */
|
| 1040 |
|
|
if (db->first_in_callback == 0) {
|
| 1041 |
|
|
db->first_in_callback = 1;
|
| 1042 |
|
|
if (db->chip_type && (db->chip_id==PCI_DM9102_ID)) {
|
| 1043 |
|
|
db->cr6_data &= ~0x40000;
|
| 1044 |
|
|
update_cr6(db->cr6_data, db->ioaddr);
|
| 1045 |
|
|
phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
|
| 1046 |
|
|
db->cr6_data |= 0x40000;
|
| 1047 |
|
|
update_cr6(db->cr6_data, db->ioaddr);
|
| 1048 |
|
|
db->timer.expires = DMFE_TIMER_WUT + HZ * 2;
|
| 1049 |
|
|
add_timer(&db->timer);
|
| 1050 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 1051 |
|
|
return;
|
| 1052 |
|
|
}
|
| 1053 |
|
|
}
|
| 1054 |
|
|
|
| 1055 |
|
|
|
| 1056 |
|
|
/* Operating Mode Check */
|
| 1057 |
|
|
if ( (db->dm910x_chk_mode & 0x1) &&
|
| 1058 |
|
|
(db->stats.rx_packets > MAX_CHECK_PACKET) )
|
| 1059 |
|
|
db->dm910x_chk_mode = 0x4;
|
| 1060 |
|
|
|
| 1061 |
|
|
/* Dynamic reset DM910X : system error or transmit time-out */
|
| 1062 |
|
|
tmp_cr8 = inl(db->ioaddr + DCR8);
|
| 1063 |
|
|
if ( (db->interval_rx_cnt==0) && (tmp_cr8) ) {
|
| 1064 |
|
|
db->reset_cr8++;
|
| 1065 |
|
|
db->wait_reset = 1;
|
| 1066 |
|
|
}
|
| 1067 |
|
|
db->interval_rx_cnt = 0;
|
| 1068 |
|
|
|
| 1069 |
|
|
/* TX polling kick monitor */
|
| 1070 |
|
|
if ( db->tx_packet_cnt &&
|
| 1071 |
|
|
time_after(jiffies, dev->trans_start + DMFE_TX_KICK) ) {
|
| 1072 |
|
|
outl(0x1, dev->base_addr + DCR1); /* Tx polling again */
|
| 1073 |
|
|
|
| 1074 |
|
|
/* TX Timeout */
|
| 1075 |
|
|
if ( time_after(jiffies, dev->trans_start + DMFE_TX_TIMEOUT) ) {
|
| 1076 |
|
|
db->reset_TXtimeout++;
|
| 1077 |
|
|
db->wait_reset = 1;
|
| 1078 |
|
|
printk(KERN_WARNING "%s: Tx timeout - resetting\n",
|
| 1079 |
|
|
dev->name);
|
| 1080 |
|
|
}
|
| 1081 |
|
|
}
|
| 1082 |
|
|
|
| 1083 |
|
|
if (db->wait_reset) {
|
| 1084 |
|
|
DMFE_DBUG(0, "Dynamic Reset device", db->tx_packet_cnt);
|
| 1085 |
|
|
db->reset_count++;
|
| 1086 |
|
|
dmfe_dynamic_reset(dev);
|
| 1087 |
|
|
db->first_in_callback = 0;
|
| 1088 |
|
|
db->timer.expires = DMFE_TIMER_WUT;
|
| 1089 |
|
|
add_timer(&db->timer);
|
| 1090 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 1091 |
|
|
return;
|
| 1092 |
|
|
}
|
| 1093 |
|
|
|
| 1094 |
|
|
/* Link status check, Dynamic media type change */
|
| 1095 |
|
|
if (db->chip_id == PCI_DM9132_ID)
|
| 1096 |
|
|
tmp_cr12 = inb(db->ioaddr + DCR9 + 3); /* DM9132 */
|
| 1097 |
|
|
else
|
| 1098 |
|
|
tmp_cr12 = inb(db->ioaddr + DCR12); /* DM9102/DM9102A */
|
| 1099 |
|
|
|
| 1100 |
|
|
if ( ((db->chip_id == PCI_DM9102_ID) &&
|
| 1101 |
|
|
(db->chip_revision == 0x02000030)) ||
|
| 1102 |
|
|
((db->chip_id == PCI_DM9132_ID) &&
|
| 1103 |
|
|
(db->chip_revision == 0x02000010)) ) {
|
| 1104 |
|
|
/* DM9102A Chip */
|
| 1105 |
|
|
if (tmp_cr12 & 2)
|
| 1106 |
|
|
tmp_cr12 = 0x0; /* Link failed */
|
| 1107 |
|
|
else
|
| 1108 |
|
|
tmp_cr12 = 0x3; /* Link OK */
|
| 1109 |
|
|
}
|
| 1110 |
|
|
|
| 1111 |
|
|
if ( !(tmp_cr12 & 0x3) && !db->link_failed ) {
|
| 1112 |
|
|
/* Link Failed */
|
| 1113 |
|
|
DMFE_DBUG(0, "Link Failed", tmp_cr12);
|
| 1114 |
|
|
db->link_failed = 1;
|
| 1115 |
|
|
|
| 1116 |
|
|
/* For Force 10/100M Half/Full mode: Enable Auto-Nego mode */
|
| 1117 |
|
|
/* AUTO or force 1M Homerun/Longrun don't need */
|
| 1118 |
|
|
if ( !(db->media_mode & 0x38) )
|
| 1119 |
|
|
phy_write(db->ioaddr, db->phy_addr, 0, 0x1000, db->chip_id);
|
| 1120 |
|
|
|
| 1121 |
|
|
/* AUTO mode, if INT phyxcer link failed, select EXT device */
|
| 1122 |
|
|
if (db->media_mode & DMFE_AUTO) {
|
| 1123 |
|
|
/* 10/100M link failed, used 1M Home-Net */
|
| 1124 |
|
|
db->cr6_data|=0x00040000; /* bit18=1, MII */
|
| 1125 |
|
|
db->cr6_data&=~0x00000200; /* bit9=0, HD mode */
|
| 1126 |
|
|
update_cr6(db->cr6_data, db->ioaddr);
|
| 1127 |
|
|
}
|
| 1128 |
|
|
} else
|
| 1129 |
|
|
if ((tmp_cr12 & 0x3) && db->link_failed) {
|
| 1130 |
|
|
DMFE_DBUG(0, "Link link OK", tmp_cr12);
|
| 1131 |
|
|
db->link_failed = 0;
|
| 1132 |
|
|
|
| 1133 |
|
|
/* Auto Sense Speed */
|
| 1134 |
|
|
if ( (db->media_mode & DMFE_AUTO) &&
|
| 1135 |
|
|
dmfe_sense_speed(db) )
|
| 1136 |
|
|
db->link_failed = 1;
|
| 1137 |
|
|
dmfe_process_mode(db);
|
| 1138 |
|
|
/* SHOW_MEDIA_TYPE(db->op_mode); */
|
| 1139 |
|
|
}
|
| 1140 |
|
|
|
| 1141 |
|
|
/* HPNA remote command check */
|
| 1142 |
|
|
if (db->HPNA_command & 0xf00) {
|
| 1143 |
|
|
db->HPNA_timer--;
|
| 1144 |
|
|
if (!db->HPNA_timer)
|
| 1145 |
|
|
dmfe_HPNA_remote_cmd_chk(db);
|
| 1146 |
|
|
}
|
| 1147 |
|
|
|
| 1148 |
|
|
/* Timer active again */
|
| 1149 |
|
|
db->timer.expires = DMFE_TIMER_WUT;
|
| 1150 |
|
|
add_timer(&db->timer);
|
| 1151 |
|
|
spin_unlock_irqrestore(&db->lock, flags);
|
| 1152 |
|
|
}
|
| 1153 |
|
|
|
| 1154 |
|
|
|
| 1155 |
|
|
/*
|
| 1156 |
|
|
* Dynamic reset the DM910X board
|
| 1157 |
|
|
* Stop DM910X board
|
| 1158 |
|
|
* Free Tx/Rx allocated memory
|
| 1159 |
|
|
* Reset DM910X board
|
| 1160 |
|
|
* Re-initilize DM910X board
|
| 1161 |
|
|
*/
|
| 1162 |
|
|
|
| 1163 |
|
|
static void dmfe_dynamic_reset(struct DEVICE *dev)
|
| 1164 |
|
|
{
|
| 1165 |
|
|
struct dmfe_board_info *db = dev->priv;
|
| 1166 |
|
|
|
| 1167 |
|
|
DMFE_DBUG(0, "dmfe_dynamic_reset()", 0);
|
| 1168 |
|
|
|
| 1169 |
|
|
/* Sopt MAC controller */
|
| 1170 |
|
|
db->cr6_data &= ~(CR6_RXSC | CR6_TXSC); /* Disable Tx/Rx */
|
| 1171 |
|
|
update_cr6(db->cr6_data, dev->base_addr);
|
| 1172 |
|
|
outl(0, dev->base_addr + DCR7); /* Disable Interrupt */
|
| 1173 |
|
|
outl(inl(dev->base_addr + DCR5), dev->base_addr + DCR5);
|
| 1174 |
|
|
|
| 1175 |
|
|
/* Disable upper layer interface */
|
| 1176 |
|
|
netif_stop_queue(dev);
|
| 1177 |
|
|
|
| 1178 |
|
|
/* Free Rx Allocate buffer */
|
| 1179 |
|
|
dmfe_free_rxbuffer(db);
|
| 1180 |
|
|
|
| 1181 |
|
|
/* system variable init */
|
| 1182 |
|
|
db->tx_packet_cnt = 0;
|
| 1183 |
|
|
db->tx_queue_cnt = 0;
|
| 1184 |
|
|
db->rx_avail_cnt = 0;
|
| 1185 |
|
|
db->link_failed = 1;
|
| 1186 |
|
|
db->wait_reset = 0;
|
| 1187 |
|
|
|
| 1188 |
|
|
/* Re-initilize DM910X board */
|
| 1189 |
|
|
dmfe_init_dm910x(dev);
|
| 1190 |
|
|
|
| 1191 |
|
|
/* Restart upper layer interface */
|
| 1192 |
|
|
netif_wake_queue(dev);
|
| 1193 |
|
|
}
|
| 1194 |
|
|
|
| 1195 |
|
|
|
| 1196 |
|
|
/*
|
| 1197 |
|
|
* free all allocated rx buffer
|
| 1198 |
|
|
*/
|
| 1199 |
|
|
|
| 1200 |
|
|
static void dmfe_free_rxbuffer(struct dmfe_board_info * db)
|
| 1201 |
|
|
{
|
| 1202 |
|
|
DMFE_DBUG(0, "dmfe_free_rxbuffer()", 0);
|
| 1203 |
|
|
|
| 1204 |
|
|
/* free allocated rx buffer */
|
| 1205 |
|
|
while (db->rx_avail_cnt) {
|
| 1206 |
|
|
dev_kfree_skb(db->rx_ready_ptr->rx_skb_ptr);
|
| 1207 |
|
|
db->rx_ready_ptr = db->rx_ready_ptr->next_rx_desc;
|
| 1208 |
|
|
db->rx_avail_cnt--;
|
| 1209 |
|
|
}
|
| 1210 |
|
|
}
|
| 1211 |
|
|
|
| 1212 |
|
|
|
| 1213 |
|
|
/*
|
| 1214 |
|
|
* Reuse the SK buffer
|
| 1215 |
|
|
*/
|
| 1216 |
|
|
|
| 1217 |
|
|
static void dmfe_reuse_skb(struct dmfe_board_info *db, struct sk_buff * skb)
|
| 1218 |
|
|
{
|
| 1219 |
|
|
struct rx_desc *rxptr = db->rx_insert_ptr;
|
| 1220 |
|
|
|
| 1221 |
|
|
if (!(rxptr->rdes0 & cpu_to_le32(0x80000000))) {
|
| 1222 |
|
|
rxptr->rx_skb_ptr = skb;
|
| 1223 |
|
|
rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
|
| 1224 |
|
|
wmb();
|
| 1225 |
|
|
rxptr->rdes0 = cpu_to_le32(0x80000000);
|
| 1226 |
|
|
db->rx_avail_cnt++;
|
| 1227 |
|
|
db->rx_insert_ptr = rxptr->next_rx_desc;
|
| 1228 |
|
|
} else
|
| 1229 |
|
|
DMFE_DBUG(0, "SK Buffer reuse method error", db->rx_avail_cnt);
|
| 1230 |
|
|
}
|
| 1231 |
|
|
|
| 1232 |
|
|
|
| 1233 |
|
|
/*
|
| 1234 |
|
|
* Initialize transmit/Receive descriptor
|
| 1235 |
|
|
* Using Chain structure, and allocate Tx/Rx buffer
|
| 1236 |
|
|
*/
|
| 1237 |
|
|
|
| 1238 |
|
|
static void dmfe_descriptor_init(struct dmfe_board_info *db, unsigned long ioaddr)
|
| 1239 |
|
|
{
|
| 1240 |
|
|
struct tx_desc *tmp_tx;
|
| 1241 |
|
|
struct rx_desc *tmp_rx;
|
| 1242 |
|
|
unsigned char *tmp_buf;
|
| 1243 |
|
|
dma_addr_t tmp_tx_dma, tmp_rx_dma;
|
| 1244 |
|
|
dma_addr_t tmp_buf_dma;
|
| 1245 |
|
|
int i;
|
| 1246 |
|
|
|
| 1247 |
|
|
DMFE_DBUG(0, "dmfe_descriptor_init()", 0);
|
| 1248 |
|
|
|
| 1249 |
|
|
/* tx descriptor start pointer */
|
| 1250 |
|
|
db->tx_insert_ptr = db->first_tx_desc;
|
| 1251 |
|
|
db->tx_remove_ptr = db->first_tx_desc;
|
| 1252 |
|
|
outl(db->first_tx_desc_dma, ioaddr + DCR4); /* TX DESC address */
|
| 1253 |
|
|
|
| 1254 |
|
|
/* rx descriptor start pointer */
|
| 1255 |
|
|
db->first_rx_desc = (void *)db->first_tx_desc + sizeof(struct tx_desc) * TX_DESC_CNT;
|
| 1256 |
|
|
db->first_rx_desc_dma = db->first_tx_desc_dma + sizeof(struct tx_desc) * TX_DESC_CNT;
|
| 1257 |
|
|
db->rx_insert_ptr = db->first_rx_desc;
|
| 1258 |
|
|
db->rx_ready_ptr = db->first_rx_desc;
|
| 1259 |
|
|
outl(db->first_rx_desc_dma, ioaddr + DCR3); /* RX DESC address */
|
| 1260 |
|
|
|
| 1261 |
|
|
/* Init Transmit chain */
|
| 1262 |
|
|
tmp_buf = db->buf_pool_start;
|
| 1263 |
|
|
tmp_buf_dma = db->buf_pool_dma_start;
|
| 1264 |
|
|
tmp_tx_dma = db->first_tx_desc_dma;
|
| 1265 |
|
|
for (tmp_tx = db->first_tx_desc, i = 0; i < TX_DESC_CNT; i++, tmp_tx++) {
|
| 1266 |
|
|
tmp_tx->tx_buf_ptr = tmp_buf;
|
| 1267 |
|
|
tmp_tx->tdes0 = cpu_to_le32(0);
|
| 1268 |
|
|
tmp_tx->tdes1 = cpu_to_le32(0x81000000); /* IC, chain */
|
| 1269 |
|
|
tmp_tx->tdes2 = cpu_to_le32(tmp_buf_dma);
|
| 1270 |
|
|
tmp_tx_dma += sizeof(struct tx_desc);
|
| 1271 |
|
|
tmp_tx->tdes3 = cpu_to_le32(tmp_tx_dma);
|
| 1272 |
|
|
tmp_tx->next_tx_desc = tmp_tx + 1;
|
| 1273 |
|
|
tmp_buf = tmp_buf + TX_BUF_ALLOC;
|
| 1274 |
|
|
tmp_buf_dma = tmp_buf_dma + TX_BUF_ALLOC;
|
| 1275 |
|
|
}
|
| 1276 |
|
|
(--tmp_tx)->tdes3 = cpu_to_le32(db->first_tx_desc_dma);
|
| 1277 |
|
|
tmp_tx->next_tx_desc = db->first_tx_desc;
|
| 1278 |
|
|
|
| 1279 |
|
|
/* Init Receive descriptor chain */
|
| 1280 |
|
|
tmp_rx_dma=db->first_rx_desc_dma;
|
| 1281 |
|
|
for (tmp_rx = db->first_rx_desc, i = 0; i < RX_DESC_CNT; i++, tmp_rx++) {
|
| 1282 |
|
|
tmp_rx->rdes0 = cpu_to_le32(0);
|
| 1283 |
|
|
tmp_rx->rdes1 = cpu_to_le32(0x01000600);
|
| 1284 |
|
|
tmp_rx_dma += sizeof(struct rx_desc);
|
| 1285 |
|
|
tmp_rx->rdes3 = cpu_to_le32(tmp_rx_dma);
|
| 1286 |
|
|
tmp_rx->next_rx_desc = tmp_rx + 1;
|
| 1287 |
|
|
}
|
| 1288 |
|
|
(--tmp_rx)->rdes3 = cpu_to_le32(db->first_rx_desc_dma);
|
| 1289 |
|
|
tmp_rx->next_rx_desc = db->first_rx_desc;
|
| 1290 |
|
|
|
| 1291 |
|
|
/* pre-allocate Rx buffer */
|
| 1292 |
|
|
allocate_rx_buffer(db);
|
| 1293 |
|
|
}
|
| 1294 |
|
|
|
| 1295 |
|
|
|
| 1296 |
|
|
/*
|
| 1297 |
|
|
* Update CR6 value
|
| 1298 |
|
|
* Firstly stop DM910X , then written value and start
|
| 1299 |
|
|
*/
|
| 1300 |
|
|
|
| 1301 |
|
|
static void update_cr6(u32 cr6_data, unsigned long ioaddr)
|
| 1302 |
|
|
{
|
| 1303 |
|
|
u32 cr6_tmp;
|
| 1304 |
|
|
|
| 1305 |
|
|
cr6_tmp = cr6_data & ~0x2002; /* stop Tx/Rx */
|
| 1306 |
|
|
outl(cr6_tmp, ioaddr + DCR6);
|
| 1307 |
|
|
udelay(5);
|
| 1308 |
|
|
outl(cr6_data, ioaddr + DCR6);
|
| 1309 |
|
|
udelay(5);
|
| 1310 |
|
|
}
|
| 1311 |
|
|
|
| 1312 |
|
|
|
| 1313 |
|
|
/*
|
| 1314 |
|
|
* Send a setup frame for DM9132
|
| 1315 |
|
|
* This setup frame initilize DM910X addres filter mode
|
| 1316 |
|
|
*/
|
| 1317 |
|
|
|
| 1318 |
|
|
static void dm9132_id_table(struct DEVICE *dev, int mc_cnt)
|
| 1319 |
|
|
{
|
| 1320 |
|
|
struct dev_mc_list *mcptr;
|
| 1321 |
|
|
u16 * addrptr;
|
| 1322 |
|
|
unsigned long ioaddr = dev->base_addr+0xc0; /* ID Table */
|
| 1323 |
|
|
u32 hash_val;
|
| 1324 |
|
|
u16 i, hash_table[4];
|
| 1325 |
|
|
|
| 1326 |
|
|
DMFE_DBUG(0, "dm9132_id_table()", 0);
|
| 1327 |
|
|
|
| 1328 |
|
|
/* Node address */
|
| 1329 |
|
|
addrptr = (u16 *) dev->dev_addr;
|
| 1330 |
|
|
outw(addrptr[0], ioaddr);
|
| 1331 |
|
|
ioaddr += 4;
|
| 1332 |
|
|
outw(addrptr[1], ioaddr);
|
| 1333 |
|
|
ioaddr += 4;
|
| 1334 |
|
|
outw(addrptr[2], ioaddr);
|
| 1335 |
|
|
ioaddr += 4;
|
| 1336 |
|
|
|
| 1337 |
|
|
/* Clear Hash Table */
|
| 1338 |
|
|
for (i = 0; i < 4; i++)
|
| 1339 |
|
|
hash_table[i] = 0x0;
|
| 1340 |
|
|
|
| 1341 |
|
|
/* broadcast address */
|
| 1342 |
|
|
hash_table[3] = 0x8000;
|
| 1343 |
|
|
|
| 1344 |
|
|
/* the multicast address in Hash Table : 64 bits */
|
| 1345 |
|
|
for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
|
| 1346 |
|
|
hash_val = cal_CRC( (char *) mcptr->dmi_addr, 6, 0) & 0x3f;
|
| 1347 |
|
|
hash_table[hash_val / 16] |= (u16) 1 << (hash_val % 16);
|
| 1348 |
|
|
}
|
| 1349 |
|
|
|
| 1350 |
|
|
/* Write the hash table to MAC MD table */
|
| 1351 |
|
|
for (i = 0; i < 4; i++, ioaddr += 4)
|
| 1352 |
|
|
outw(hash_table[i], ioaddr);
|
| 1353 |
|
|
}
|
| 1354 |
|
|
|
| 1355 |
|
|
|
| 1356 |
|
|
/*
|
| 1357 |
|
|
* Send a setup frame for DM9102/DM9102A
|
| 1358 |
|
|
* This setup frame initilize DM910X addres filter mode
|
| 1359 |
|
|
*/
|
| 1360 |
|
|
|
| 1361 |
|
|
static void send_filter_frame(struct DEVICE *dev, int mc_cnt)
|
| 1362 |
|
|
{
|
| 1363 |
|
|
struct dmfe_board_info *db = dev->priv;
|
| 1364 |
|
|
struct dev_mc_list *mcptr;
|
| 1365 |
|
|
struct tx_desc *txptr;
|
| 1366 |
|
|
u16 * addrptr;
|
| 1367 |
|
|
u32 * suptr;
|
| 1368 |
|
|
int i;
|
| 1369 |
|
|
|
| 1370 |
|
|
DMFE_DBUG(0, "send_filter_frame()", 0);
|
| 1371 |
|
|
|
| 1372 |
|
|
txptr = db->tx_insert_ptr;
|
| 1373 |
|
|
suptr = (u32 *) txptr->tx_buf_ptr;
|
| 1374 |
|
|
|
| 1375 |
|
|
/* Node address */
|
| 1376 |
|
|
addrptr = (u16 *) dev->dev_addr;
|
| 1377 |
|
|
*suptr++ = addrptr[0];
|
| 1378 |
|
|
*suptr++ = addrptr[1];
|
| 1379 |
|
|
*suptr++ = addrptr[2];
|
| 1380 |
|
|
|
| 1381 |
|
|
/* broadcast address */
|
| 1382 |
|
|
*suptr++ = 0xffff;
|
| 1383 |
|
|
*suptr++ = 0xffff;
|
| 1384 |
|
|
*suptr++ = 0xffff;
|
| 1385 |
|
|
|
| 1386 |
|
|
/* fit the multicast address */
|
| 1387 |
|
|
for (mcptr = dev->mc_list, i = 0; i < mc_cnt; i++, mcptr = mcptr->next) {
|
| 1388 |
|
|
addrptr = (u16 *) mcptr->dmi_addr;
|
| 1389 |
|
|
*suptr++ = addrptr[0];
|
| 1390 |
|
|
*suptr++ = addrptr[1];
|
| 1391 |
|
|
*suptr++ = addrptr[2];
|
| 1392 |
|
|
}
|
| 1393 |
|
|
|
| 1394 |
|
|
for (; i<14; i++) {
|
| 1395 |
|
|
*suptr++ = 0xffff;
|
| 1396 |
|
|
*suptr++ = 0xffff;
|
| 1397 |
|
|
*suptr++ = 0xffff;
|
| 1398 |
|
|
}
|
| 1399 |
|
|
|
| 1400 |
|
|
/* prepare the setup frame */
|
| 1401 |
|
|
db->tx_insert_ptr = txptr->next_tx_desc;
|
| 1402 |
|
|
txptr->tdes1 = cpu_to_le32(0x890000c0);
|
| 1403 |
|
|
|
| 1404 |
|
|
/* Resource Check and Send the setup packet */
|
| 1405 |
|
|
if (!db->tx_packet_cnt) {
|
| 1406 |
|
|
/* Resource Empty */
|
| 1407 |
|
|
db->tx_packet_cnt++;
|
| 1408 |
|
|
txptr->tdes0 = cpu_to_le32(0x80000000);
|
| 1409 |
|
|
update_cr6(db->cr6_data | 0x2000, dev->base_addr);
|
| 1410 |
|
|
outl(0x1, dev->base_addr + DCR1); /* Issue Tx polling */
|
| 1411 |
|
|
update_cr6(db->cr6_data, dev->base_addr);
|
| 1412 |
|
|
dev->trans_start = jiffies;
|
| 1413 |
|
|
} else
|
| 1414 |
|
|
db->tx_queue_cnt++; /* Put in TX queue */
|
| 1415 |
|
|
}
|
| 1416 |
|
|
|
| 1417 |
|
|
|
| 1418 |
|
|
/*
|
| 1419 |
|
|
* Allocate rx buffer,
|
| 1420 |
|
|
* As possible as allocate maxiumn Rx buffer
|
| 1421 |
|
|
*/
|
| 1422 |
|
|
|
| 1423 |
|
|
static void allocate_rx_buffer(struct dmfe_board_info *db)
|
| 1424 |
|
|
{
|
| 1425 |
|
|
struct rx_desc *rxptr;
|
| 1426 |
|
|
struct sk_buff *skb;
|
| 1427 |
|
|
|
| 1428 |
|
|
rxptr = db->rx_insert_ptr;
|
| 1429 |
|
|
|
| 1430 |
|
|
while(db->rx_avail_cnt < RX_DESC_CNT) {
|
| 1431 |
|
|
if ( ( skb = dev_alloc_skb(RX_ALLOC_SIZE) ) == NULL )
|
| 1432 |
|
|
break;
|
| 1433 |
|
|
rxptr->rx_skb_ptr = skb; /* FIXME (?) */
|
| 1434 |
|
|
rxptr->rdes2 = cpu_to_le32( pci_map_single(db->pdev, skb->tail, RX_ALLOC_SIZE, PCI_DMA_FROMDEVICE) );
|
| 1435 |
|
|
wmb();
|
| 1436 |
|
|
rxptr->rdes0 = cpu_to_le32(0x80000000);
|
| 1437 |
|
|
rxptr = rxptr->next_rx_desc;
|
| 1438 |
|
|
db->rx_avail_cnt++;
|
| 1439 |
|
|
}
|
| 1440 |
|
|
|
| 1441 |
|
|
db->rx_insert_ptr = rxptr;
|
| 1442 |
|
|
}
|
| 1443 |
|
|
|
| 1444 |
|
|
|
| 1445 |
|
|
/*
|
| 1446 |
|
|
* Read one word data from the serial ROM
|
| 1447 |
|
|
*/
|
| 1448 |
|
|
|
| 1449 |
|
|
static u16 read_srom_word(long ioaddr, int offset)
|
| 1450 |
|
|
{
|
| 1451 |
|
|
int i;
|
| 1452 |
|
|
u16 srom_data = 0;
|
| 1453 |
|
|
long cr9_ioaddr = ioaddr + DCR9;
|
| 1454 |
|
|
|
| 1455 |
|
|
outl(CR9_SROM_READ, cr9_ioaddr);
|
| 1456 |
|
|
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
|
| 1457 |
|
|
|
| 1458 |
|
|
/* Send the Read Command 110b */
|
| 1459 |
|
|
SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
|
| 1460 |
|
|
SROM_CLK_WRITE(SROM_DATA_1, cr9_ioaddr);
|
| 1461 |
|
|
SROM_CLK_WRITE(SROM_DATA_0, cr9_ioaddr);
|
| 1462 |
|
|
|
| 1463 |
|
|
/* Send the offset */
|
| 1464 |
|
|
for (i = 5; i >= 0; i--) {
|
| 1465 |
|
|
srom_data = (offset & (1 << i)) ? SROM_DATA_1 : SROM_DATA_0;
|
| 1466 |
|
|
SROM_CLK_WRITE(srom_data, cr9_ioaddr);
|
| 1467 |
|
|
}
|
| 1468 |
|
|
|
| 1469 |
|
|
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
|
| 1470 |
|
|
|
| 1471 |
|
|
for (i = 16; i > 0; i--) {
|
| 1472 |
|
|
outl(CR9_SROM_READ | CR9_SRCS | CR9_SRCLK, cr9_ioaddr);
|
| 1473 |
|
|
udelay(5);
|
| 1474 |
|
|
srom_data = (srom_data << 1) | ((inl(cr9_ioaddr) & CR9_CRDOUT) ? 1 : 0);
|
| 1475 |
|
|
outl(CR9_SROM_READ | CR9_SRCS, cr9_ioaddr);
|
| 1476 |
|
|
udelay(5);
|
| 1477 |
|
|
}
|
| 1478 |
|
|
|
| 1479 |
|
|
outl(CR9_SROM_READ, cr9_ioaddr);
|
| 1480 |
|
|
return srom_data;
|
| 1481 |
|
|
}
|
| 1482 |
|
|
|
| 1483 |
|
|
|
| 1484 |
|
|
/*
|
| 1485 |
|
|
* Auto sense the media mode
|
| 1486 |
|
|
*/
|
| 1487 |
|
|
|
| 1488 |
|
|
static u8 dmfe_sense_speed(struct dmfe_board_info * db)
|
| 1489 |
|
|
{
|
| 1490 |
|
|
u8 ErrFlag = 0;
|
| 1491 |
|
|
u16 phy_mode;
|
| 1492 |
|
|
|
| 1493 |
|
|
/* CR6 bit18=0, select 10/100M */
|
| 1494 |
|
|
update_cr6( (db->cr6_data & ~0x40000), db->ioaddr);
|
| 1495 |
|
|
|
| 1496 |
|
|
phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
|
| 1497 |
|
|
phy_mode = phy_read(db->ioaddr, db->phy_addr, 1, db->chip_id);
|
| 1498 |
|
|
|
| 1499 |
|
|
if ( (phy_mode & 0x24) == 0x24 ) {
|
| 1500 |
|
|
if (db->chip_id == PCI_DM9132_ID) /* DM9132 */
|
| 1501 |
|
|
phy_mode = phy_read(db->ioaddr, db->phy_addr, 7, db->chip_id) & 0xf000;
|
| 1502 |
|
|
else /* DM9102/DM9102A */
|
| 1503 |
|
|
phy_mode = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0xf000;
|
| 1504 |
|
|
/* printk(DRV_NAME ": Phy_mode %x ",phy_mode); */
|
| 1505 |
|
|
switch (phy_mode) {
|
| 1506 |
|
|
case 0x1000: db->op_mode = DMFE_10MHF; break;
|
| 1507 |
|
|
case 0x2000: db->op_mode = DMFE_10MFD; break;
|
| 1508 |
|
|
case 0x4000: db->op_mode = DMFE_100MHF; break;
|
| 1509 |
|
|
case 0x8000: db->op_mode = DMFE_100MFD; break;
|
| 1510 |
|
|
default: db->op_mode = DMFE_10MHF;
|
| 1511 |
|
|
ErrFlag = 1;
|
| 1512 |
|
|
break;
|
| 1513 |
|
|
}
|
| 1514 |
|
|
} else {
|
| 1515 |
|
|
db->op_mode = DMFE_10MHF;
|
| 1516 |
|
|
DMFE_DBUG(0, "Link Failed :", phy_mode);
|
| 1517 |
|
|
ErrFlag = 1;
|
| 1518 |
|
|
}
|
| 1519 |
|
|
|
| 1520 |
|
|
return ErrFlag;
|
| 1521 |
|
|
}
|
| 1522 |
|
|
|
| 1523 |
|
|
|
| 1524 |
|
|
/*
|
| 1525 |
|
|
* Set 10/100 phyxcer capability
|
| 1526 |
|
|
* AUTO mode : phyxcer register4 is NIC capability
|
| 1527 |
|
|
* Force mode: phyxcer register4 is the force media
|
| 1528 |
|
|
*/
|
| 1529 |
|
|
|
| 1530 |
|
|
static void dmfe_set_phyxcer(struct dmfe_board_info *db)
|
| 1531 |
|
|
{
|
| 1532 |
|
|
u16 phy_reg;
|
| 1533 |
|
|
|
| 1534 |
|
|
/* Select 10/100M phyxcer */
|
| 1535 |
|
|
db->cr6_data &= ~0x40000;
|
| 1536 |
|
|
update_cr6(db->cr6_data, db->ioaddr);
|
| 1537 |
|
|
|
| 1538 |
|
|
/* DM9009 Chip: Phyxcer reg18 bit12=0 */
|
| 1539 |
|
|
if (db->chip_id == PCI_DM9009_ID) {
|
| 1540 |
|
|
phy_reg = phy_read(db->ioaddr, db->phy_addr, 18, db->chip_id) & ~0x1000;
|
| 1541 |
|
|
phy_write(db->ioaddr, db->phy_addr, 18, phy_reg, db->chip_id);
|
| 1542 |
|
|
}
|
| 1543 |
|
|
|
| 1544 |
|
|
/* Phyxcer capability setting */
|
| 1545 |
|
|
phy_reg = phy_read(db->ioaddr, db->phy_addr, 4, db->chip_id) & ~0x01e0;
|
| 1546 |
|
|
|
| 1547 |
|
|
if (db->media_mode & DMFE_AUTO) {
|
| 1548 |
|
|
/* AUTO Mode */
|
| 1549 |
|
|
phy_reg |= db->PHY_reg4;
|
| 1550 |
|
|
} else {
|
| 1551 |
|
|
/* Force Mode */
|
| 1552 |
|
|
switch(db->media_mode) {
|
| 1553 |
|
|
case DMFE_10MHF: phy_reg |= 0x20; break;
|
| 1554 |
|
|
case DMFE_10MFD: phy_reg |= 0x40; break;
|
| 1555 |
|
|
case DMFE_100MHF: phy_reg |= 0x80; break;
|
| 1556 |
|
|
case DMFE_100MFD: phy_reg |= 0x100; break;
|
| 1557 |
|
|
}
|
| 1558 |
|
|
if (db->chip_id == PCI_DM9009_ID) phy_reg &= 0x61;
|
| 1559 |
|
|
}
|
| 1560 |
|
|
|
| 1561 |
|
|
/* Write new capability to Phyxcer Reg4 */
|
| 1562 |
|
|
if ( !(phy_reg & 0x01e0)) {
|
| 1563 |
|
|
phy_reg|=db->PHY_reg4;
|
| 1564 |
|
|
db->media_mode|=DMFE_AUTO;
|
| 1565 |
|
|
}
|
| 1566 |
|
|
phy_write(db->ioaddr, db->phy_addr, 4, phy_reg, db->chip_id);
|
| 1567 |
|
|
|
| 1568 |
|
|
/* Restart Auto-Negotiation */
|
| 1569 |
|
|
if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
|
| 1570 |
|
|
phy_write(db->ioaddr, db->phy_addr, 0, 0x1800, db->chip_id);
|
| 1571 |
|
|
if ( !db->chip_type )
|
| 1572 |
|
|
phy_write(db->ioaddr, db->phy_addr, 0, 0x1200, db->chip_id);
|
| 1573 |
|
|
}
|
| 1574 |
|
|
|
| 1575 |
|
|
|
| 1576 |
|
|
/*
|
| 1577 |
|
|
* Process op-mode
|
| 1578 |
|
|
* AUTO mode : PHY controller in Auto-negotiation Mode
|
| 1579 |
|
|
* Force mode: PHY controller in force mode with HUB
|
| 1580 |
|
|
* N-way force capability with SWITCH
|
| 1581 |
|
|
*/
|
| 1582 |
|
|
|
| 1583 |
|
|
static void dmfe_process_mode(struct dmfe_board_info *db)
|
| 1584 |
|
|
{
|
| 1585 |
|
|
u16 phy_reg;
|
| 1586 |
|
|
|
| 1587 |
|
|
/* Full Duplex Mode Check */
|
| 1588 |
|
|
if (db->op_mode & 0x4)
|
| 1589 |
|
|
db->cr6_data |= CR6_FDM; /* Set Full Duplex Bit */
|
| 1590 |
|
|
else
|
| 1591 |
|
|
db->cr6_data &= ~CR6_FDM; /* Clear Full Duplex Bit */
|
| 1592 |
|
|
|
| 1593 |
|
|
/* Transciver Selection */
|
| 1594 |
|
|
if (db->op_mode & 0x10) /* 1M HomePNA */
|
| 1595 |
|
|
db->cr6_data |= 0x40000;/* External MII select */
|
| 1596 |
|
|
else
|
| 1597 |
|
|
db->cr6_data &= ~0x40000;/* Internal 10/100 transciver */
|
| 1598 |
|
|
|
| 1599 |
|
|
update_cr6(db->cr6_data, db->ioaddr);
|
| 1600 |
|
|
|
| 1601 |
|
|
/* 10/100M phyxcer force mode need */
|
| 1602 |
|
|
if ( !(db->media_mode & 0x18)) {
|
| 1603 |
|
|
/* Forece Mode */
|
| 1604 |
|
|
phy_reg = phy_read(db->ioaddr, db->phy_addr, 6, db->chip_id);
|
| 1605 |
|
|
if ( !(phy_reg & 0x1) ) {
|
| 1606 |
|
|
/* parter without N-Way capability */
|
| 1607 |
|
|
phy_reg = 0x0;
|
| 1608 |
|
|
switch(db->op_mode) {
|
| 1609 |
|
|
case DMFE_10MHF: phy_reg = 0x0; break;
|
| 1610 |
|
|
case DMFE_10MFD: phy_reg = 0x100; break;
|
| 1611 |
|
|
case DMFE_100MHF: phy_reg = 0x2000; break;
|
| 1612 |
|
|
case DMFE_100MFD: phy_reg = 0x2100; break;
|
| 1613 |
|
|
}
|
| 1614 |
|
|
phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
|
| 1615 |
|
|
if ( db->chip_type && (db->chip_id == PCI_DM9102_ID) )
|
| 1616 |
|
|
mdelay(20);
|
| 1617 |
|
|
phy_write(db->ioaddr, db->phy_addr, 0, phy_reg, db->chip_id);
|
| 1618 |
|
|
}
|
| 1619 |
|
|
}
|
| 1620 |
|
|
}
|
| 1621 |
|
|
|
| 1622 |
|
|
|
| 1623 |
|
|
/*
|
| 1624 |
|
|
* Write a word to Phy register
|
| 1625 |
|
|
*/
|
| 1626 |
|
|
|
| 1627 |
|
|
static void phy_write(unsigned long iobase, u8 phy_addr, u8 offset, u16 phy_data, u32 chip_id)
|
| 1628 |
|
|
{
|
| 1629 |
|
|
u16 i;
|
| 1630 |
|
|
unsigned long ioaddr;
|
| 1631 |
|
|
|
| 1632 |
|
|
if (chip_id == PCI_DM9132_ID) {
|
| 1633 |
|
|
ioaddr = iobase + 0x80 + offset * 4;
|
| 1634 |
|
|
outw(phy_data, ioaddr);
|
| 1635 |
|
|
} else {
|
| 1636 |
|
|
/* DM9102/DM9102A Chip */
|
| 1637 |
|
|
ioaddr = iobase + DCR9;
|
| 1638 |
|
|
|
| 1639 |
|
|
/* Send 33 synchronization clock to Phy controller */
|
| 1640 |
|
|
for (i = 0; i < 35; i++)
|
| 1641 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_1);
|
| 1642 |
|
|
|
| 1643 |
|
|
/* Send start command(01) to Phy */
|
| 1644 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_0);
|
| 1645 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_1);
|
| 1646 |
|
|
|
| 1647 |
|
|
/* Send write command(01) to Phy */
|
| 1648 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_0);
|
| 1649 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_1);
|
| 1650 |
|
|
|
| 1651 |
|
|
/* Send Phy addres */
|
| 1652 |
|
|
for (i = 0x10; i > 0; i = i >> 1)
|
| 1653 |
|
|
phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
|
| 1654 |
|
|
|
| 1655 |
|
|
/* Send register addres */
|
| 1656 |
|
|
for (i = 0x10; i > 0; i = i >> 1)
|
| 1657 |
|
|
phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
|
| 1658 |
|
|
|
| 1659 |
|
|
/* written trasnition */
|
| 1660 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_1);
|
| 1661 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_0);
|
| 1662 |
|
|
|
| 1663 |
|
|
/* Write a word data to PHY controller */
|
| 1664 |
|
|
for ( i = 0x8000; i > 0; i >>= 1)
|
| 1665 |
|
|
phy_write_1bit(ioaddr, phy_data & i ? PHY_DATA_1 : PHY_DATA_0);
|
| 1666 |
|
|
}
|
| 1667 |
|
|
}
|
| 1668 |
|
|
|
| 1669 |
|
|
|
| 1670 |
|
|
/*
|
| 1671 |
|
|
* Read a word data from phy register
|
| 1672 |
|
|
*/
|
| 1673 |
|
|
|
| 1674 |
|
|
static u16 phy_read(unsigned long iobase, u8 phy_addr, u8 offset, u32 chip_id)
|
| 1675 |
|
|
{
|
| 1676 |
|
|
int i;
|
| 1677 |
|
|
u16 phy_data;
|
| 1678 |
|
|
unsigned long ioaddr;
|
| 1679 |
|
|
|
| 1680 |
|
|
if (chip_id == PCI_DM9132_ID) {
|
| 1681 |
|
|
/* DM9132 Chip */
|
| 1682 |
|
|
ioaddr = iobase + 0x80 + offset * 4;
|
| 1683 |
|
|
phy_data = inw(ioaddr);
|
| 1684 |
|
|
} else {
|
| 1685 |
|
|
/* DM9102/DM9102A Chip */
|
| 1686 |
|
|
ioaddr = iobase + DCR9;
|
| 1687 |
|
|
|
| 1688 |
|
|
/* Send 33 synchronization clock to Phy controller */
|
| 1689 |
|
|
for (i = 0; i < 35; i++)
|
| 1690 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_1);
|
| 1691 |
|
|
|
| 1692 |
|
|
/* Send start command(01) to Phy */
|
| 1693 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_0);
|
| 1694 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_1);
|
| 1695 |
|
|
|
| 1696 |
|
|
/* Send read command(10) to Phy */
|
| 1697 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_1);
|
| 1698 |
|
|
phy_write_1bit(ioaddr, PHY_DATA_0);
|
| 1699 |
|
|
|
| 1700 |
|
|
/* Send Phy addres */
|
| 1701 |
|
|
for (i = 0x10; i > 0; i = i >> 1)
|
| 1702 |
|
|
phy_write_1bit(ioaddr, phy_addr & i ? PHY_DATA_1 : PHY_DATA_0);
|
| 1703 |
|
|
|
| 1704 |
|
|
/* Send register addres */
|
| 1705 |
|
|
for (i = 0x10; i > 0; i = i >> 1)
|
| 1706 |
|
|
phy_write_1bit(ioaddr, offset & i ? PHY_DATA_1 : PHY_DATA_0);
|
| 1707 |
|
|
|
| 1708 |
|
|
/* Skip transition state */
|
| 1709 |
|
|
phy_read_1bit(ioaddr);
|
| 1710 |
|
|
|
| 1711 |
|
|
/* read 16bit data */
|
| 1712 |
|
|
for (phy_data = 0, i = 0; i < 16; i++) {
|
| 1713 |
|
|
phy_data <<= 1;
|
| 1714 |
|
|
phy_data |= phy_read_1bit(ioaddr);
|
| 1715 |
|
|
}
|
| 1716 |
|
|
}
|
| 1717 |
|
|
|
| 1718 |
|
|
return phy_data;
|
| 1719 |
|
|
}
|
| 1720 |
|
|
|
| 1721 |
|
|
|
| 1722 |
|
|
/*
|
| 1723 |
|
|
* Write one bit data to Phy Controller
|
| 1724 |
|
|
*/
|
| 1725 |
|
|
|
| 1726 |
|
|
static void phy_write_1bit(unsigned long ioaddr, u32 phy_data)
|
| 1727 |
|
|
{
|
| 1728 |
|
|
outl(phy_data, ioaddr); /* MII Clock Low */
|
| 1729 |
|
|
udelay(1);
|
| 1730 |
|
|
outl(phy_data | MDCLKH, ioaddr); /* MII Clock High */
|
| 1731 |
|
|
udelay(1);
|
| 1732 |
|
|
outl(phy_data, ioaddr); /* MII Clock Low */
|
| 1733 |
|
|
udelay(1);
|
| 1734 |
|
|
}
|
| 1735 |
|
|
|
| 1736 |
|
|
|
| 1737 |
|
|
/*
|
| 1738 |
|
|
* Read one bit phy data from PHY controller
|
| 1739 |
|
|
*/
|
| 1740 |
|
|
|
| 1741 |
|
|
static u16 phy_read_1bit(unsigned long ioaddr)
|
| 1742 |
|
|
{
|
| 1743 |
|
|
u16 phy_data;
|
| 1744 |
|
|
|
| 1745 |
|
|
outl(0x50000, ioaddr);
|
| 1746 |
|
|
udelay(1);
|
| 1747 |
|
|
phy_data = ( inl(ioaddr) >> 19 ) & 0x1;
|
| 1748 |
|
|
outl(0x40000, ioaddr);
|
| 1749 |
|
|
udelay(1);
|
| 1750 |
|
|
|
| 1751 |
|
|
return phy_data;
|
| 1752 |
|
|
}
|
| 1753 |
|
|
|
| 1754 |
|
|
|
| 1755 |
|
|
/*
|
| 1756 |
|
|
* Calculate the CRC valude of the Rx packet
|
| 1757 |
|
|
* flag = 1 : return the reverse CRC (for the received packet CRC)
|
| 1758 |
|
|
* 0 : return the normal CRC (for Hash Table index)
|
| 1759 |
|
|
*/
|
| 1760 |
|
|
|
| 1761 |
|
|
static inline u32 cal_CRC(unsigned char * Data, unsigned int Len, u8 flag)
|
| 1762 |
|
|
{
|
| 1763 |
|
|
u32 crc = ether_crc_le(Len, Data);
|
| 1764 |
|
|
if (flag) crc = ~crc;
|
| 1765 |
|
|
return crc;
|
| 1766 |
|
|
}
|
| 1767 |
|
|
|
| 1768 |
|
|
|
| 1769 |
|
|
/*
|
| 1770 |
|
|
* Parser SROM and media mode
|
| 1771 |
|
|
*/
|
| 1772 |
|
|
|
| 1773 |
|
|
static void dmfe_parse_srom(struct dmfe_board_info * db)
|
| 1774 |
|
|
{
|
| 1775 |
|
|
char * srom = db->srom;
|
| 1776 |
|
|
int dmfe_mode, tmp_reg;
|
| 1777 |
|
|
|
| 1778 |
|
|
DMFE_DBUG(0, "dmfe_parse_srom() ", 0);
|
| 1779 |
|
|
|
| 1780 |
|
|
/* Init CR15 */
|
| 1781 |
|
|
db->cr15_data = CR15_DEFAULT;
|
| 1782 |
|
|
|
| 1783 |
|
|
/* Check SROM Version */
|
| 1784 |
|
|
if ( ( (int) srom[18] & 0xff) == SROM_V41_CODE) {
|
| 1785 |
|
|
/* SROM V4.01 */
|
| 1786 |
|
|
/* Get NIC support media mode */
|
| 1787 |
|
|
db->NIC_capability = le16_to_cpup(srom + 34);
|
| 1788 |
|
|
db->PHY_reg4 = 0;
|
| 1789 |
|
|
for (tmp_reg = 1; tmp_reg < 0x10; tmp_reg <<= 1) {
|
| 1790 |
|
|
switch( db->NIC_capability & tmp_reg ) {
|
| 1791 |
|
|
case 0x1: db->PHY_reg4 |= 0x0020; break;
|
| 1792 |
|
|
case 0x2: db->PHY_reg4 |= 0x0040; break;
|
| 1793 |
|
|
case 0x4: db->PHY_reg4 |= 0x0080; break;
|
| 1794 |
|
|
case 0x8: db->PHY_reg4 |= 0x0100; break;
|
| 1795 |
|
|
}
|
| 1796 |
|
|
}
|
| 1797 |
|
|
|
| 1798 |
|
|
/* Media Mode Force or not check */
|
| 1799 |
|
|
dmfe_mode = le32_to_cpup(srom + 34) & le32_to_cpup(srom + 36);
|
| 1800 |
|
|
switch(dmfe_mode) {
|
| 1801 |
|
|
case 0x4: dmfe_media_mode = DMFE_100MHF; break; /* 100MHF */
|
| 1802 |
|
|
case 0x2: dmfe_media_mode = DMFE_10MFD; break; /* 10MFD */
|
| 1803 |
|
|
case 0x8: dmfe_media_mode = DMFE_100MFD; break; /* 100MFD */
|
| 1804 |
|
|
case 0x100:
|
| 1805 |
|
|
case 0x200: dmfe_media_mode = DMFE_1M_HPNA; break;/* HomePNA */
|
| 1806 |
|
|
}
|
| 1807 |
|
|
|
| 1808 |
|
|
/* Special Function setting */
|
| 1809 |
|
|
/* VLAN function */
|
| 1810 |
|
|
if ( (SF_mode & 0x1) || (srom[43] & 0x80) )
|
| 1811 |
|
|
db->cr15_data |= 0x40;
|
| 1812 |
|
|
|
| 1813 |
|
|
/* Flow Control */
|
| 1814 |
|
|
if ( (SF_mode & 0x2) || (srom[40] & 0x1) )
|
| 1815 |
|
|
db->cr15_data |= 0x400;
|
| 1816 |
|
|
|
| 1817 |
|
|
/* TX pause packet */
|
| 1818 |
|
|
if ( (SF_mode & 0x4) || (srom[40] & 0xe) )
|
| 1819 |
|
|
db->cr15_data |= 0x9800;
|
| 1820 |
|
|
}
|
| 1821 |
|
|
|
| 1822 |
|
|
/* Parse HPNA parameter */
|
| 1823 |
|
|
db->HPNA_command = 1;
|
| 1824 |
|
|
|
| 1825 |
|
|
/* Accept remote command or not */
|
| 1826 |
|
|
if (HPNA_rx_cmd == 0)
|
| 1827 |
|
|
db->HPNA_command |= 0x8000;
|
| 1828 |
|
|
|
| 1829 |
|
|
/* Issue remote command & operation mode */
|
| 1830 |
|
|
if (HPNA_tx_cmd == 1)
|
| 1831 |
|
|
switch(HPNA_mode) { /* Issue Remote Command */
|
| 1832 |
|
|
case 0: db->HPNA_command |= 0x0904; break;
|
| 1833 |
|
|
case 1: db->HPNA_command |= 0x0a00; break;
|
| 1834 |
|
|
case 2: db->HPNA_command |= 0x0506; break;
|
| 1835 |
|
|
case 3: db->HPNA_command |= 0x0602; break;
|
| 1836 |
|
|
}
|
| 1837 |
|
|
else
|
| 1838 |
|
|
switch(HPNA_mode) { /* Don't Issue */
|
| 1839 |
|
|
case 0: db->HPNA_command |= 0x0004; break;
|
| 1840 |
|
|
case 1: db->HPNA_command |= 0x0000; break;
|
| 1841 |
|
|
case 2: db->HPNA_command |= 0x0006; break;
|
| 1842 |
|
|
case 3: db->HPNA_command |= 0x0002; break;
|
| 1843 |
|
|
}
|
| 1844 |
|
|
|
| 1845 |
|
|
/* Check DM9801 or DM9802 present or not */
|
| 1846 |
|
|
db->HPNA_present = 0;
|
| 1847 |
|
|
update_cr6(db->cr6_data|0x40000, db->ioaddr);
|
| 1848 |
|
|
tmp_reg = phy_read(db->ioaddr, db->phy_addr, 3, db->chip_id);
|
| 1849 |
|
|
if ( ( tmp_reg & 0xfff0 ) == 0xb900 ) {
|
| 1850 |
|
|
/* DM9801 or DM9802 present */
|
| 1851 |
|
|
db->HPNA_timer = 8;
|
| 1852 |
|
|
if ( phy_read(db->ioaddr, db->phy_addr, 31, db->chip_id) == 0x4404) {
|
| 1853 |
|
|
/* DM9801 HomeRun */
|
| 1854 |
|
|
db->HPNA_present = 1;
|
| 1855 |
|
|
dmfe_program_DM9801(db, tmp_reg);
|
| 1856 |
|
|
} else {
|
| 1857 |
|
|
/* DM9802 LongRun */
|
| 1858 |
|
|
db->HPNA_present = 2;
|
| 1859 |
|
|
dmfe_program_DM9802(db);
|
| 1860 |
|
|
}
|
| 1861 |
|
|
}
|
| 1862 |
|
|
|
| 1863 |
|
|
}
|
| 1864 |
|
|
|
| 1865 |
|
|
|
| 1866 |
|
|
/*
|
| 1867 |
|
|
* Init HomeRun DM9801
|
| 1868 |
|
|
*/
|
| 1869 |
|
|
|
| 1870 |
|
|
static void dmfe_program_DM9801(struct dmfe_board_info * db, int HPNA_rev)
|
| 1871 |
|
|
{
|
| 1872 |
|
|
uint reg17, reg25;
|
| 1873 |
|
|
|
| 1874 |
|
|
if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9801_NOISE_FLOOR;
|
| 1875 |
|
|
switch(HPNA_rev) {
|
| 1876 |
|
|
case 0xb900: /* DM9801 E3 */
|
| 1877 |
|
|
db->HPNA_command |= 0x1000;
|
| 1878 |
|
|
reg25 = phy_read(db->ioaddr, db->phy_addr, 24, db->chip_id);
|
| 1879 |
|
|
reg25 = ( (reg25 + HPNA_NoiseFloor) & 0xff) | 0xf000;
|
| 1880 |
|
|
reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
|
| 1881 |
|
|
break;
|
| 1882 |
|
|
case 0xb901: /* DM9801 E4 */
|
| 1883 |
|
|
reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
|
| 1884 |
|
|
reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor;
|
| 1885 |
|
|
reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
|
| 1886 |
|
|
reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor + 3;
|
| 1887 |
|
|
break;
|
| 1888 |
|
|
case 0xb902: /* DM9801 E5 */
|
| 1889 |
|
|
case 0xb903: /* DM9801 E6 */
|
| 1890 |
|
|
default:
|
| 1891 |
|
|
db->HPNA_command |= 0x1000;
|
| 1892 |
|
|
reg25 = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
|
| 1893 |
|
|
reg25 = (reg25 & 0xff00) + HPNA_NoiseFloor - 5;
|
| 1894 |
|
|
reg17 = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id);
|
| 1895 |
|
|
reg17 = (reg17 & 0xfff0) + HPNA_NoiseFloor;
|
| 1896 |
|
|
break;
|
| 1897 |
|
|
}
|
| 1898 |
|
|
phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
|
| 1899 |
|
|
phy_write(db->ioaddr, db->phy_addr, 17, reg17, db->chip_id);
|
| 1900 |
|
|
phy_write(db->ioaddr, db->phy_addr, 25, reg25, db->chip_id);
|
| 1901 |
|
|
}
|
| 1902 |
|
|
|
| 1903 |
|
|
|
| 1904 |
|
|
/*
|
| 1905 |
|
|
* Init HomeRun DM9802
|
| 1906 |
|
|
*/
|
| 1907 |
|
|
|
| 1908 |
|
|
static void dmfe_program_DM9802(struct dmfe_board_info * db)
|
| 1909 |
|
|
{
|
| 1910 |
|
|
uint phy_reg;
|
| 1911 |
|
|
|
| 1912 |
|
|
if ( !HPNA_NoiseFloor ) HPNA_NoiseFloor = DM9802_NOISE_FLOOR;
|
| 1913 |
|
|
phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
|
| 1914 |
|
|
phy_reg = phy_read(db->ioaddr, db->phy_addr, 25, db->chip_id);
|
| 1915 |
|
|
phy_reg = ( phy_reg & 0xff00) + HPNA_NoiseFloor;
|
| 1916 |
|
|
phy_write(db->ioaddr, db->phy_addr, 25, phy_reg, db->chip_id);
|
| 1917 |
|
|
}
|
| 1918 |
|
|
|
| 1919 |
|
|
|
| 1920 |
|
|
/*
|
| 1921 |
|
|
* Check remote HPNA power and speed status. If not correct,
|
| 1922 |
|
|
* issue command again.
|
| 1923 |
|
|
*/
|
| 1924 |
|
|
|
| 1925 |
|
|
static void dmfe_HPNA_remote_cmd_chk(struct dmfe_board_info * db)
|
| 1926 |
|
|
{
|
| 1927 |
|
|
uint phy_reg;
|
| 1928 |
|
|
|
| 1929 |
|
|
/* Got remote device status */
|
| 1930 |
|
|
phy_reg = phy_read(db->ioaddr, db->phy_addr, 17, db->chip_id) & 0x60;
|
| 1931 |
|
|
switch(phy_reg) {
|
| 1932 |
|
|
case 0x00: phy_reg = 0x0a00;break; /* LP/LS */
|
| 1933 |
|
|
case 0x20: phy_reg = 0x0900;break; /* LP/HS */
|
| 1934 |
|
|
case 0x40: phy_reg = 0x0600;break; /* HP/LS */
|
| 1935 |
|
|
case 0x60: phy_reg = 0x0500;break; /* HP/HS */
|
| 1936 |
|
|
}
|
| 1937 |
|
|
|
| 1938 |
|
|
/* Check remote device status match our setting ot not */
|
| 1939 |
|
|
if ( phy_reg != (db->HPNA_command & 0x0f00) ) {
|
| 1940 |
|
|
phy_write(db->ioaddr, db->phy_addr, 16, db->HPNA_command, db->chip_id);
|
| 1941 |
|
|
db->HPNA_timer=8;
|
| 1942 |
|
|
} else
|
| 1943 |
|
|
db->HPNA_timer=600; /* Match, every 10 minutes, check */
|
| 1944 |
|
|
}
|
| 1945 |
|
|
|
| 1946 |
|
|
|
| 1947 |
|
|
|
| 1948 |
|
|
static struct pci_device_id dmfe_pci_tbl[] __devinitdata = {
|
| 1949 |
|
|
{ 0x1282, 0x9132, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9132_ID },
|
| 1950 |
|
|
{ 0x1282, 0x9102, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
|
| 1951 |
|
|
{ 0x1282, 0x9100, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9100_ID },
|
| 1952 |
|
|
{ 0x1282, 0x9009, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9009_ID },
|
| 1953 |
|
|
{ 0x10B9, 0x5261, PCI_ANY_ID, PCI_ANY_ID, 0, 0, PCI_DM9102_ID },
|
| 1954 |
|
|
{ 0, }
|
| 1955 |
|
|
};
|
| 1956 |
|
|
MODULE_DEVICE_TABLE(pci, dmfe_pci_tbl);
|
| 1957 |
|
|
|
| 1958 |
|
|
|
| 1959 |
|
|
static struct pci_driver dmfe_driver = {
|
| 1960 |
|
|
name: "dmfe",
|
| 1961 |
|
|
id_table: dmfe_pci_tbl,
|
| 1962 |
|
|
probe: dmfe_init_one,
|
| 1963 |
|
|
remove: __devexit_p(dmfe_remove_one),
|
| 1964 |
|
|
};
|
| 1965 |
|
|
|
| 1966 |
|
|
MODULE_AUTHOR("Sten Wang, sten_wang@davicom.com.tw");
|
| 1967 |
|
|
MODULE_DESCRIPTION("Davicom DM910X fast ethernet driver");
|
| 1968 |
|
|
MODULE_LICENSE("GPL");
|
| 1969 |
|
|
|
| 1970 |
|
|
MODULE_PARM(debug, "i");
|
| 1971 |
|
|
MODULE_PARM(mode, "i");
|
| 1972 |
|
|
MODULE_PARM(cr6set, "i");
|
| 1973 |
|
|
MODULE_PARM(chkmode, "i");
|
| 1974 |
|
|
MODULE_PARM(HPNA_mode, "i");
|
| 1975 |
|
|
MODULE_PARM(HPNA_rx_cmd, "i");
|
| 1976 |
|
|
MODULE_PARM(HPNA_tx_cmd, "i");
|
| 1977 |
|
|
MODULE_PARM(HPNA_NoiseFloor, "i");
|
| 1978 |
|
|
MODULE_PARM(SF_mode, "i");
|
| 1979 |
|
|
MODULE_PARM_DESC(debug, "Davicom DM9xxx enable debugging (0-1)");
|
| 1980 |
|
|
MODULE_PARM_DESC(mode, "Davicom DM9xxx: Bit 0: 10/100Mbps, bit 2: duplex, bit 8: HomePNA");
|
| 1981 |
|
|
MODULE_PARM_DESC(SF_mode, "Davicom DM9xxx special function (bit 0: VLAN, bit 1 Flow Control, bit 2: TX pause packet)");
|
| 1982 |
|
|
|
| 1983 |
|
|
/* Description:
|
| 1984 |
|
|
* when user used insmod to add module, system invoked init_module()
|
| 1985 |
|
|
* to initilize and register.
|
| 1986 |
|
|
*/
|
| 1987 |
|
|
|
| 1988 |
|
|
static int __init dmfe_init_module(void)
|
| 1989 |
|
|
{
|
| 1990 |
|
|
int rc;
|
| 1991 |
|
|
|
| 1992 |
|
|
printk(version);
|
| 1993 |
|
|
printed_version = 1;
|
| 1994 |
|
|
|
| 1995 |
|
|
DMFE_DBUG(0, "init_module() ", debug);
|
| 1996 |
|
|
|
| 1997 |
|
|
if (debug)
|
| 1998 |
|
|
dmfe_debug = debug; /* set debug flag */
|
| 1999 |
|
|
if (cr6set)
|
| 2000 |
|
|
dmfe_cr6_user_set = cr6set;
|
| 2001 |
|
|
|
| 2002 |
|
|
switch(mode) {
|
| 2003 |
|
|
case DMFE_10MHF:
|
| 2004 |
|
|
case DMFE_100MHF:
|
| 2005 |
|
|
case DMFE_10MFD:
|
| 2006 |
|
|
case DMFE_100MFD:
|
| 2007 |
|
|
case DMFE_1M_HPNA:
|
| 2008 |
|
|
dmfe_media_mode = mode;
|
| 2009 |
|
|
break;
|
| 2010 |
|
|
default:dmfe_media_mode = DMFE_AUTO;
|
| 2011 |
|
|
break;
|
| 2012 |
|
|
}
|
| 2013 |
|
|
|
| 2014 |
|
|
if (HPNA_mode > 4)
|
| 2015 |
|
|
HPNA_mode = 0; /* Default: LP/HS */
|
| 2016 |
|
|
if (HPNA_rx_cmd > 1)
|
| 2017 |
|
|
HPNA_rx_cmd = 0; /* Default: Ignored remote cmd */
|
| 2018 |
|
|
if (HPNA_tx_cmd > 1)
|
| 2019 |
|
|
HPNA_tx_cmd = 0; /* Default: Don't issue remote cmd */
|
| 2020 |
|
|
if (HPNA_NoiseFloor > 15)
|
| 2021 |
|
|
HPNA_NoiseFloor = 0;
|
| 2022 |
|
|
|
| 2023 |
|
|
rc = pci_module_init(&dmfe_driver);
|
| 2024 |
|
|
if (rc < 0)
|
| 2025 |
|
|
return rc;
|
| 2026 |
|
|
|
| 2027 |
|
|
return 0;
|
| 2028 |
|
|
}
|
| 2029 |
|
|
|
| 2030 |
|
|
|
| 2031 |
|
|
/*
|
| 2032 |
|
|
* Description:
|
| 2033 |
|
|
* when user used rmmod to delete module, system invoked clean_module()
|
| 2034 |
|
|
* to un-register all registered services.
|
| 2035 |
|
|
*/
|
| 2036 |
|
|
|
| 2037 |
|
|
static void __exit dmfe_cleanup_module(void)
|
| 2038 |
|
|
{
|
| 2039 |
|
|
DMFE_DBUG(0, "dmfe_clean_module() ", debug);
|
| 2040 |
|
|
pci_unregister_driver(&dmfe_driver);
|
| 2041 |
|
|
}
|
| 2042 |
|
|
|
| 2043 |
|
|
module_init(dmfe_init_module);
|
| 2044 |
|
|
module_exit(dmfe_cleanup_module);
|
