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phoenix |
/*******************************************************************************
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Copyright(c) 1999 - 2004 Intel Corporation. All rights reserved.
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This program is free software; you can redistribute it and/or modify it
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under the terms of the GNU General Public License as published by the Free
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Software Foundation; either version 2 of the License, or (at your option)
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any later version.
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This program is distributed in the hope that it will be useful, but WITHOUT
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ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
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FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
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more details.
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You should have received a copy of the GNU General Public License along with
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this program; if not, write to the Free Software Foundation, Inc., 59
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Temple Place - Suite 330, Boston, MA 02111-1307, USA.
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The full GNU General Public License is included in this distribution in the
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file called LICENSE.
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Contact Information:
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Linux NICS <linux.nics@intel.com>
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Intel Corporation, 5200 N.E. Elam Young Parkway, Hillsboro, OR 97124-6497
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*******************************************************************************/
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/* e1000_hw.h
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* Structures, enums, and macros for the MAC
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*/
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#ifndef _E1000_HW_H_
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#define _E1000_HW_H_
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#include "e1000_osdep.h"
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/* Forward declarations of structures used by the shared code */
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struct e1000_hw;
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struct e1000_hw_stats;
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/* Enumerated types specific to the e1000 hardware */
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/* Media Access Controlers */
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typedef enum {
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e1000_undefined = 0,
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e1000_82542_rev2_0,
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e1000_82542_rev2_1,
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e1000_82543,
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e1000_82544,
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e1000_82540,
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e1000_82545,
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e1000_82545_rev_3,
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e1000_82546,
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e1000_82546_rev_3,
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e1000_82541,
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e1000_82541_rev_2,
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e1000_82547,
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e1000_82547_rev_2,
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e1000_num_macs
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} e1000_mac_type;
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typedef enum {
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e1000_eeprom_uninitialized = 0,
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e1000_eeprom_spi,
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e1000_eeprom_microwire,
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e1000_num_eeprom_types
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} e1000_eeprom_type;
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/* Media Types */
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typedef enum {
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e1000_media_type_copper = 0,
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e1000_media_type_fiber = 1,
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e1000_media_type_internal_serdes = 2,
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e1000_num_media_types
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} e1000_media_type;
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typedef enum {
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e1000_10_half = 0,
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e1000_10_full = 1,
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e1000_100_half = 2,
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e1000_100_full = 3
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} e1000_speed_duplex_type;
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/* Flow Control Settings */
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typedef enum {
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e1000_fc_none = 0,
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e1000_fc_rx_pause = 1,
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e1000_fc_tx_pause = 2,
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e1000_fc_full = 3,
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e1000_fc_default = 0xFF
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} e1000_fc_type;
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/* PCI bus types */
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typedef enum {
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e1000_bus_type_unknown = 0,
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e1000_bus_type_pci,
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e1000_bus_type_pcix,
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e1000_bus_type_reserved
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} e1000_bus_type;
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/* PCI bus speeds */
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typedef enum {
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e1000_bus_speed_unknown = 0,
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e1000_bus_speed_33,
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e1000_bus_speed_66,
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e1000_bus_speed_100,
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e1000_bus_speed_120,
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e1000_bus_speed_133,
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e1000_bus_speed_reserved
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} e1000_bus_speed;
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/* PCI bus widths */
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typedef enum {
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e1000_bus_width_unknown = 0,
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e1000_bus_width_32,
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e1000_bus_width_64,
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e1000_bus_width_reserved
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} e1000_bus_width;
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/* PHY status info structure and supporting enums */
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typedef enum {
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e1000_cable_length_50 = 0,
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e1000_cable_length_50_80,
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e1000_cable_length_80_110,
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e1000_cable_length_110_140,
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e1000_cable_length_140,
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e1000_cable_length_undefined = 0xFF
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} e1000_cable_length;
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typedef enum {
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e1000_igp_cable_length_10 = 10,
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e1000_igp_cable_length_20 = 20,
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e1000_igp_cable_length_30 = 30,
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e1000_igp_cable_length_40 = 40,
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e1000_igp_cable_length_50 = 50,
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e1000_igp_cable_length_60 = 60,
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e1000_igp_cable_length_70 = 70,
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e1000_igp_cable_length_80 = 80,
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e1000_igp_cable_length_90 = 90,
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e1000_igp_cable_length_100 = 100,
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e1000_igp_cable_length_110 = 110,
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e1000_igp_cable_length_120 = 120,
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e1000_igp_cable_length_130 = 130,
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e1000_igp_cable_length_140 = 140,
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e1000_igp_cable_length_150 = 150,
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e1000_igp_cable_length_160 = 160,
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e1000_igp_cable_length_170 = 170,
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e1000_igp_cable_length_180 = 180
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} e1000_igp_cable_length;
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typedef enum {
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e1000_10bt_ext_dist_enable_normal = 0,
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e1000_10bt_ext_dist_enable_lower,
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e1000_10bt_ext_dist_enable_undefined = 0xFF
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} e1000_10bt_ext_dist_enable;
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typedef enum {
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e1000_rev_polarity_normal = 0,
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e1000_rev_polarity_reversed,
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e1000_rev_polarity_undefined = 0xFF
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} e1000_rev_polarity;
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typedef enum {
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e1000_downshift_normal = 0,
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e1000_downshift_activated,
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e1000_downshift_undefined = 0xFF
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} e1000_downshift;
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typedef enum {
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e1000_polarity_reversal_enabled = 0,
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e1000_polarity_reversal_disabled,
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e1000_polarity_reversal_undefined = 0xFF
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} e1000_polarity_reversal;
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typedef enum {
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e1000_auto_x_mode_manual_mdi = 0,
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e1000_auto_x_mode_manual_mdix,
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e1000_auto_x_mode_auto1,
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e1000_auto_x_mode_auto2,
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e1000_auto_x_mode_undefined = 0xFF
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} e1000_auto_x_mode;
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typedef enum {
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e1000_1000t_rx_status_not_ok = 0,
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e1000_1000t_rx_status_ok,
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e1000_1000t_rx_status_undefined = 0xFF
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} e1000_1000t_rx_status;
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typedef enum {
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e1000_phy_m88 = 0,
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e1000_phy_igp,
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e1000_phy_undefined = 0xFF
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} e1000_phy_type;
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typedef enum {
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e1000_ms_hw_default = 0,
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e1000_ms_force_master,
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e1000_ms_force_slave,
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e1000_ms_auto
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} e1000_ms_type;
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typedef enum {
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e1000_ffe_config_enabled = 0,
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e1000_ffe_config_active,
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e1000_ffe_config_blocked
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} e1000_ffe_config;
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typedef enum {
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e1000_dsp_config_disabled = 0,
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e1000_dsp_config_enabled,
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e1000_dsp_config_activated,
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e1000_dsp_config_undefined = 0xFF
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} e1000_dsp_config;
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struct e1000_phy_info {
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e1000_cable_length cable_length;
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e1000_10bt_ext_dist_enable extended_10bt_distance;
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e1000_rev_polarity cable_polarity;
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e1000_downshift downshift;
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e1000_polarity_reversal polarity_correction;
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e1000_auto_x_mode mdix_mode;
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e1000_1000t_rx_status local_rx;
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e1000_1000t_rx_status remote_rx;
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};
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struct e1000_phy_stats {
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uint32_t idle_errors;
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uint32_t receive_errors;
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};
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struct e1000_eeprom_info {
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e1000_eeprom_type type;
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uint16_t word_size;
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uint16_t opcode_bits;
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uint16_t address_bits;
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uint16_t delay_usec;
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uint16_t page_size;
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};
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/* Error Codes */
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#define E1000_SUCCESS 0
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#define E1000_ERR_EEPROM 1
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#define E1000_ERR_PHY 2
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#define E1000_ERR_CONFIG 3
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#define E1000_ERR_PARAM 4
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#define E1000_ERR_MAC_TYPE 5
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#define E1000_ERR_PHY_TYPE 6
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/* Function prototypes */
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/* Initialization */
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int32_t e1000_reset_hw(struct e1000_hw *hw);
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int32_t e1000_init_hw(struct e1000_hw *hw);
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int32_t e1000_set_mac_type(struct e1000_hw *hw);
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void e1000_set_media_type(struct e1000_hw *hw);
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/* Link Configuration */
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int32_t e1000_setup_link(struct e1000_hw *hw);
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int32_t e1000_phy_setup_autoneg(struct e1000_hw *hw);
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void e1000_config_collision_dist(struct e1000_hw *hw);
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int32_t e1000_config_fc_after_link_up(struct e1000_hw *hw);
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int32_t e1000_check_for_link(struct e1000_hw *hw);
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int32_t e1000_get_speed_and_duplex(struct e1000_hw *hw, uint16_t * speed, uint16_t * duplex);
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int32_t e1000_wait_autoneg(struct e1000_hw *hw);
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int32_t e1000_force_mac_fc(struct e1000_hw *hw);
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/* PHY */
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int32_t e1000_read_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t *phy_data);
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int32_t e1000_write_phy_reg(struct e1000_hw *hw, uint32_t reg_addr, uint16_t data);
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void e1000_phy_hw_reset(struct e1000_hw *hw);
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int32_t e1000_phy_reset(struct e1000_hw *hw);
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int32_t e1000_detect_gig_phy(struct e1000_hw *hw);
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int32_t e1000_phy_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
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int32_t e1000_phy_m88_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
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int32_t e1000_phy_igp_get_info(struct e1000_hw *hw, struct e1000_phy_info *phy_info);
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int32_t e1000_get_cable_length(struct e1000_hw *hw, uint16_t *min_length, uint16_t *max_length);
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int32_t e1000_check_polarity(struct e1000_hw *hw, uint16_t *polarity);
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int32_t e1000_check_downshift(struct e1000_hw *hw);
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int32_t e1000_validate_mdi_setting(struct e1000_hw *hw);
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/* EEPROM Functions */
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void e1000_init_eeprom_params(struct e1000_hw *hw);
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int32_t e1000_read_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
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int32_t e1000_validate_eeprom_checksum(struct e1000_hw *hw);
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int32_t e1000_update_eeprom_checksum(struct e1000_hw *hw);
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int32_t e1000_write_eeprom(struct e1000_hw *hw, uint16_t reg, uint16_t words, uint16_t *data);
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int32_t e1000_read_part_num(struct e1000_hw *hw, uint32_t * part_num);
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int32_t e1000_read_mac_addr(struct e1000_hw * hw);
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/* Filters (multicast, vlan, receive) */
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void e1000_init_rx_addrs(struct e1000_hw *hw);
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void e1000_mc_addr_list_update(struct e1000_hw *hw, uint8_t * mc_addr_list, uint32_t mc_addr_count, uint32_t pad, uint32_t rar_used_count);
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uint32_t e1000_hash_mc_addr(struct e1000_hw *hw, uint8_t * mc_addr);
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void e1000_mta_set(struct e1000_hw *hw, uint32_t hash_value);
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void e1000_rar_set(struct e1000_hw *hw, uint8_t * mc_addr, uint32_t rar_index);
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void e1000_write_vfta(struct e1000_hw *hw, uint32_t offset, uint32_t value);
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void e1000_clear_vfta(struct e1000_hw *hw);
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/* LED functions */
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int32_t e1000_setup_led(struct e1000_hw *hw);
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int32_t e1000_cleanup_led(struct e1000_hw *hw);
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int32_t e1000_led_on(struct e1000_hw *hw);
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int32_t e1000_led_off(struct e1000_hw *hw);
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/* Adaptive IFS Functions */
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/* Everything else */
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void e1000_clear_hw_cntrs(struct e1000_hw *hw);
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void e1000_reset_adaptive(struct e1000_hw *hw);
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void e1000_update_adaptive(struct e1000_hw *hw);
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void e1000_tbi_adjust_stats(struct e1000_hw *hw, struct e1000_hw_stats *stats, uint32_t frame_len, uint8_t * mac_addr);
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void e1000_get_bus_info(struct e1000_hw *hw);
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void e1000_pci_set_mwi(struct e1000_hw *hw);
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void e1000_pci_clear_mwi(struct e1000_hw *hw);
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void e1000_read_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
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void e1000_write_pci_cfg(struct e1000_hw *hw, uint32_t reg, uint16_t * value);
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/* Port I/O is only supported on 82544 and newer */
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uint32_t e1000_io_read(struct e1000_hw *hw, unsigned long port);
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uint32_t e1000_read_reg_io(struct e1000_hw *hw, uint32_t offset);
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322 |
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|
void e1000_io_write(struct e1000_hw *hw, unsigned long port, uint32_t value);
|
323 |
|
|
void e1000_write_reg_io(struct e1000_hw *hw, uint32_t offset, uint32_t value);
|
324 |
|
|
int32_t e1000_config_dsp_after_link_change(struct e1000_hw *hw, boolean_t link_up);
|
325 |
|
|
int32_t e1000_set_d3_lplu_state(struct e1000_hw *hw, boolean_t active);
|
326 |
|
|
|
327 |
|
|
#define E1000_READ_REG_IO(a, reg) \
|
328 |
|
|
e1000_read_reg_io((a), E1000_##reg)
|
329 |
|
|
#define E1000_WRITE_REG_IO(a, reg, val) \
|
330 |
|
|
e1000_write_reg_io((a), E1000_##reg, val)
|
331 |
|
|
|
332 |
|
|
/* PCI Device IDs */
|
333 |
|
|
#define E1000_DEV_ID_82542 0x1000
|
334 |
|
|
#define E1000_DEV_ID_82543GC_FIBER 0x1001
|
335 |
|
|
#define E1000_DEV_ID_82543GC_COPPER 0x1004
|
336 |
|
|
#define E1000_DEV_ID_82544EI_COPPER 0x1008
|
337 |
|
|
#define E1000_DEV_ID_82544EI_FIBER 0x1009
|
338 |
|
|
#define E1000_DEV_ID_82544GC_COPPER 0x100C
|
339 |
|
|
#define E1000_DEV_ID_82544GC_LOM 0x100D
|
340 |
|
|
#define E1000_DEV_ID_82540EM 0x100E
|
341 |
|
|
#define E1000_DEV_ID_82540EM_LOM 0x1015
|
342 |
|
|
#define E1000_DEV_ID_82540EP_LOM 0x1016
|
343 |
|
|
#define E1000_DEV_ID_82540EP 0x1017
|
344 |
|
|
#define E1000_DEV_ID_82540EP_LP 0x101E
|
345 |
|
|
#define E1000_DEV_ID_82545EM_COPPER 0x100F
|
346 |
|
|
#define E1000_DEV_ID_82545EM_FIBER 0x1011
|
347 |
|
|
#define E1000_DEV_ID_82545GM_COPPER 0x1026
|
348 |
|
|
#define E1000_DEV_ID_82545GM_FIBER 0x1027
|
349 |
|
|
#define E1000_DEV_ID_82545GM_SERDES 0x1028
|
350 |
|
|
#define E1000_DEV_ID_82546EB_COPPER 0x1010
|
351 |
|
|
#define E1000_DEV_ID_82546EB_FIBER 0x1012
|
352 |
|
|
#define E1000_DEV_ID_82546EB_QUAD_COPPER 0x101D
|
353 |
|
|
#define E1000_DEV_ID_82541EI 0x1013
|
354 |
|
|
#define E1000_DEV_ID_82541EI_MOBILE 0x1018
|
355 |
|
|
#define E1000_DEV_ID_82541ER 0x1078
|
356 |
|
|
#define E1000_DEV_ID_82547GI 0x1075
|
357 |
|
|
#define E1000_DEV_ID_82541GI 0x1076
|
358 |
|
|
#define E1000_DEV_ID_82541GI_MOBILE 0x1077
|
359 |
|
|
#define E1000_DEV_ID_82546GB_COPPER 0x1079
|
360 |
|
|
#define E1000_DEV_ID_82546GB_FIBER 0x107A
|
361 |
|
|
#define E1000_DEV_ID_82546GB_SERDES 0x107B
|
362 |
|
|
#define E1000_DEV_ID_82547EI 0x1019
|
363 |
|
|
|
364 |
|
|
#define NODE_ADDRESS_SIZE 6
|
365 |
|
|
#define ETH_LENGTH_OF_ADDRESS 6
|
366 |
|
|
|
367 |
|
|
/* MAC decode size is 128K - This is the size of BAR0 */
|
368 |
|
|
#define MAC_DECODE_SIZE (128 * 1024)
|
369 |
|
|
|
370 |
|
|
#define E1000_82542_2_0_REV_ID 2
|
371 |
|
|
#define E1000_82542_2_1_REV_ID 3
|
372 |
|
|
|
373 |
|
|
#define SPEED_10 10
|
374 |
|
|
#define SPEED_100 100
|
375 |
|
|
#define SPEED_1000 1000
|
376 |
|
|
#define HALF_DUPLEX 1
|
377 |
|
|
#define FULL_DUPLEX 2
|
378 |
|
|
|
379 |
|
|
/* The sizes (in bytes) of a ethernet packet */
|
380 |
|
|
#define ENET_HEADER_SIZE 14
|
381 |
|
|
#define MAXIMUM_ETHERNET_FRAME_SIZE 1518 /* With FCS */
|
382 |
|
|
#define MINIMUM_ETHERNET_FRAME_SIZE 64 /* With FCS */
|
383 |
|
|
#define ETHERNET_FCS_SIZE 4
|
384 |
|
|
#define MAXIMUM_ETHERNET_PACKET_SIZE \
|
385 |
|
|
(MAXIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
|
386 |
|
|
#define MINIMUM_ETHERNET_PACKET_SIZE \
|
387 |
|
|
(MINIMUM_ETHERNET_FRAME_SIZE - ETHERNET_FCS_SIZE)
|
388 |
|
|
#define CRC_LENGTH ETHERNET_FCS_SIZE
|
389 |
|
|
#define MAX_JUMBO_FRAME_SIZE 0x3F00
|
390 |
|
|
|
391 |
|
|
|
392 |
|
|
/* 802.1q VLAN Packet Sizes */
|
393 |
|
|
#define VLAN_TAG_SIZE 4 /* 802.3ac tag (not DMAed) */
|
394 |
|
|
|
395 |
|
|
/* Ethertype field values */
|
396 |
|
|
#define ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.3ac packet */
|
397 |
|
|
#define ETHERNET_IP_TYPE 0x0800 /* IP packets */
|
398 |
|
|
#define ETHERNET_ARP_TYPE 0x0806 /* Address Resolution Protocol (ARP) */
|
399 |
|
|
|
400 |
|
|
/* Packet Header defines */
|
401 |
|
|
#define IP_PROTOCOL_TCP 6
|
402 |
|
|
#define IP_PROTOCOL_UDP 0x11
|
403 |
|
|
|
404 |
|
|
/* This defines the bits that are set in the Interrupt Mask
|
405 |
|
|
* Set/Read Register. Each bit is documented below:
|
406 |
|
|
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
|
407 |
|
|
* o RXSEQ = Receive Sequence Error
|
408 |
|
|
*/
|
409 |
|
|
#define POLL_IMS_ENABLE_MASK ( \
|
410 |
|
|
E1000_IMS_RXDMT0 | \
|
411 |
|
|
E1000_IMS_RXSEQ)
|
412 |
|
|
|
413 |
|
|
/* This defines the bits that are set in the Interrupt Mask
|
414 |
|
|
* Set/Read Register. Each bit is documented below:
|
415 |
|
|
* o RXT0 = Receiver Timer Interrupt (ring 0)
|
416 |
|
|
* o TXDW = Transmit Descriptor Written Back
|
417 |
|
|
* o RXDMT0 = Receive Descriptor Minimum Threshold hit (ring 0)
|
418 |
|
|
* o RXSEQ = Receive Sequence Error
|
419 |
|
|
* o LSC = Link Status Change
|
420 |
|
|
*/
|
421 |
|
|
#define IMS_ENABLE_MASK ( \
|
422 |
|
|
E1000_IMS_RXT0 | \
|
423 |
|
|
E1000_IMS_TXDW | \
|
424 |
|
|
E1000_IMS_RXDMT0 | \
|
425 |
|
|
E1000_IMS_RXSEQ | \
|
426 |
|
|
E1000_IMS_LSC)
|
427 |
|
|
|
428 |
|
|
/* Number of high/low register pairs in the RAR. The RAR (Receive Address
|
429 |
|
|
* Registers) holds the directed and multicast addresses that we monitor. We
|
430 |
|
|
* reserve one of these spots for our directed address, allowing us room for
|
431 |
|
|
* E1000_RAR_ENTRIES - 1 multicast addresses.
|
432 |
|
|
*/
|
433 |
|
|
#define E1000_RAR_ENTRIES 15
|
434 |
|
|
|
435 |
|
|
#define MIN_NUMBER_OF_DESCRIPTORS 8
|
436 |
|
|
#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8
|
437 |
|
|
|
438 |
|
|
/* Receive Descriptor */
|
439 |
|
|
struct e1000_rx_desc {
|
440 |
|
|
uint64_t buffer_addr; /* Address of the descriptor's data buffer */
|
441 |
|
|
uint16_t length; /* Length of data DMAed into data buffer */
|
442 |
|
|
uint16_t csum; /* Packet checksum */
|
443 |
|
|
uint8_t status; /* Descriptor status */
|
444 |
|
|
uint8_t errors; /* Descriptor Errors */
|
445 |
|
|
uint16_t special;
|
446 |
|
|
};
|
447 |
|
|
|
448 |
|
|
/* Receive Decriptor bit definitions */
|
449 |
|
|
#define E1000_RXD_STAT_DD 0x01 /* Descriptor Done */
|
450 |
|
|
#define E1000_RXD_STAT_EOP 0x02 /* End of Packet */
|
451 |
|
|
#define E1000_RXD_STAT_IXSM 0x04 /* Ignore checksum */
|
452 |
|
|
#define E1000_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */
|
453 |
|
|
#define E1000_RXD_STAT_TCPCS 0x20 /* TCP xsum calculated */
|
454 |
|
|
#define E1000_RXD_STAT_IPCS 0x40 /* IP xsum calculated */
|
455 |
|
|
#define E1000_RXD_STAT_PIF 0x80 /* passed in-exact filter */
|
456 |
|
|
#define E1000_RXD_ERR_CE 0x01 /* CRC Error */
|
457 |
|
|
#define E1000_RXD_ERR_SE 0x02 /* Symbol Error */
|
458 |
|
|
#define E1000_RXD_ERR_SEQ 0x04 /* Sequence Error */
|
459 |
|
|
#define E1000_RXD_ERR_CXE 0x10 /* Carrier Extension Error */
|
460 |
|
|
#define E1000_RXD_ERR_TCPE 0x20 /* TCP/UDP Checksum Error */
|
461 |
|
|
#define E1000_RXD_ERR_IPE 0x40 /* IP Checksum Error */
|
462 |
|
|
#define E1000_RXD_ERR_RXE 0x80 /* Rx Data Error */
|
463 |
|
|
#define E1000_RXD_SPC_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */
|
464 |
|
|
#define E1000_RXD_SPC_PRI_MASK 0xE000 /* Priority is in upper 3 bits */
|
465 |
|
|
#define E1000_RXD_SPC_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */
|
466 |
|
|
#define E1000_RXD_SPC_CFI_MASK 0x1000 /* CFI is bit 12 */
|
467 |
|
|
#define E1000_RXD_SPC_CFI_SHIFT 0x000C /* CFI is bit 12 */
|
468 |
|
|
|
469 |
|
|
/* mask to determine if packets should be dropped due to frame errors */
|
470 |
|
|
#define E1000_RXD_ERR_FRAME_ERR_MASK ( \
|
471 |
|
|
E1000_RXD_ERR_CE | \
|
472 |
|
|
E1000_RXD_ERR_SE | \
|
473 |
|
|
E1000_RXD_ERR_SEQ | \
|
474 |
|
|
E1000_RXD_ERR_CXE | \
|
475 |
|
|
E1000_RXD_ERR_RXE)
|
476 |
|
|
|
477 |
|
|
/* Transmit Descriptor */
|
478 |
|
|
struct e1000_tx_desc {
|
479 |
|
|
uint64_t buffer_addr; /* Address of the descriptor's data buffer */
|
480 |
|
|
union {
|
481 |
|
|
uint32_t data;
|
482 |
|
|
struct {
|
483 |
|
|
uint16_t length; /* Data buffer length */
|
484 |
|
|
uint8_t cso; /* Checksum offset */
|
485 |
|
|
uint8_t cmd; /* Descriptor control */
|
486 |
|
|
} flags;
|
487 |
|
|
} lower;
|
488 |
|
|
union {
|
489 |
|
|
uint32_t data;
|
490 |
|
|
struct {
|
491 |
|
|
uint8_t status; /* Descriptor status */
|
492 |
|
|
uint8_t css; /* Checksum start */
|
493 |
|
|
uint16_t special;
|
494 |
|
|
} fields;
|
495 |
|
|
} upper;
|
496 |
|
|
};
|
497 |
|
|
|
498 |
|
|
/* Transmit Descriptor bit definitions */
|
499 |
|
|
#define E1000_TXD_DTYP_D 0x00100000 /* Data Descriptor */
|
500 |
|
|
#define E1000_TXD_DTYP_C 0x00000000 /* Context Descriptor */
|
501 |
|
|
#define E1000_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */
|
502 |
|
|
#define E1000_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */
|
503 |
|
|
#define E1000_TXD_CMD_EOP 0x01000000 /* End of Packet */
|
504 |
|
|
#define E1000_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */
|
505 |
|
|
#define E1000_TXD_CMD_IC 0x04000000 /* Insert Checksum */
|
506 |
|
|
#define E1000_TXD_CMD_RS 0x08000000 /* Report Status */
|
507 |
|
|
#define E1000_TXD_CMD_RPS 0x10000000 /* Report Packet Sent */
|
508 |
|
|
#define E1000_TXD_CMD_DEXT 0x20000000 /* Descriptor extension (0 = legacy) */
|
509 |
|
|
#define E1000_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */
|
510 |
|
|
#define E1000_TXD_CMD_IDE 0x80000000 /* Enable Tidv register */
|
511 |
|
|
#define E1000_TXD_STAT_DD 0x00000001 /* Descriptor Done */
|
512 |
|
|
#define E1000_TXD_STAT_EC 0x00000002 /* Excess Collisions */
|
513 |
|
|
#define E1000_TXD_STAT_LC 0x00000004 /* Late Collisions */
|
514 |
|
|
#define E1000_TXD_STAT_TU 0x00000008 /* Transmit underrun */
|
515 |
|
|
#define E1000_TXD_CMD_TCP 0x01000000 /* TCP packet */
|
516 |
|
|
#define E1000_TXD_CMD_IP 0x02000000 /* IP packet */
|
517 |
|
|
#define E1000_TXD_CMD_TSE 0x04000000 /* TCP Seg enable */
|
518 |
|
|
#define E1000_TXD_STAT_TC 0x00000004 /* Tx Underrun */
|
519 |
|
|
|
520 |
|
|
/* Offload Context Descriptor */
|
521 |
|
|
struct e1000_context_desc {
|
522 |
|
|
union {
|
523 |
|
|
uint32_t ip_config;
|
524 |
|
|
struct {
|
525 |
|
|
uint8_t ipcss; /* IP checksum start */
|
526 |
|
|
uint8_t ipcso; /* IP checksum offset */
|
527 |
|
|
uint16_t ipcse; /* IP checksum end */
|
528 |
|
|
} ip_fields;
|
529 |
|
|
} lower_setup;
|
530 |
|
|
union {
|
531 |
|
|
uint32_t tcp_config;
|
532 |
|
|
struct {
|
533 |
|
|
uint8_t tucss; /* TCP checksum start */
|
534 |
|
|
uint8_t tucso; /* TCP checksum offset */
|
535 |
|
|
uint16_t tucse; /* TCP checksum end */
|
536 |
|
|
} tcp_fields;
|
537 |
|
|
} upper_setup;
|
538 |
|
|
uint32_t cmd_and_length; /* */
|
539 |
|
|
union {
|
540 |
|
|
uint32_t data;
|
541 |
|
|
struct {
|
542 |
|
|
uint8_t status; /* Descriptor status */
|
543 |
|
|
uint8_t hdr_len; /* Header length */
|
544 |
|
|
uint16_t mss; /* Maximum segment size */
|
545 |
|
|
} fields;
|
546 |
|
|
} tcp_seg_setup;
|
547 |
|
|
};
|
548 |
|
|
|
549 |
|
|
/* Offload data descriptor */
|
550 |
|
|
struct e1000_data_desc {
|
551 |
|
|
uint64_t buffer_addr; /* Address of the descriptor's buffer address */
|
552 |
|
|
union {
|
553 |
|
|
uint32_t data;
|
554 |
|
|
struct {
|
555 |
|
|
uint16_t length; /* Data buffer length */
|
556 |
|
|
uint8_t typ_len_ext; /* */
|
557 |
|
|
uint8_t cmd; /* */
|
558 |
|
|
} flags;
|
559 |
|
|
} lower;
|
560 |
|
|
union {
|
561 |
|
|
uint32_t data;
|
562 |
|
|
struct {
|
563 |
|
|
uint8_t status; /* Descriptor status */
|
564 |
|
|
uint8_t popts; /* Packet Options */
|
565 |
|
|
uint16_t special; /* */
|
566 |
|
|
} fields;
|
567 |
|
|
} upper;
|
568 |
|
|
};
|
569 |
|
|
|
570 |
|
|
/* Filters */
|
571 |
|
|
#define E1000_NUM_UNICAST 16 /* Unicast filter entries */
|
572 |
|
|
#define E1000_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */
|
573 |
|
|
#define E1000_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */
|
574 |
|
|
|
575 |
|
|
|
576 |
|
|
/* Receive Address Register */
|
577 |
|
|
struct e1000_rar {
|
578 |
|
|
volatile uint32_t low; /* receive address low */
|
579 |
|
|
volatile uint32_t high; /* receive address high */
|
580 |
|
|
};
|
581 |
|
|
|
582 |
|
|
/* Number of entries in the Multicast Table Array (MTA). */
|
583 |
|
|
#define E1000_NUM_MTA_REGISTERS 128
|
584 |
|
|
|
585 |
|
|
/* IPv4 Address Table Entry */
|
586 |
|
|
struct e1000_ipv4_at_entry {
|
587 |
|
|
volatile uint32_t ipv4_addr; /* IP Address (RW) */
|
588 |
|
|
volatile uint32_t reserved;
|
589 |
|
|
};
|
590 |
|
|
|
591 |
|
|
/* Four wakeup IP addresses are supported */
|
592 |
|
|
#define E1000_WAKEUP_IP_ADDRESS_COUNT_MAX 4
|
593 |
|
|
#define E1000_IP4AT_SIZE E1000_WAKEUP_IP_ADDRESS_COUNT_MAX
|
594 |
|
|
#define E1000_IP6AT_SIZE 1
|
595 |
|
|
|
596 |
|
|
/* IPv6 Address Table Entry */
|
597 |
|
|
struct e1000_ipv6_at_entry {
|
598 |
|
|
volatile uint8_t ipv6_addr[16];
|
599 |
|
|
};
|
600 |
|
|
|
601 |
|
|
/* Flexible Filter Length Table Entry */
|
602 |
|
|
struct e1000_fflt_entry {
|
603 |
|
|
volatile uint32_t length; /* Flexible Filter Length (RW) */
|
604 |
|
|
volatile uint32_t reserved;
|
605 |
|
|
};
|
606 |
|
|
|
607 |
|
|
/* Flexible Filter Mask Table Entry */
|
608 |
|
|
struct e1000_ffmt_entry {
|
609 |
|
|
volatile uint32_t mask; /* Flexible Filter Mask (RW) */
|
610 |
|
|
volatile uint32_t reserved;
|
611 |
|
|
};
|
612 |
|
|
|
613 |
|
|
/* Flexible Filter Value Table Entry */
|
614 |
|
|
struct e1000_ffvt_entry {
|
615 |
|
|
volatile uint32_t value; /* Flexible Filter Value (RW) */
|
616 |
|
|
volatile uint32_t reserved;
|
617 |
|
|
};
|
618 |
|
|
|
619 |
|
|
/* Four Flexible Filters are supported */
|
620 |
|
|
#define E1000_FLEXIBLE_FILTER_COUNT_MAX 4
|
621 |
|
|
|
622 |
|
|
/* Each Flexible Filter is at most 128 (0x80) bytes in length */
|
623 |
|
|
#define E1000_FLEXIBLE_FILTER_SIZE_MAX 128
|
624 |
|
|
|
625 |
|
|
#define E1000_FFLT_SIZE E1000_FLEXIBLE_FILTER_COUNT_MAX
|
626 |
|
|
#define E1000_FFMT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
|
627 |
|
|
#define E1000_FFVT_SIZE E1000_FLEXIBLE_FILTER_SIZE_MAX
|
628 |
|
|
|
629 |
|
|
/* Register Set. (82543, 82544)
|
630 |
|
|
*
|
631 |
|
|
* Registers are defined to be 32 bits and should be accessed as 32 bit values.
|
632 |
|
|
* These registers are physically located on the NIC, but are mapped into the
|
633 |
|
|
* host memory address space.
|
634 |
|
|
*
|
635 |
|
|
* RW - register is both readable and writable
|
636 |
|
|
* RO - register is read only
|
637 |
|
|
* WO - register is write only
|
638 |
|
|
* R/clr - register is read only and is cleared when read
|
639 |
|
|
* A - register array
|
640 |
|
|
*/
|
641 |
|
|
#define E1000_CTRL 0x00000 /* Device Control - RW */
|
642 |
|
|
#define E1000_CTRL_DUP 0x00004 /* Device Control Duplicate (Shadow) - RW */
|
643 |
|
|
#define E1000_STATUS 0x00008 /* Device Status - RO */
|
644 |
|
|
#define E1000_EECD 0x00010 /* EEPROM/Flash Control - RW */
|
645 |
|
|
#define E1000_EERD 0x00014 /* EEPROM Read - RW */
|
646 |
|
|
#define E1000_CTRL_EXT 0x00018 /* Extended Device Control - RW */
|
647 |
|
|
#define E1000_FLA 0x0001C /* Flash Access - RW */
|
648 |
|
|
#define E1000_MDIC 0x00020 /* MDI Control - RW */
|
649 |
|
|
#define E1000_FCAL 0x00028 /* Flow Control Address Low - RW */
|
650 |
|
|
#define E1000_FCAH 0x0002C /* Flow Control Address High -RW */
|
651 |
|
|
#define E1000_FCT 0x00030 /* Flow Control Type - RW */
|
652 |
|
|
#define E1000_VET 0x00038 /* VLAN Ether Type - RW */
|
653 |
|
|
#define E1000_ICR 0x000C0 /* Interrupt Cause Read - R/clr */
|
654 |
|
|
#define E1000_ITR 0x000C4 /* Interrupt Throttling Rate - RW */
|
655 |
|
|
#define E1000_ICS 0x000C8 /* Interrupt Cause Set - WO */
|
656 |
|
|
#define E1000_IMS 0x000D0 /* Interrupt Mask Set - RW */
|
657 |
|
|
#define E1000_IMC 0x000D8 /* Interrupt Mask Clear - WO */
|
658 |
|
|
#define E1000_RCTL 0x00100 /* RX Control - RW */
|
659 |
|
|
#define E1000_FCTTV 0x00170 /* Flow Control Transmit Timer Value - RW */
|
660 |
|
|
#define E1000_TXCW 0x00178 /* TX Configuration Word - RW */
|
661 |
|
|
#define E1000_RXCW 0x00180 /* RX Configuration Word - RO */
|
662 |
|
|
#define E1000_TCTL 0x00400 /* TX Control - RW */
|
663 |
|
|
#define E1000_TIPG 0x00410 /* TX Inter-packet gap -RW */
|
664 |
|
|
#define E1000_TBT 0x00448 /* TX Burst Timer - RW */
|
665 |
|
|
#define E1000_AIT 0x00458 /* Adaptive Interframe Spacing Throttle - RW */
|
666 |
|
|
#define E1000_LEDCTL 0x00E00 /* LED Control - RW */
|
667 |
|
|
#define E1000_PBA 0x01000 /* Packet Buffer Allocation - RW */
|
668 |
|
|
#define E1000_FCRTL 0x02160 /* Flow Control Receive Threshold Low - RW */
|
669 |
|
|
#define E1000_FCRTH 0x02168 /* Flow Control Receive Threshold High - RW */
|
670 |
|
|
#define E1000_RDBAL 0x02800 /* RX Descriptor Base Address Low - RW */
|
671 |
|
|
#define E1000_RDBAH 0x02804 /* RX Descriptor Base Address High - RW */
|
672 |
|
|
#define E1000_RDLEN 0x02808 /* RX Descriptor Length - RW */
|
673 |
|
|
#define E1000_RDH 0x02810 /* RX Descriptor Head - RW */
|
674 |
|
|
#define E1000_RDT 0x02818 /* RX Descriptor Tail - RW */
|
675 |
|
|
#define E1000_RDTR 0x02820 /* RX Delay Timer - RW */
|
676 |
|
|
#define E1000_RXDCTL 0x02828 /* RX Descriptor Control - RW */
|
677 |
|
|
#define E1000_RADV 0x0282C /* RX Interrupt Absolute Delay Timer - RW */
|
678 |
|
|
#define E1000_RSRPD 0x02C00 /* RX Small Packet Detect - RW */
|
679 |
|
|
#define E1000_TXDMAC 0x03000 /* TX DMA Control - RW */
|
680 |
|
|
#define E1000_TDFH 0x03410 /* TX Data FIFO Head - RW */
|
681 |
|
|
#define E1000_TDFT 0x03418 /* TX Data FIFO Tail - RW */
|
682 |
|
|
#define E1000_TDFHS 0x03420 /* TX Data FIFO Head Saved - RW */
|
683 |
|
|
#define E1000_TDFTS 0x03428 /* TX Data FIFO Tail Saved - RW */
|
684 |
|
|
#define E1000_TDFPC 0x03430 /* TX Data FIFO Packet Count - RW */
|
685 |
|
|
#define E1000_TDBAL 0x03800 /* TX Descriptor Base Address Low - RW */
|
686 |
|
|
#define E1000_TDBAH 0x03804 /* TX Descriptor Base Address High - RW */
|
687 |
|
|
#define E1000_TDLEN 0x03808 /* TX Descriptor Length - RW */
|
688 |
|
|
#define E1000_TDH 0x03810 /* TX Descriptor Head - RW */
|
689 |
|
|
#define E1000_TDT 0x03818 /* TX Descripotr Tail - RW */
|
690 |
|
|
#define E1000_TIDV 0x03820 /* TX Interrupt Delay Value - RW */
|
691 |
|
|
#define E1000_TXDCTL 0x03828 /* TX Descriptor Control - RW */
|
692 |
|
|
#define E1000_TADV 0x0382C /* TX Interrupt Absolute Delay Val - RW */
|
693 |
|
|
#define E1000_TSPMT 0x03830 /* TCP Segmentation PAD & Min Threshold - RW */
|
694 |
|
|
#define E1000_CRCERRS 0x04000 /* CRC Error Count - R/clr */
|
695 |
|
|
#define E1000_ALGNERRC 0x04004 /* Alignment Error Count - R/clr */
|
696 |
|
|
#define E1000_SYMERRS 0x04008 /* Symbol Error Count - R/clr */
|
697 |
|
|
#define E1000_RXERRC 0x0400C /* Receive Error Count - R/clr */
|
698 |
|
|
#define E1000_MPC 0x04010 /* Missed Packet Count - R/clr */
|
699 |
|
|
#define E1000_SCC 0x04014 /* Single Collision Count - R/clr */
|
700 |
|
|
#define E1000_ECOL 0x04018 /* Excessive Collision Count - R/clr */
|
701 |
|
|
#define E1000_MCC 0x0401C /* Multiple Collision Count - R/clr */
|
702 |
|
|
#define E1000_LATECOL 0x04020 /* Late Collision Count - R/clr */
|
703 |
|
|
#define E1000_COLC 0x04028 /* Collision Count - R/clr */
|
704 |
|
|
#define E1000_DC 0x04030 /* Defer Count - R/clr */
|
705 |
|
|
#define E1000_TNCRS 0x04034 /* TX-No CRS - R/clr */
|
706 |
|
|
#define E1000_SEC 0x04038 /* Sequence Error Count - R/clr */
|
707 |
|
|
#define E1000_CEXTERR 0x0403C /* Carrier Extension Error Count - R/clr */
|
708 |
|
|
#define E1000_RLEC 0x04040 /* Receive Length Error Count - R/clr */
|
709 |
|
|
#define E1000_XONRXC 0x04048 /* XON RX Count - R/clr */
|
710 |
|
|
#define E1000_XONTXC 0x0404C /* XON TX Count - R/clr */
|
711 |
|
|
#define E1000_XOFFRXC 0x04050 /* XOFF RX Count - R/clr */
|
712 |
|
|
#define E1000_XOFFTXC 0x04054 /* XOFF TX Count - R/clr */
|
713 |
|
|
#define E1000_FCRUC 0x04058 /* Flow Control RX Unsupported Count- R/clr */
|
714 |
|
|
#define E1000_PRC64 0x0405C /* Packets RX (64 bytes) - R/clr */
|
715 |
|
|
#define E1000_PRC127 0x04060 /* Packets RX (65-127 bytes) - R/clr */
|
716 |
|
|
#define E1000_PRC255 0x04064 /* Packets RX (128-255 bytes) - R/clr */
|
717 |
|
|
#define E1000_PRC511 0x04068 /* Packets RX (255-511 bytes) - R/clr */
|
718 |
|
|
#define E1000_PRC1023 0x0406C /* Packets RX (512-1023 bytes) - R/clr */
|
719 |
|
|
#define E1000_PRC1522 0x04070 /* Packets RX (1024-1522 bytes) - R/clr */
|
720 |
|
|
#define E1000_GPRC 0x04074 /* Good Packets RX Count - R/clr */
|
721 |
|
|
#define E1000_BPRC 0x04078 /* Broadcast Packets RX Count - R/clr */
|
722 |
|
|
#define E1000_MPRC 0x0407C /* Multicast Packets RX Count - R/clr */
|
723 |
|
|
#define E1000_GPTC 0x04080 /* Good Packets TX Count - R/clr */
|
724 |
|
|
#define E1000_GORCL 0x04088 /* Good Octets RX Count Low - R/clr */
|
725 |
|
|
#define E1000_GORCH 0x0408C /* Good Octets RX Count High - R/clr */
|
726 |
|
|
#define E1000_GOTCL 0x04090 /* Good Octets TX Count Low - R/clr */
|
727 |
|
|
#define E1000_GOTCH 0x04094 /* Good Octets TX Count High - R/clr */
|
728 |
|
|
#define E1000_RNBC 0x040A0 /* RX No Buffers Count - R/clr */
|
729 |
|
|
#define E1000_RUC 0x040A4 /* RX Undersize Count - R/clr */
|
730 |
|
|
#define E1000_RFC 0x040A8 /* RX Fragment Count - R/clr */
|
731 |
|
|
#define E1000_ROC 0x040AC /* RX Oversize Count - R/clr */
|
732 |
|
|
#define E1000_RJC 0x040B0 /* RX Jabber Count - R/clr */
|
733 |
|
|
#define E1000_MGTPRC 0x040B4 /* Management Packets RX Count - R/clr */
|
734 |
|
|
#define E1000_MGTPDC 0x040B8 /* Management Packets Dropped Count - R/clr */
|
735 |
|
|
#define E1000_MGTPTC 0x040BC /* Management Packets TX Count - R/clr */
|
736 |
|
|
#define E1000_TORL 0x040C0 /* Total Octets RX Low - R/clr */
|
737 |
|
|
#define E1000_TORH 0x040C4 /* Total Octets RX High - R/clr */
|
738 |
|
|
#define E1000_TOTL 0x040C8 /* Total Octets TX Low - R/clr */
|
739 |
|
|
#define E1000_TOTH 0x040CC /* Total Octets TX High - R/clr */
|
740 |
|
|
#define E1000_TPR 0x040D0 /* Total Packets RX - R/clr */
|
741 |
|
|
#define E1000_TPT 0x040D4 /* Total Packets TX - R/clr */
|
742 |
|
|
#define E1000_PTC64 0x040D8 /* Packets TX (64 bytes) - R/clr */
|
743 |
|
|
#define E1000_PTC127 0x040DC /* Packets TX (65-127 bytes) - R/clr */
|
744 |
|
|
#define E1000_PTC255 0x040E0 /* Packets TX (128-255 bytes) - R/clr */
|
745 |
|
|
#define E1000_PTC511 0x040E4 /* Packets TX (256-511 bytes) - R/clr */
|
746 |
|
|
#define E1000_PTC1023 0x040E8 /* Packets TX (512-1023 bytes) - R/clr */
|
747 |
|
|
#define E1000_PTC1522 0x040EC /* Packets TX (1024-1522 Bytes) - R/clr */
|
748 |
|
|
#define E1000_MPTC 0x040F0 /* Multicast Packets TX Count - R/clr */
|
749 |
|
|
#define E1000_BPTC 0x040F4 /* Broadcast Packets TX Count - R/clr */
|
750 |
|
|
#define E1000_TSCTC 0x040F8 /* TCP Segmentation Context TX - R/clr */
|
751 |
|
|
#define E1000_TSCTFC 0x040FC /* TCP Segmentation Context TX Fail - R/clr */
|
752 |
|
|
#define E1000_RXCSUM 0x05000 /* RX Checksum Control - RW */
|
753 |
|
|
#define E1000_MTA 0x05200 /* Multicast Table Array - RW Array */
|
754 |
|
|
#define E1000_RA 0x05400 /* Receive Address - RW Array */
|
755 |
|
|
#define E1000_VFTA 0x05600 /* VLAN Filter Table Array - RW Array */
|
756 |
|
|
#define E1000_WUC 0x05800 /* Wakeup Control - RW */
|
757 |
|
|
#define E1000_WUFC 0x05808 /* Wakeup Filter Control - RW */
|
758 |
|
|
#define E1000_WUS 0x05810 /* Wakeup Status - RO */
|
759 |
|
|
#define E1000_MANC 0x05820 /* Management Control - RW */
|
760 |
|
|
#define E1000_IPAV 0x05838 /* IP Address Valid - RW */
|
761 |
|
|
#define E1000_IP4AT 0x05840 /* IPv4 Address Table - RW Array */
|
762 |
|
|
#define E1000_IP6AT 0x05880 /* IPv6 Address Table - RW Array */
|
763 |
|
|
#define E1000_WUPL 0x05900 /* Wakeup Packet Length - RW */
|
764 |
|
|
#define E1000_WUPM 0x05A00 /* Wakeup Packet Memory - RO A */
|
765 |
|
|
#define E1000_FFLT 0x05F00 /* Flexible Filter Length Table - RW Array */
|
766 |
|
|
#define E1000_FFMT 0x09000 /* Flexible Filter Mask Table - RW Array */
|
767 |
|
|
#define E1000_FFVT 0x09800 /* Flexible Filter Value Table - RW Array */
|
768 |
|
|
|
769 |
|
|
/* Register Set (82542)
|
770 |
|
|
*
|
771 |
|
|
* Some of the 82542 registers are located at different offsets than they are
|
772 |
|
|
* in more current versions of the 8254x. Despite the difference in location,
|
773 |
|
|
* the registers function in the same manner.
|
774 |
|
|
*/
|
775 |
|
|
#define E1000_82542_CTRL E1000_CTRL
|
776 |
|
|
#define E1000_82542_CTRL_DUP E1000_CTRL_DUP
|
777 |
|
|
#define E1000_82542_STATUS E1000_STATUS
|
778 |
|
|
#define E1000_82542_EECD E1000_EECD
|
779 |
|
|
#define E1000_82542_EERD E1000_EERD
|
780 |
|
|
#define E1000_82542_CTRL_EXT E1000_CTRL_EXT
|
781 |
|
|
#define E1000_82542_FLA E1000_FLA
|
782 |
|
|
#define E1000_82542_MDIC E1000_MDIC
|
783 |
|
|
#define E1000_82542_FCAL E1000_FCAL
|
784 |
|
|
#define E1000_82542_FCAH E1000_FCAH
|
785 |
|
|
#define E1000_82542_FCT E1000_FCT
|
786 |
|
|
#define E1000_82542_VET E1000_VET
|
787 |
|
|
#define E1000_82542_RA 0x00040
|
788 |
|
|
#define E1000_82542_ICR E1000_ICR
|
789 |
|
|
#define E1000_82542_ITR E1000_ITR
|
790 |
|
|
#define E1000_82542_ICS E1000_ICS
|
791 |
|
|
#define E1000_82542_IMS E1000_IMS
|
792 |
|
|
#define E1000_82542_IMC E1000_IMC
|
793 |
|
|
#define E1000_82542_RCTL E1000_RCTL
|
794 |
|
|
#define E1000_82542_RDTR 0x00108
|
795 |
|
|
#define E1000_82542_RDBAL 0x00110
|
796 |
|
|
#define E1000_82542_RDBAH 0x00114
|
797 |
|
|
#define E1000_82542_RDLEN 0x00118
|
798 |
|
|
#define E1000_82542_RDH 0x00120
|
799 |
|
|
#define E1000_82542_RDT 0x00128
|
800 |
|
|
#define E1000_82542_FCRTH 0x00160
|
801 |
|
|
#define E1000_82542_FCRTL 0x00168
|
802 |
|
|
#define E1000_82542_FCTTV E1000_FCTTV
|
803 |
|
|
#define E1000_82542_TXCW E1000_TXCW
|
804 |
|
|
#define E1000_82542_RXCW E1000_RXCW
|
805 |
|
|
#define E1000_82542_MTA 0x00200
|
806 |
|
|
#define E1000_82542_TCTL E1000_TCTL
|
807 |
|
|
#define E1000_82542_TIPG E1000_TIPG
|
808 |
|
|
#define E1000_82542_TDBAL 0x00420
|
809 |
|
|
#define E1000_82542_TDBAH 0x00424
|
810 |
|
|
#define E1000_82542_TDLEN 0x00428
|
811 |
|
|
#define E1000_82542_TDH 0x00430
|
812 |
|
|
#define E1000_82542_TDT 0x00438
|
813 |
|
|
#define E1000_82542_TIDV 0x00440
|
814 |
|
|
#define E1000_82542_TBT E1000_TBT
|
815 |
|
|
#define E1000_82542_AIT E1000_AIT
|
816 |
|
|
#define E1000_82542_VFTA 0x00600
|
817 |
|
|
#define E1000_82542_LEDCTL E1000_LEDCTL
|
818 |
|
|
#define E1000_82542_PBA E1000_PBA
|
819 |
|
|
#define E1000_82542_RXDCTL E1000_RXDCTL
|
820 |
|
|
#define E1000_82542_RADV E1000_RADV
|
821 |
|
|
#define E1000_82542_RSRPD E1000_RSRPD
|
822 |
|
|
#define E1000_82542_TXDMAC E1000_TXDMAC
|
823 |
|
|
#define E1000_82542_TDFHS E1000_TDFHS
|
824 |
|
|
#define E1000_82542_TDFTS E1000_TDFTS
|
825 |
|
|
#define E1000_82542_TDFPC E1000_TDFPC
|
826 |
|
|
#define E1000_82542_TXDCTL E1000_TXDCTL
|
827 |
|
|
#define E1000_82542_TADV E1000_TADV
|
828 |
|
|
#define E1000_82542_TSPMT E1000_TSPMT
|
829 |
|
|
#define E1000_82542_CRCERRS E1000_CRCERRS
|
830 |
|
|
#define E1000_82542_ALGNERRC E1000_ALGNERRC
|
831 |
|
|
#define E1000_82542_SYMERRS E1000_SYMERRS
|
832 |
|
|
#define E1000_82542_RXERRC E1000_RXERRC
|
833 |
|
|
#define E1000_82542_MPC E1000_MPC
|
834 |
|
|
#define E1000_82542_SCC E1000_SCC
|
835 |
|
|
#define E1000_82542_ECOL E1000_ECOL
|
836 |
|
|
#define E1000_82542_MCC E1000_MCC
|
837 |
|
|
#define E1000_82542_LATECOL E1000_LATECOL
|
838 |
|
|
#define E1000_82542_COLC E1000_COLC
|
839 |
|
|
#define E1000_82542_DC E1000_DC
|
840 |
|
|
#define E1000_82542_TNCRS E1000_TNCRS
|
841 |
|
|
#define E1000_82542_SEC E1000_SEC
|
842 |
|
|
#define E1000_82542_CEXTERR E1000_CEXTERR
|
843 |
|
|
#define E1000_82542_RLEC E1000_RLEC
|
844 |
|
|
#define E1000_82542_XONRXC E1000_XONRXC
|
845 |
|
|
#define E1000_82542_XONTXC E1000_XONTXC
|
846 |
|
|
#define E1000_82542_XOFFRXC E1000_XOFFRXC
|
847 |
|
|
#define E1000_82542_XOFFTXC E1000_XOFFTXC
|
848 |
|
|
#define E1000_82542_FCRUC E1000_FCRUC
|
849 |
|
|
#define E1000_82542_PRC64 E1000_PRC64
|
850 |
|
|
#define E1000_82542_PRC127 E1000_PRC127
|
851 |
|
|
#define E1000_82542_PRC255 E1000_PRC255
|
852 |
|
|
#define E1000_82542_PRC511 E1000_PRC511
|
853 |
|
|
#define E1000_82542_PRC1023 E1000_PRC1023
|
854 |
|
|
#define E1000_82542_PRC1522 E1000_PRC1522
|
855 |
|
|
#define E1000_82542_GPRC E1000_GPRC
|
856 |
|
|
#define E1000_82542_BPRC E1000_BPRC
|
857 |
|
|
#define E1000_82542_MPRC E1000_MPRC
|
858 |
|
|
#define E1000_82542_GPTC E1000_GPTC
|
859 |
|
|
#define E1000_82542_GORCL E1000_GORCL
|
860 |
|
|
#define E1000_82542_GORCH E1000_GORCH
|
861 |
|
|
#define E1000_82542_GOTCL E1000_GOTCL
|
862 |
|
|
#define E1000_82542_GOTCH E1000_GOTCH
|
863 |
|
|
#define E1000_82542_RNBC E1000_RNBC
|
864 |
|
|
#define E1000_82542_RUC E1000_RUC
|
865 |
|
|
#define E1000_82542_RFC E1000_RFC
|
866 |
|
|
#define E1000_82542_ROC E1000_ROC
|
867 |
|
|
#define E1000_82542_RJC E1000_RJC
|
868 |
|
|
#define E1000_82542_MGTPRC E1000_MGTPRC
|
869 |
|
|
#define E1000_82542_MGTPDC E1000_MGTPDC
|
870 |
|
|
#define E1000_82542_MGTPTC E1000_MGTPTC
|
871 |
|
|
#define E1000_82542_TORL E1000_TORL
|
872 |
|
|
#define E1000_82542_TORH E1000_TORH
|
873 |
|
|
#define E1000_82542_TOTL E1000_TOTL
|
874 |
|
|
#define E1000_82542_TOTH E1000_TOTH
|
875 |
|
|
#define E1000_82542_TPR E1000_TPR
|
876 |
|
|
#define E1000_82542_TPT E1000_TPT
|
877 |
|
|
#define E1000_82542_PTC64 E1000_PTC64
|
878 |
|
|
#define E1000_82542_PTC127 E1000_PTC127
|
879 |
|
|
#define E1000_82542_PTC255 E1000_PTC255
|
880 |
|
|
#define E1000_82542_PTC511 E1000_PTC511
|
881 |
|
|
#define E1000_82542_PTC1023 E1000_PTC1023
|
882 |
|
|
#define E1000_82542_PTC1522 E1000_PTC1522
|
883 |
|
|
#define E1000_82542_MPTC E1000_MPTC
|
884 |
|
|
#define E1000_82542_BPTC E1000_BPTC
|
885 |
|
|
#define E1000_82542_TSCTC E1000_TSCTC
|
886 |
|
|
#define E1000_82542_TSCTFC E1000_TSCTFC
|
887 |
|
|
#define E1000_82542_RXCSUM E1000_RXCSUM
|
888 |
|
|
#define E1000_82542_WUC E1000_WUC
|
889 |
|
|
#define E1000_82542_WUFC E1000_WUFC
|
890 |
|
|
#define E1000_82542_WUS E1000_WUS
|
891 |
|
|
#define E1000_82542_MANC E1000_MANC
|
892 |
|
|
#define E1000_82542_IPAV E1000_IPAV
|
893 |
|
|
#define E1000_82542_IP4AT E1000_IP4AT
|
894 |
|
|
#define E1000_82542_IP6AT E1000_IP6AT
|
895 |
|
|
#define E1000_82542_WUPL E1000_WUPL
|
896 |
|
|
#define E1000_82542_WUPM E1000_WUPM
|
897 |
|
|
#define E1000_82542_FFLT E1000_FFLT
|
898 |
|
|
#define E1000_82542_TDFH 0x08010
|
899 |
|
|
#define E1000_82542_TDFT 0x08018
|
900 |
|
|
#define E1000_82542_FFMT E1000_FFMT
|
901 |
|
|
#define E1000_82542_FFVT E1000_FFVT
|
902 |
|
|
|
903 |
|
|
/* Statistics counters collected by the MAC */
|
904 |
|
|
struct e1000_hw_stats {
|
905 |
|
|
uint64_t crcerrs;
|
906 |
|
|
uint64_t algnerrc;
|
907 |
|
|
uint64_t symerrs;
|
908 |
|
|
uint64_t rxerrc;
|
909 |
|
|
uint64_t mpc;
|
910 |
|
|
uint64_t scc;
|
911 |
|
|
uint64_t ecol;
|
912 |
|
|
uint64_t mcc;
|
913 |
|
|
uint64_t latecol;
|
914 |
|
|
uint64_t colc;
|
915 |
|
|
uint64_t dc;
|
916 |
|
|
uint64_t tncrs;
|
917 |
|
|
uint64_t sec;
|
918 |
|
|
uint64_t cexterr;
|
919 |
|
|
uint64_t rlec;
|
920 |
|
|
uint64_t xonrxc;
|
921 |
|
|
uint64_t xontxc;
|
922 |
|
|
uint64_t xoffrxc;
|
923 |
|
|
uint64_t xofftxc;
|
924 |
|
|
uint64_t fcruc;
|
925 |
|
|
uint64_t prc64;
|
926 |
|
|
uint64_t prc127;
|
927 |
|
|
uint64_t prc255;
|
928 |
|
|
uint64_t prc511;
|
929 |
|
|
uint64_t prc1023;
|
930 |
|
|
uint64_t prc1522;
|
931 |
|
|
uint64_t gprc;
|
932 |
|
|
uint64_t bprc;
|
933 |
|
|
uint64_t mprc;
|
934 |
|
|
uint64_t gptc;
|
935 |
|
|
uint64_t gorcl;
|
936 |
|
|
uint64_t gorch;
|
937 |
|
|
uint64_t gotcl;
|
938 |
|
|
uint64_t gotch;
|
939 |
|
|
uint64_t rnbc;
|
940 |
|
|
uint64_t ruc;
|
941 |
|
|
uint64_t rfc;
|
942 |
|
|
uint64_t roc;
|
943 |
|
|
uint64_t rjc;
|
944 |
|
|
uint64_t mgprc;
|
945 |
|
|
uint64_t mgpdc;
|
946 |
|
|
uint64_t mgptc;
|
947 |
|
|
uint64_t torl;
|
948 |
|
|
uint64_t torh;
|
949 |
|
|
uint64_t totl;
|
950 |
|
|
uint64_t toth;
|
951 |
|
|
uint64_t tpr;
|
952 |
|
|
uint64_t tpt;
|
953 |
|
|
uint64_t ptc64;
|
954 |
|
|
uint64_t ptc127;
|
955 |
|
|
uint64_t ptc255;
|
956 |
|
|
uint64_t ptc511;
|
957 |
|
|
uint64_t ptc1023;
|
958 |
|
|
uint64_t ptc1522;
|
959 |
|
|
uint64_t mptc;
|
960 |
|
|
uint64_t bptc;
|
961 |
|
|
uint64_t tsctc;
|
962 |
|
|
uint64_t tsctfc;
|
963 |
|
|
};
|
964 |
|
|
|
965 |
|
|
/* Structure containing variables used by the shared code (e1000_hw.c) */
|
966 |
|
|
struct e1000_hw {
|
967 |
|
|
uint8_t *hw_addr;
|
968 |
|
|
e1000_mac_type mac_type;
|
969 |
|
|
e1000_phy_type phy_type;
|
970 |
|
|
uint32_t phy_init_script;
|
971 |
|
|
e1000_media_type media_type;
|
972 |
|
|
void *back;
|
973 |
|
|
e1000_fc_type fc;
|
974 |
|
|
e1000_bus_speed bus_speed;
|
975 |
|
|
e1000_bus_width bus_width;
|
976 |
|
|
e1000_bus_type bus_type;
|
977 |
|
|
struct e1000_eeprom_info eeprom;
|
978 |
|
|
e1000_ms_type master_slave;
|
979 |
|
|
e1000_ms_type original_master_slave;
|
980 |
|
|
e1000_ffe_config ffe_config_state;
|
981 |
|
|
unsigned long io_base;
|
982 |
|
|
uint32_t phy_id;
|
983 |
|
|
uint32_t phy_revision;
|
984 |
|
|
uint32_t phy_addr;
|
985 |
|
|
uint32_t original_fc;
|
986 |
|
|
uint32_t txcw;
|
987 |
|
|
uint32_t autoneg_failed;
|
988 |
|
|
uint32_t max_frame_size;
|
989 |
|
|
uint32_t min_frame_size;
|
990 |
|
|
uint32_t mc_filter_type;
|
991 |
|
|
uint32_t num_mc_addrs;
|
992 |
|
|
uint32_t collision_delta;
|
993 |
|
|
uint32_t tx_packet_delta;
|
994 |
|
|
uint32_t ledctl_default;
|
995 |
|
|
uint32_t ledctl_mode1;
|
996 |
|
|
uint32_t ledctl_mode2;
|
997 |
|
|
uint16_t phy_spd_default;
|
998 |
|
|
uint16_t autoneg_advertised;
|
999 |
|
|
uint16_t pci_cmd_word;
|
1000 |
|
|
uint16_t fc_high_water;
|
1001 |
|
|
uint16_t fc_low_water;
|
1002 |
|
|
uint16_t fc_pause_time;
|
1003 |
|
|
uint16_t current_ifs_val;
|
1004 |
|
|
uint16_t ifs_min_val;
|
1005 |
|
|
uint16_t ifs_max_val;
|
1006 |
|
|
uint16_t ifs_step_size;
|
1007 |
|
|
uint16_t ifs_ratio;
|
1008 |
|
|
uint16_t device_id;
|
1009 |
|
|
uint16_t vendor_id;
|
1010 |
|
|
uint16_t subsystem_id;
|
1011 |
|
|
uint16_t subsystem_vendor_id;
|
1012 |
|
|
uint8_t revision_id;
|
1013 |
|
|
uint8_t autoneg;
|
1014 |
|
|
uint8_t mdix;
|
1015 |
|
|
uint8_t forced_speed_duplex;
|
1016 |
|
|
uint8_t wait_autoneg_complete;
|
1017 |
|
|
uint8_t dma_fairness;
|
1018 |
|
|
uint8_t mac_addr[NODE_ADDRESS_SIZE];
|
1019 |
|
|
uint8_t perm_mac_addr[NODE_ADDRESS_SIZE];
|
1020 |
|
|
boolean_t disable_polarity_correction;
|
1021 |
|
|
boolean_t speed_downgraded;
|
1022 |
|
|
e1000_dsp_config dsp_config_state;
|
1023 |
|
|
boolean_t get_link_status;
|
1024 |
|
|
boolean_t serdes_link_down;
|
1025 |
|
|
boolean_t tbi_compatibility_en;
|
1026 |
|
|
boolean_t tbi_compatibility_on;
|
1027 |
|
|
boolean_t phy_reset_disable;
|
1028 |
|
|
boolean_t fc_send_xon;
|
1029 |
|
|
boolean_t fc_strict_ieee;
|
1030 |
|
|
boolean_t report_tx_early;
|
1031 |
|
|
boolean_t adaptive_ifs;
|
1032 |
|
|
boolean_t ifs_params_forced;
|
1033 |
|
|
boolean_t in_ifs_mode;
|
1034 |
|
|
};
|
1035 |
|
|
|
1036 |
|
|
|
1037 |
|
|
#define E1000_EEPROM_SWDPIN0 0x0001 /* SWDPIN 0 EEPROM Value */
|
1038 |
|
|
#define E1000_EEPROM_LED_LOGIC 0x0020 /* Led Logic Word */
|
1039 |
|
|
|
1040 |
|
|
/* Register Bit Masks */
|
1041 |
|
|
/* Device Control */
|
1042 |
|
|
#define E1000_CTRL_FD 0x00000001 /* Full duplex.0=half; 1=full */
|
1043 |
|
|
#define E1000_CTRL_BEM 0x00000002 /* Endian Mode.0=little,1=big */
|
1044 |
|
|
#define E1000_CTRL_PRIOR 0x00000004 /* Priority on PCI. 0=rx,1=fair */
|
1045 |
|
|
#define E1000_CTRL_LRST 0x00000008 /* Link reset. 0=normal,1=reset */
|
1046 |
|
|
#define E1000_CTRL_TME 0x00000010 /* Test mode. 0=normal,1=test */
|
1047 |
|
|
#define E1000_CTRL_SLE 0x00000020 /* Serial Link on 0=dis,1=en */
|
1048 |
|
|
#define E1000_CTRL_ASDE 0x00000020 /* Auto-speed detect enable */
|
1049 |
|
|
#define E1000_CTRL_SLU 0x00000040 /* Set link up (Force Link) */
|
1050 |
|
|
#define E1000_CTRL_ILOS 0x00000080 /* Invert Loss-Of Signal */
|
1051 |
|
|
#define E1000_CTRL_SPD_SEL 0x00000300 /* Speed Select Mask */
|
1052 |
|
|
#define E1000_CTRL_SPD_10 0x00000000 /* Force 10Mb */
|
1053 |
|
|
#define E1000_CTRL_SPD_100 0x00000100 /* Force 100Mb */
|
1054 |
|
|
#define E1000_CTRL_SPD_1000 0x00000200 /* Force 1Gb */
|
1055 |
|
|
#define E1000_CTRL_BEM32 0x00000400 /* Big Endian 32 mode */
|
1056 |
|
|
#define E1000_CTRL_FRCSPD 0x00000800 /* Force Speed */
|
1057 |
|
|
#define E1000_CTRL_FRCDPX 0x00001000 /* Force Duplex */
|
1058 |
|
|
#define E1000_CTRL_SWDPIN0 0x00040000 /* SWDPIN 0 value */
|
1059 |
|
|
#define E1000_CTRL_SWDPIN1 0x00080000 /* SWDPIN 1 value */
|
1060 |
|
|
#define E1000_CTRL_SWDPIN2 0x00100000 /* SWDPIN 2 value */
|
1061 |
|
|
#define E1000_CTRL_SWDPIN3 0x00200000 /* SWDPIN 3 value */
|
1062 |
|
|
#define E1000_CTRL_SWDPIO0 0x00400000 /* SWDPIN 0 Input or output */
|
1063 |
|
|
#define E1000_CTRL_SWDPIO1 0x00800000 /* SWDPIN 1 input or output */
|
1064 |
|
|
#define E1000_CTRL_SWDPIO2 0x01000000 /* SWDPIN 2 input or output */
|
1065 |
|
|
#define E1000_CTRL_SWDPIO3 0x02000000 /* SWDPIN 3 input or output */
|
1066 |
|
|
#define E1000_CTRL_RST 0x04000000 /* Global reset */
|
1067 |
|
|
#define E1000_CTRL_RFCE 0x08000000 /* Receive Flow Control enable */
|
1068 |
|
|
#define E1000_CTRL_TFCE 0x10000000 /* Transmit flow control enable */
|
1069 |
|
|
#define E1000_CTRL_RTE 0x20000000 /* Routing tag enable */
|
1070 |
|
|
#define E1000_CTRL_VME 0x40000000 /* IEEE VLAN mode enable */
|
1071 |
|
|
#define E1000_CTRL_PHY_RST 0x80000000 /* PHY Reset */
|
1072 |
|
|
|
1073 |
|
|
/* Device Status */
|
1074 |
|
|
#define E1000_STATUS_FD 0x00000001 /* Full duplex.0=half,1=full */
|
1075 |
|
|
#define E1000_STATUS_LU 0x00000002 /* Link up.0=no,1=link */
|
1076 |
|
|
#define E1000_STATUS_FUNC_MASK 0x0000000C /* PCI Function Mask */
|
1077 |
|
|
#define E1000_STATUS_FUNC_0 0x00000000 /* Function 0 */
|
1078 |
|
|
#define E1000_STATUS_FUNC_1 0x00000004 /* Function 1 */
|
1079 |
|
|
#define E1000_STATUS_TXOFF 0x00000010 /* transmission paused */
|
1080 |
|
|
#define E1000_STATUS_TBIMODE 0x00000020 /* TBI mode */
|
1081 |
|
|
#define E1000_STATUS_SPEED_MASK 0x000000C0
|
1082 |
|
|
#define E1000_STATUS_SPEED_10 0x00000000 /* Speed 10Mb/s */
|
1083 |
|
|
#define E1000_STATUS_SPEED_100 0x00000040 /* Speed 100Mb/s */
|
1084 |
|
|
#define E1000_STATUS_SPEED_1000 0x00000080 /* Speed 1000Mb/s */
|
1085 |
|
|
#define E1000_STATUS_ASDV 0x00000300 /* Auto speed detect value */
|
1086 |
|
|
#define E1000_STATUS_MTXCKOK 0x00000400 /* MTX clock running OK */
|
1087 |
|
|
#define E1000_STATUS_PCI66 0x00000800 /* In 66Mhz slot */
|
1088 |
|
|
#define E1000_STATUS_BUS64 0x00001000 /* In 64 bit slot */
|
1089 |
|
|
#define E1000_STATUS_PCIX_MODE 0x00002000 /* PCI-X mode */
|
1090 |
|
|
#define E1000_STATUS_PCIX_SPEED 0x0000C000 /* PCI-X bus speed */
|
1091 |
|
|
|
1092 |
|
|
/* Constants used to intrepret the masked PCI-X bus speed. */
|
1093 |
|
|
#define E1000_STATUS_PCIX_SPEED_66 0x00000000 /* PCI-X bus speed 50-66 MHz */
|
1094 |
|
|
#define E1000_STATUS_PCIX_SPEED_100 0x00004000 /* PCI-X bus speed 66-100 MHz */
|
1095 |
|
|
#define E1000_STATUS_PCIX_SPEED_133 0x00008000 /* PCI-X bus speed 100-133 MHz */
|
1096 |
|
|
|
1097 |
|
|
/* EEPROM/Flash Control */
|
1098 |
|
|
#define E1000_EECD_SK 0x00000001 /* EEPROM Clock */
|
1099 |
|
|
#define E1000_EECD_CS 0x00000002 /* EEPROM Chip Select */
|
1100 |
|
|
#define E1000_EECD_DI 0x00000004 /* EEPROM Data In */
|
1101 |
|
|
#define E1000_EECD_DO 0x00000008 /* EEPROM Data Out */
|
1102 |
|
|
#define E1000_EECD_FWE_MASK 0x00000030
|
1103 |
|
|
#define E1000_EECD_FWE_DIS 0x00000010 /* Disable FLASH writes */
|
1104 |
|
|
#define E1000_EECD_FWE_EN 0x00000020 /* Enable FLASH writes */
|
1105 |
|
|
#define E1000_EECD_FWE_SHIFT 4
|
1106 |
|
|
#define E1000_EECD_REQ 0x00000040 /* EEPROM Access Request */
|
1107 |
|
|
#define E1000_EECD_GNT 0x00000080 /* EEPROM Access Grant */
|
1108 |
|
|
#define E1000_EECD_PRES 0x00000100 /* EEPROM Present */
|
1109 |
|
|
#define E1000_EECD_SIZE 0x00000200 /* EEPROM Size (0=64 word 1=256 word) */
|
1110 |
|
|
#define E1000_EECD_ADDR_BITS 0x00000400 /* EEPROM Addressing bits based on type
|
1111 |
|
|
* (0-small, 1-large) */
|
1112 |
|
|
#define E1000_EECD_TYPE 0x00002000 /* EEPROM Type (1-SPI, 0-Microwire) */
|
1113 |
|
|
#ifndef E1000_EEPROM_GRANT_ATTEMPTS
|
1114 |
|
|
#define E1000_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM # attempts to gain grant */
|
1115 |
|
|
#endif
|
1116 |
|
|
|
1117 |
|
|
/* EEPROM Read */
|
1118 |
|
|
#define E1000_EERD_START 0x00000001 /* Start Read */
|
1119 |
|
|
#define E1000_EERD_DONE 0x00000010 /* Read Done */
|
1120 |
|
|
#define E1000_EERD_ADDR_SHIFT 8
|
1121 |
|
|
#define E1000_EERD_ADDR_MASK 0x0000FF00 /* Read Address */
|
1122 |
|
|
#define E1000_EERD_DATA_SHIFT 16
|
1123 |
|
|
#define E1000_EERD_DATA_MASK 0xFFFF0000 /* Read Data */
|
1124 |
|
|
|
1125 |
|
|
/* SPI EEPROM Status Register */
|
1126 |
|
|
#define EEPROM_STATUS_RDY_SPI 0x01
|
1127 |
|
|
#define EEPROM_STATUS_WEN_SPI 0x02
|
1128 |
|
|
#define EEPROM_STATUS_BP0_SPI 0x04
|
1129 |
|
|
#define EEPROM_STATUS_BP1_SPI 0x08
|
1130 |
|
|
#define EEPROM_STATUS_WPEN_SPI 0x80
|
1131 |
|
|
|
1132 |
|
|
/* Extended Device Control */
|
1133 |
|
|
#define E1000_CTRL_EXT_GPI0_EN 0x00000001 /* Maps SDP4 to GPI0 */
|
1134 |
|
|
#define E1000_CTRL_EXT_GPI1_EN 0x00000002 /* Maps SDP5 to GPI1 */
|
1135 |
|
|
#define E1000_CTRL_EXT_PHYINT_EN E1000_CTRL_EXT_GPI1_EN
|
1136 |
|
|
#define E1000_CTRL_EXT_GPI2_EN 0x00000004 /* Maps SDP6 to GPI2 */
|
1137 |
|
|
#define E1000_CTRL_EXT_GPI3_EN 0x00000008 /* Maps SDP7 to GPI3 */
|
1138 |
|
|
#define E1000_CTRL_EXT_SDP4_DATA 0x00000010 /* Value of SW Defineable Pin 4 */
|
1139 |
|
|
#define E1000_CTRL_EXT_SDP5_DATA 0x00000020 /* Value of SW Defineable Pin 5 */
|
1140 |
|
|
#define E1000_CTRL_EXT_PHY_INT E1000_CTRL_EXT_SDP5_DATA
|
1141 |
|
|
#define E1000_CTRL_EXT_SDP6_DATA 0x00000040 /* Value of SW Defineable Pin 6 */
|
1142 |
|
|
#define E1000_CTRL_EXT_SDP7_DATA 0x00000080 /* Value of SW Defineable Pin 7 */
|
1143 |
|
|
#define E1000_CTRL_EXT_SDP4_DIR 0x00000100 /* Direction of SDP4 0=in 1=out */
|
1144 |
|
|
#define E1000_CTRL_EXT_SDP5_DIR 0x00000200 /* Direction of SDP5 0=in 1=out */
|
1145 |
|
|
#define E1000_CTRL_EXT_SDP6_DIR 0x00000400 /* Direction of SDP6 0=in 1=out */
|
1146 |
|
|
#define E1000_CTRL_EXT_SDP7_DIR 0x00000800 /* Direction of SDP7 0=in 1=out */
|
1147 |
|
|
#define E1000_CTRL_EXT_ASDCHK 0x00001000 /* Initiate an ASD sequence */
|
1148 |
|
|
#define E1000_CTRL_EXT_EE_RST 0x00002000 /* Reinitialize from EEPROM */
|
1149 |
|
|
#define E1000_CTRL_EXT_IPS 0x00004000 /* Invert Power State */
|
1150 |
|
|
#define E1000_CTRL_EXT_SPD_BYPS 0x00008000 /* Speed Select Bypass */
|
1151 |
|
|
#define E1000_CTRL_EXT_LINK_MODE_MASK 0x00C00000
|
1152 |
|
|
#define E1000_CTRL_EXT_LINK_MODE_GMII 0x00000000
|
1153 |
|
|
#define E1000_CTRL_EXT_LINK_MODE_TBI 0x00C00000
|
1154 |
|
|
#define E1000_CTRL_EXT_WR_WMARK_MASK 0x03000000
|
1155 |
|
|
#define E1000_CTRL_EXT_WR_WMARK_256 0x00000000
|
1156 |
|
|
#define E1000_CTRL_EXT_WR_WMARK_320 0x01000000
|
1157 |
|
|
#define E1000_CTRL_EXT_WR_WMARK_384 0x02000000
|
1158 |
|
|
#define E1000_CTRL_EXT_WR_WMARK_448 0x03000000
|
1159 |
|
|
|
1160 |
|
|
/* MDI Control */
|
1161 |
|
|
#define E1000_MDIC_DATA_MASK 0x0000FFFF
|
1162 |
|
|
#define E1000_MDIC_REG_MASK 0x001F0000
|
1163 |
|
|
#define E1000_MDIC_REG_SHIFT 16
|
1164 |
|
|
#define E1000_MDIC_PHY_MASK 0x03E00000
|
1165 |
|
|
#define E1000_MDIC_PHY_SHIFT 21
|
1166 |
|
|
#define E1000_MDIC_OP_WRITE 0x04000000
|
1167 |
|
|
#define E1000_MDIC_OP_READ 0x08000000
|
1168 |
|
|
#define E1000_MDIC_READY 0x10000000
|
1169 |
|
|
#define E1000_MDIC_INT_EN 0x20000000
|
1170 |
|
|
#define E1000_MDIC_ERROR 0x40000000
|
1171 |
|
|
|
1172 |
|
|
/* LED Control */
|
1173 |
|
|
#define E1000_LEDCTL_LED0_MODE_MASK 0x0000000F
|
1174 |
|
|
#define E1000_LEDCTL_LED0_MODE_SHIFT 0
|
1175 |
|
|
#define E1000_LEDCTL_LED0_IVRT 0x00000040
|
1176 |
|
|
#define E1000_LEDCTL_LED0_BLINK 0x00000080
|
1177 |
|
|
#define E1000_LEDCTL_LED1_MODE_MASK 0x00000F00
|
1178 |
|
|
#define E1000_LEDCTL_LED1_MODE_SHIFT 8
|
1179 |
|
|
#define E1000_LEDCTL_LED1_IVRT 0x00004000
|
1180 |
|
|
#define E1000_LEDCTL_LED1_BLINK 0x00008000
|
1181 |
|
|
#define E1000_LEDCTL_LED2_MODE_MASK 0x000F0000
|
1182 |
|
|
#define E1000_LEDCTL_LED2_MODE_SHIFT 16
|
1183 |
|
|
#define E1000_LEDCTL_LED2_IVRT 0x00400000
|
1184 |
|
|
#define E1000_LEDCTL_LED2_BLINK 0x00800000
|
1185 |
|
|
#define E1000_LEDCTL_LED3_MODE_MASK 0x0F000000
|
1186 |
|
|
#define E1000_LEDCTL_LED3_MODE_SHIFT 24
|
1187 |
|
|
#define E1000_LEDCTL_LED3_IVRT 0x40000000
|
1188 |
|
|
#define E1000_LEDCTL_LED3_BLINK 0x80000000
|
1189 |
|
|
|
1190 |
|
|
#define E1000_LEDCTL_MODE_LINK_10_1000 0x0
|
1191 |
|
|
#define E1000_LEDCTL_MODE_LINK_100_1000 0x1
|
1192 |
|
|
#define E1000_LEDCTL_MODE_LINK_UP 0x2
|
1193 |
|
|
#define E1000_LEDCTL_MODE_ACTIVITY 0x3
|
1194 |
|
|
#define E1000_LEDCTL_MODE_LINK_ACTIVITY 0x4
|
1195 |
|
|
#define E1000_LEDCTL_MODE_LINK_10 0x5
|
1196 |
|
|
#define E1000_LEDCTL_MODE_LINK_100 0x6
|
1197 |
|
|
#define E1000_LEDCTL_MODE_LINK_1000 0x7
|
1198 |
|
|
#define E1000_LEDCTL_MODE_PCIX_MODE 0x8
|
1199 |
|
|
#define E1000_LEDCTL_MODE_FULL_DUPLEX 0x9
|
1200 |
|
|
#define E1000_LEDCTL_MODE_COLLISION 0xA
|
1201 |
|
|
#define E1000_LEDCTL_MODE_BUS_SPEED 0xB
|
1202 |
|
|
#define E1000_LEDCTL_MODE_BUS_SIZE 0xC
|
1203 |
|
|
#define E1000_LEDCTL_MODE_PAUSED 0xD
|
1204 |
|
|
#define E1000_LEDCTL_MODE_LED_ON 0xE
|
1205 |
|
|
#define E1000_LEDCTL_MODE_LED_OFF 0xF
|
1206 |
|
|
|
1207 |
|
|
/* Receive Address */
|
1208 |
|
|
#define E1000_RAH_AV 0x80000000 /* Receive descriptor valid */
|
1209 |
|
|
|
1210 |
|
|
/* Interrupt Cause Read */
|
1211 |
|
|
#define E1000_ICR_TXDW 0x00000001 /* Transmit desc written back */
|
1212 |
|
|
#define E1000_ICR_TXQE 0x00000002 /* Transmit Queue empty */
|
1213 |
|
|
#define E1000_ICR_LSC 0x00000004 /* Link Status Change */
|
1214 |
|
|
#define E1000_ICR_RXSEQ 0x00000008 /* rx sequence error */
|
1215 |
|
|
#define E1000_ICR_RXDMT0 0x00000010 /* rx desc min. threshold (0) */
|
1216 |
|
|
#define E1000_ICR_RXO 0x00000040 /* rx overrun */
|
1217 |
|
|
#define E1000_ICR_RXT0 0x00000080 /* rx timer intr (ring 0) */
|
1218 |
|
|
#define E1000_ICR_MDAC 0x00000200 /* MDIO access complete */
|
1219 |
|
|
#define E1000_ICR_RXCFG 0x00000400 /* RX /c/ ordered set */
|
1220 |
|
|
#define E1000_ICR_GPI_EN0 0x00000800 /* GP Int 0 */
|
1221 |
|
|
#define E1000_ICR_GPI_EN1 0x00001000 /* GP Int 1 */
|
1222 |
|
|
#define E1000_ICR_GPI_EN2 0x00002000 /* GP Int 2 */
|
1223 |
|
|
#define E1000_ICR_GPI_EN3 0x00004000 /* GP Int 3 */
|
1224 |
|
|
#define E1000_ICR_TXD_LOW 0x00008000
|
1225 |
|
|
#define E1000_ICR_SRPD 0x00010000
|
1226 |
|
|
|
1227 |
|
|
/* Interrupt Cause Set */
|
1228 |
|
|
#define E1000_ICS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
|
1229 |
|
|
#define E1000_ICS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
|
1230 |
|
|
#define E1000_ICS_LSC E1000_ICR_LSC /* Link Status Change */
|
1231 |
|
|
#define E1000_ICS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
|
1232 |
|
|
#define E1000_ICS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
|
1233 |
|
|
#define E1000_ICS_RXO E1000_ICR_RXO /* rx overrun */
|
1234 |
|
|
#define E1000_ICS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
|
1235 |
|
|
#define E1000_ICS_MDAC E1000_ICR_MDAC /* MDIO access complete */
|
1236 |
|
|
#define E1000_ICS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
|
1237 |
|
|
#define E1000_ICS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
|
1238 |
|
|
#define E1000_ICS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
|
1239 |
|
|
#define E1000_ICS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
|
1240 |
|
|
#define E1000_ICS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
|
1241 |
|
|
#define E1000_ICS_TXD_LOW E1000_ICR_TXD_LOW
|
1242 |
|
|
#define E1000_ICS_SRPD E1000_ICR_SRPD
|
1243 |
|
|
|
1244 |
|
|
/* Interrupt Mask Set */
|
1245 |
|
|
#define E1000_IMS_TXDW E1000_ICR_TXDW /* Transmit desc written back */
|
1246 |
|
|
#define E1000_IMS_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
|
1247 |
|
|
#define E1000_IMS_LSC E1000_ICR_LSC /* Link Status Change */
|
1248 |
|
|
#define E1000_IMS_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
|
1249 |
|
|
#define E1000_IMS_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
|
1250 |
|
|
#define E1000_IMS_RXO E1000_ICR_RXO /* rx overrun */
|
1251 |
|
|
#define E1000_IMS_RXT0 E1000_ICR_RXT0 /* rx timer intr */
|
1252 |
|
|
#define E1000_IMS_MDAC E1000_ICR_MDAC /* MDIO access complete */
|
1253 |
|
|
#define E1000_IMS_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
|
1254 |
|
|
#define E1000_IMS_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
|
1255 |
|
|
#define E1000_IMS_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
|
1256 |
|
|
#define E1000_IMS_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
|
1257 |
|
|
#define E1000_IMS_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
|
1258 |
|
|
#define E1000_IMS_TXD_LOW E1000_ICR_TXD_LOW
|
1259 |
|
|
#define E1000_IMS_SRPD E1000_ICR_SRPD
|
1260 |
|
|
|
1261 |
|
|
/* Interrupt Mask Clear */
|
1262 |
|
|
#define E1000_IMC_TXDW E1000_ICR_TXDW /* Transmit desc written back */
|
1263 |
|
|
#define E1000_IMC_TXQE E1000_ICR_TXQE /* Transmit Queue empty */
|
1264 |
|
|
#define E1000_IMC_LSC E1000_ICR_LSC /* Link Status Change */
|
1265 |
|
|
#define E1000_IMC_RXSEQ E1000_ICR_RXSEQ /* rx sequence error */
|
1266 |
|
|
#define E1000_IMC_RXDMT0 E1000_ICR_RXDMT0 /* rx desc min. threshold */
|
1267 |
|
|
#define E1000_IMC_RXO E1000_ICR_RXO /* rx overrun */
|
1268 |
|
|
#define E1000_IMC_RXT0 E1000_ICR_RXT0 /* rx timer intr */
|
1269 |
|
|
#define E1000_IMC_MDAC E1000_ICR_MDAC /* MDIO access complete */
|
1270 |
|
|
#define E1000_IMC_RXCFG E1000_ICR_RXCFG /* RX /c/ ordered set */
|
1271 |
|
|
#define E1000_IMC_GPI_EN0 E1000_ICR_GPI_EN0 /* GP Int 0 */
|
1272 |
|
|
#define E1000_IMC_GPI_EN1 E1000_ICR_GPI_EN1 /* GP Int 1 */
|
1273 |
|
|
#define E1000_IMC_GPI_EN2 E1000_ICR_GPI_EN2 /* GP Int 2 */
|
1274 |
|
|
#define E1000_IMC_GPI_EN3 E1000_ICR_GPI_EN3 /* GP Int 3 */
|
1275 |
|
|
#define E1000_IMC_TXD_LOW E1000_ICR_TXD_LOW
|
1276 |
|
|
#define E1000_IMC_SRPD E1000_ICR_SRPD
|
1277 |
|
|
|
1278 |
|
|
/* Receive Control */
|
1279 |
|
|
#define E1000_RCTL_RST 0x00000001 /* Software reset */
|
1280 |
|
|
#define E1000_RCTL_EN 0x00000002 /* enable */
|
1281 |
|
|
#define E1000_RCTL_SBP 0x00000004 /* store bad packet */
|
1282 |
|
|
#define E1000_RCTL_UPE 0x00000008 /* unicast promiscuous enable */
|
1283 |
|
|
#define E1000_RCTL_MPE 0x00000010 /* multicast promiscuous enab */
|
1284 |
|
|
#define E1000_RCTL_LPE 0x00000020 /* long packet enable */
|
1285 |
|
|
#define E1000_RCTL_LBM_NO 0x00000000 /* no loopback mode */
|
1286 |
|
|
#define E1000_RCTL_LBM_MAC 0x00000040 /* MAC loopback mode */
|
1287 |
|
|
#define E1000_RCTL_LBM_SLP 0x00000080 /* serial link loopback mode */
|
1288 |
|
|
#define E1000_RCTL_LBM_TCVR 0x000000C0 /* tcvr loopback mode */
|
1289 |
|
|
#define E1000_RCTL_RDMTS_HALF 0x00000000 /* rx desc min threshold size */
|
1290 |
|
|
#define E1000_RCTL_RDMTS_QUAT 0x00000100 /* rx desc min threshold size */
|
1291 |
|
|
#define E1000_RCTL_RDMTS_EIGTH 0x00000200 /* rx desc min threshold size */
|
1292 |
|
|
#define E1000_RCTL_MO_SHIFT 12 /* multicast offset shift */
|
1293 |
|
|
#define E1000_RCTL_MO_0 0x00000000 /* multicast offset 11:0 */
|
1294 |
|
|
#define E1000_RCTL_MO_1 0x00001000 /* multicast offset 12:1 */
|
1295 |
|
|
#define E1000_RCTL_MO_2 0x00002000 /* multicast offset 13:2 */
|
1296 |
|
|
#define E1000_RCTL_MO_3 0x00003000 /* multicast offset 15:4 */
|
1297 |
|
|
#define E1000_RCTL_MDR 0x00004000 /* multicast desc ring 0 */
|
1298 |
|
|
#define E1000_RCTL_BAM 0x00008000 /* broadcast enable */
|
1299 |
|
|
/* these buffer sizes are valid if E1000_RCTL_BSEX is 0 */
|
1300 |
|
|
#define E1000_RCTL_SZ_2048 0x00000000 /* rx buffer size 2048 */
|
1301 |
|
|
#define E1000_RCTL_SZ_1024 0x00010000 /* rx buffer size 1024 */
|
1302 |
|
|
#define E1000_RCTL_SZ_512 0x00020000 /* rx buffer size 512 */
|
1303 |
|
|
#define E1000_RCTL_SZ_256 0x00030000 /* rx buffer size 256 */
|
1304 |
|
|
/* these buffer sizes are valid if E1000_RCTL_BSEX is 1 */
|
1305 |
|
|
#define E1000_RCTL_SZ_16384 0x00010000 /* rx buffer size 16384 */
|
1306 |
|
|
#define E1000_RCTL_SZ_8192 0x00020000 /* rx buffer size 8192 */
|
1307 |
|
|
#define E1000_RCTL_SZ_4096 0x00030000 /* rx buffer size 4096 */
|
1308 |
|
|
#define E1000_RCTL_VFE 0x00040000 /* vlan filter enable */
|
1309 |
|
|
#define E1000_RCTL_CFIEN 0x00080000 /* canonical form enable */
|
1310 |
|
|
#define E1000_RCTL_CFI 0x00100000 /* canonical form indicator */
|
1311 |
|
|
#define E1000_RCTL_DPF 0x00400000 /* discard pause frames */
|
1312 |
|
|
#define E1000_RCTL_PMCF 0x00800000 /* pass MAC control frames */
|
1313 |
|
|
#define E1000_RCTL_BSEX 0x02000000 /* Buffer size extension */
|
1314 |
|
|
#define E1000_RCTL_SECRC 0x04000000 /* Strip Ethernet CRC */
|
1315 |
|
|
|
1316 |
|
|
/* Receive Descriptor */
|
1317 |
|
|
#define E1000_RDT_DELAY 0x0000ffff /* Delay timer (1=1024us) */
|
1318 |
|
|
#define E1000_RDT_FPDB 0x80000000 /* Flush descriptor block */
|
1319 |
|
|
#define E1000_RDLEN_LEN 0x0007ff80 /* descriptor length */
|
1320 |
|
|
#define E1000_RDH_RDH 0x0000ffff /* receive descriptor head */
|
1321 |
|
|
#define E1000_RDT_RDT 0x0000ffff /* receive descriptor tail */
|
1322 |
|
|
|
1323 |
|
|
/* Flow Control */
|
1324 |
|
|
#define E1000_FCRTH_RTH 0x0000FFF8 /* Mask Bits[15:3] for RTH */
|
1325 |
|
|
#define E1000_FCRTH_XFCE 0x80000000 /* External Flow Control Enable */
|
1326 |
|
|
#define E1000_FCRTL_RTL 0x0000FFF8 /* Mask Bits[15:3] for RTL */
|
1327 |
|
|
#define E1000_FCRTL_XONE 0x80000000 /* Enable XON frame transmission */
|
1328 |
|
|
|
1329 |
|
|
/* Receive Descriptor Control */
|
1330 |
|
|
#define E1000_RXDCTL_PTHRESH 0x0000003F /* RXDCTL Prefetch Threshold */
|
1331 |
|
|
#define E1000_RXDCTL_HTHRESH 0x00003F00 /* RXDCTL Host Threshold */
|
1332 |
|
|
#define E1000_RXDCTL_WTHRESH 0x003F0000 /* RXDCTL Writeback Threshold */
|
1333 |
|
|
#define E1000_RXDCTL_GRAN 0x01000000 /* RXDCTL Granularity */
|
1334 |
|
|
|
1335 |
|
|
/* Transmit Descriptor Control */
|
1336 |
|
|
#define E1000_TXDCTL_PTHRESH 0x000000FF /* TXDCTL Prefetch Threshold */
|
1337 |
|
|
#define E1000_TXDCTL_HTHRESH 0x0000FF00 /* TXDCTL Host Threshold */
|
1338 |
|
|
#define E1000_TXDCTL_WTHRESH 0x00FF0000 /* TXDCTL Writeback Threshold */
|
1339 |
|
|
#define E1000_TXDCTL_GRAN 0x01000000 /* TXDCTL Granularity */
|
1340 |
|
|
#define E1000_TXDCTL_LWTHRESH 0xFE000000 /* TXDCTL Low Threshold */
|
1341 |
|
|
#define E1000_TXDCTL_FULL_TX_DESC_WB 0x01010000 /* GRAN=1, WTHRESH=1 */
|
1342 |
|
|
|
1343 |
|
|
/* Transmit Configuration Word */
|
1344 |
|
|
#define E1000_TXCW_FD 0x00000020 /* TXCW full duplex */
|
1345 |
|
|
#define E1000_TXCW_HD 0x00000040 /* TXCW half duplex */
|
1346 |
|
|
#define E1000_TXCW_PAUSE 0x00000080 /* TXCW sym pause request */
|
1347 |
|
|
#define E1000_TXCW_ASM_DIR 0x00000100 /* TXCW astm pause direction */
|
1348 |
|
|
#define E1000_TXCW_PAUSE_MASK 0x00000180 /* TXCW pause request mask */
|
1349 |
|
|
#define E1000_TXCW_RF 0x00003000 /* TXCW remote fault */
|
1350 |
|
|
#define E1000_TXCW_NP 0x00008000 /* TXCW next page */
|
1351 |
|
|
#define E1000_TXCW_CW 0x0000ffff /* TxConfigWord mask */
|
1352 |
|
|
#define E1000_TXCW_TXC 0x40000000 /* Transmit Config control */
|
1353 |
|
|
#define E1000_TXCW_ANE 0x80000000 /* Auto-neg enable */
|
1354 |
|
|
|
1355 |
|
|
/* Receive Configuration Word */
|
1356 |
|
|
#define E1000_RXCW_CW 0x0000ffff /* RxConfigWord mask */
|
1357 |
|
|
#define E1000_RXCW_NC 0x04000000 /* Receive config no carrier */
|
1358 |
|
|
#define E1000_RXCW_IV 0x08000000 /* Receive config invalid */
|
1359 |
|
|
#define E1000_RXCW_CC 0x10000000 /* Receive config change */
|
1360 |
|
|
#define E1000_RXCW_C 0x20000000 /* Receive config */
|
1361 |
|
|
#define E1000_RXCW_SYNCH 0x40000000 /* Receive config synch */
|
1362 |
|
|
#define E1000_RXCW_ANC 0x80000000 /* Auto-neg complete */
|
1363 |
|
|
|
1364 |
|
|
/* Transmit Control */
|
1365 |
|
|
#define E1000_TCTL_RST 0x00000001 /* software reset */
|
1366 |
|
|
#define E1000_TCTL_EN 0x00000002 /* enable tx */
|
1367 |
|
|
#define E1000_TCTL_BCE 0x00000004 /* busy check enable */
|
1368 |
|
|
#define E1000_TCTL_PSP 0x00000008 /* pad short packets */
|
1369 |
|
|
#define E1000_TCTL_CT 0x00000ff0 /* collision threshold */
|
1370 |
|
|
#define E1000_TCTL_COLD 0x003ff000 /* collision distance */
|
1371 |
|
|
#define E1000_TCTL_SWXOFF 0x00400000 /* SW Xoff transmission */
|
1372 |
|
|
#define E1000_TCTL_PBE 0x00800000 /* Packet Burst Enable */
|
1373 |
|
|
#define E1000_TCTL_RTLC 0x01000000 /* Re-transmit on late collision */
|
1374 |
|
|
#define E1000_TCTL_NRTU 0x02000000 /* No Re-transmit on underrun */
|
1375 |
|
|
|
1376 |
|
|
/* Receive Checksum Control */
|
1377 |
|
|
#define E1000_RXCSUM_PCSS_MASK 0x000000FF /* Packet Checksum Start */
|
1378 |
|
|
#define E1000_RXCSUM_IPOFL 0x00000100 /* IPv4 checksum offload */
|
1379 |
|
|
#define E1000_RXCSUM_TUOFL 0x00000200 /* TCP / UDP checksum offload */
|
1380 |
|
|
#define E1000_RXCSUM_IPV6OFL 0x00000400 /* IPv6 checksum offload */
|
1381 |
|
|
|
1382 |
|
|
/* Definitions for power management and wakeup registers */
|
1383 |
|
|
/* Wake Up Control */
|
1384 |
|
|
#define E1000_WUC_APME 0x00000001 /* APM Enable */
|
1385 |
|
|
#define E1000_WUC_PME_EN 0x00000002 /* PME Enable */
|
1386 |
|
|
#define E1000_WUC_PME_STATUS 0x00000004 /* PME Status */
|
1387 |
|
|
#define E1000_WUC_APMPME 0x00000008 /* Assert PME on APM Wakeup */
|
1388 |
|
|
#define E1000_WUC_SPM 0x80000000 /* Enable SPM */
|
1389 |
|
|
|
1390 |
|
|
/* Wake Up Filter Control */
|
1391 |
|
|
#define E1000_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */
|
1392 |
|
|
#define E1000_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */
|
1393 |
|
|
#define E1000_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */
|
1394 |
|
|
#define E1000_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */
|
1395 |
|
|
#define E1000_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */
|
1396 |
|
|
#define E1000_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */
|
1397 |
|
|
#define E1000_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */
|
1398 |
|
|
#define E1000_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */
|
1399 |
|
|
#define E1000_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */
|
1400 |
|
|
#define E1000_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */
|
1401 |
|
|
#define E1000_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */
|
1402 |
|
|
#define E1000_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */
|
1403 |
|
|
#define E1000_WUFC_ALL_FILTERS 0x000F00FF /* Mask for all wakeup filters */
|
1404 |
|
|
#define E1000_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */
|
1405 |
|
|
#define E1000_WUFC_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
|
1406 |
|
|
|
1407 |
|
|
/* Wake Up Status */
|
1408 |
|
|
#define E1000_WUS_LNKC 0x00000001 /* Link Status Changed */
|
1409 |
|
|
#define E1000_WUS_MAG 0x00000002 /* Magic Packet Received */
|
1410 |
|
|
#define E1000_WUS_EX 0x00000004 /* Directed Exact Received */
|
1411 |
|
|
#define E1000_WUS_MC 0x00000008 /* Directed Multicast Received */
|
1412 |
|
|
#define E1000_WUS_BC 0x00000010 /* Broadcast Received */
|
1413 |
|
|
#define E1000_WUS_ARP 0x00000020 /* ARP Request Packet Received */
|
1414 |
|
|
#define E1000_WUS_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Received */
|
1415 |
|
|
#define E1000_WUS_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Received */
|
1416 |
|
|
#define E1000_WUS_FLX0 0x00010000 /* Flexible Filter 0 Match */
|
1417 |
|
|
#define E1000_WUS_FLX1 0x00020000 /* Flexible Filter 1 Match */
|
1418 |
|
|
#define E1000_WUS_FLX2 0x00040000 /* Flexible Filter 2 Match */
|
1419 |
|
|
#define E1000_WUS_FLX3 0x00080000 /* Flexible Filter 3 Match */
|
1420 |
|
|
#define E1000_WUS_FLX_FILTERS 0x000F0000 /* Mask for the 4 flexible filters */
|
1421 |
|
|
|
1422 |
|
|
/* Management Control */
|
1423 |
|
|
#define E1000_MANC_SMBUS_EN 0x00000001 /* SMBus Enabled - RO */
|
1424 |
|
|
#define E1000_MANC_ASF_EN 0x00000002 /* ASF Enabled - RO */
|
1425 |
|
|
#define E1000_MANC_R_ON_FORCE 0x00000004 /* Reset on Force TCO - RO */
|
1426 |
|
|
#define E1000_MANC_RMCP_EN 0x00000100 /* Enable RCMP 026Fh Filtering */
|
1427 |
|
|
#define E1000_MANC_0298_EN 0x00000200 /* Enable RCMP 0298h Filtering */
|
1428 |
|
|
#define E1000_MANC_IPV4_EN 0x00000400 /* Enable IPv4 */
|
1429 |
|
|
#define E1000_MANC_IPV6_EN 0x00000800 /* Enable IPv6 */
|
1430 |
|
|
#define E1000_MANC_SNAP_EN 0x00001000 /* Accept LLC/SNAP */
|
1431 |
|
|
#define E1000_MANC_ARP_EN 0x00002000 /* Enable ARP Request Filtering */
|
1432 |
|
|
#define E1000_MANC_NEIGHBOR_EN 0x00004000 /* Enable Neighbor Discovery
|
1433 |
|
|
* Filtering */
|
1434 |
|
|
#define E1000_MANC_TCO_RESET 0x00010000 /* TCO Reset Occurred */
|
1435 |
|
|
#define E1000_MANC_RCV_TCO_EN 0x00020000 /* Receive TCO Packets Enabled */
|
1436 |
|
|
#define E1000_MANC_REPORT_STATUS 0x00040000 /* Status Reporting Enabled */
|
1437 |
|
|
#define E1000_MANC_SMB_REQ 0x01000000 /* SMBus Request */
|
1438 |
|
|
#define E1000_MANC_SMB_GNT 0x02000000 /* SMBus Grant */
|
1439 |
|
|
#define E1000_MANC_SMB_CLK_IN 0x04000000 /* SMBus Clock In */
|
1440 |
|
|
#define E1000_MANC_SMB_DATA_IN 0x08000000 /* SMBus Data In */
|
1441 |
|
|
#define E1000_MANC_SMB_DATA_OUT 0x10000000 /* SMBus Data Out */
|
1442 |
|
|
#define E1000_MANC_SMB_CLK_OUT 0x20000000 /* SMBus Clock Out */
|
1443 |
|
|
|
1444 |
|
|
#define E1000_MANC_SMB_DATA_OUT_SHIFT 28 /* SMBus Data Out Shift */
|
1445 |
|
|
#define E1000_MANC_SMB_CLK_OUT_SHIFT 29 /* SMBus Clock Out Shift */
|
1446 |
|
|
|
1447 |
|
|
/* Wake Up Packet Length */
|
1448 |
|
|
#define E1000_WUPL_LENGTH_MASK 0x0FFF /* Only the lower 12 bits are valid */
|
1449 |
|
|
|
1450 |
|
|
#define E1000_MDALIGN 4096
|
1451 |
|
|
|
1452 |
|
|
/* EEPROM Commands - Microwire */
|
1453 |
|
|
#define EEPROM_READ_OPCODE_MICROWIRE 0x6 /* EEPROM read opcode */
|
1454 |
|
|
#define EEPROM_WRITE_OPCODE_MICROWIRE 0x5 /* EEPROM write opcode */
|
1455 |
|
|
#define EEPROM_ERASE_OPCODE_MICROWIRE 0x7 /* EEPROM erase opcode */
|
1456 |
|
|
#define EEPROM_EWEN_OPCODE_MICROWIRE 0x13 /* EEPROM erase/write enable */
|
1457 |
|
|
#define EEPROM_EWDS_OPCODE_MICROWIRE 0x10 /* EEPROM erast/write disable */
|
1458 |
|
|
|
1459 |
|
|
/* EEPROM Commands - SPI */
|
1460 |
|
|
#define EEPROM_MAX_RETRY_SPI 5000 /* Max wait of 5ms, for RDY signal */
|
1461 |
|
|
#define EEPROM_READ_OPCODE_SPI 0x3 /* EEPROM read opcode */
|
1462 |
|
|
#define EEPROM_WRITE_OPCODE_SPI 0x2 /* EEPROM write opcode */
|
1463 |
|
|
#define EEPROM_A8_OPCODE_SPI 0x8 /* opcode bit-3 = address bit-8 */
|
1464 |
|
|
#define EEPROM_WREN_OPCODE_SPI 0x6 /* EEPROM set Write Enable latch */
|
1465 |
|
|
#define EEPROM_WRDI_OPCODE_SPI 0x4 /* EEPROM reset Write Enable latch */
|
1466 |
|
|
#define EEPROM_RDSR_OPCODE_SPI 0x5 /* EEPROM read Status register */
|
1467 |
|
|
#define EEPROM_WRSR_OPCODE_SPI 0x1 /* EEPROM write Status register */
|
1468 |
|
|
|
1469 |
|
|
/* EEPROM Size definitions */
|
1470 |
|
|
#define EEPROM_SIZE_16KB 0x1800
|
1471 |
|
|
#define EEPROM_SIZE_8KB 0x1400
|
1472 |
|
|
#define EEPROM_SIZE_4KB 0x1000
|
1473 |
|
|
#define EEPROM_SIZE_2KB 0x0C00
|
1474 |
|
|
#define EEPROM_SIZE_1KB 0x0800
|
1475 |
|
|
#define EEPROM_SIZE_512B 0x0400
|
1476 |
|
|
#define EEPROM_SIZE_128B 0x0000
|
1477 |
|
|
#define EEPROM_SIZE_MASK 0x1C00
|
1478 |
|
|
|
1479 |
|
|
/* EEPROM Word Offsets */
|
1480 |
|
|
#define EEPROM_COMPAT 0x0003
|
1481 |
|
|
#define EEPROM_ID_LED_SETTINGS 0x0004
|
1482 |
|
|
#define EEPROM_SERDES_AMPLITUDE 0x0006 /* For SERDES output amplitude adjustment. */
|
1483 |
|
|
#define EEPROM_INIT_CONTROL1_REG 0x000A
|
1484 |
|
|
#define EEPROM_INIT_CONTROL2_REG 0x000F
|
1485 |
|
|
#define EEPROM_INIT_CONTROL3_PORT_B 0x0014
|
1486 |
|
|
#define EEPROM_INIT_CONTROL3_PORT_A 0x0024
|
1487 |
|
|
#define EEPROM_CFG 0x0012
|
1488 |
|
|
#define EEPROM_FLASH_VERSION 0x0032
|
1489 |
|
|
#define EEPROM_CHECKSUM_REG 0x003F
|
1490 |
|
|
|
1491 |
|
|
/* Word definitions for ID LED Settings */
|
1492 |
|
|
#define ID_LED_RESERVED_0000 0x0000
|
1493 |
|
|
#define ID_LED_RESERVED_FFFF 0xFFFF
|
1494 |
|
|
#define ID_LED_DEFAULT ((ID_LED_OFF1_ON2 << 12) | \
|
1495 |
|
|
(ID_LED_OFF1_OFF2 << 8) | \
|
1496 |
|
|
(ID_LED_DEF1_DEF2 << 4) | \
|
1497 |
|
|
(ID_LED_DEF1_DEF2))
|
1498 |
|
|
#define ID_LED_DEF1_DEF2 0x1
|
1499 |
|
|
#define ID_LED_DEF1_ON2 0x2
|
1500 |
|
|
#define ID_LED_DEF1_OFF2 0x3
|
1501 |
|
|
#define ID_LED_ON1_DEF2 0x4
|
1502 |
|
|
#define ID_LED_ON1_ON2 0x5
|
1503 |
|
|
#define ID_LED_ON1_OFF2 0x6
|
1504 |
|
|
#define ID_LED_OFF1_DEF2 0x7
|
1505 |
|
|
#define ID_LED_OFF1_ON2 0x8
|
1506 |
|
|
#define ID_LED_OFF1_OFF2 0x9
|
1507 |
|
|
|
1508 |
|
|
#define IGP_ACTIVITY_LED_MASK 0xFFFFF0FF
|
1509 |
|
|
#define IGP_ACTIVITY_LED_ENABLE 0x0300
|
1510 |
|
|
#define IGP_LED3_MODE 0x07000000
|
1511 |
|
|
|
1512 |
|
|
|
1513 |
|
|
/* Mask bits for SERDES amplitude adjustment in Word 6 of the EEPROM */
|
1514 |
|
|
#define EEPROM_SERDES_AMPLITUDE_MASK 0x000F
|
1515 |
|
|
|
1516 |
|
|
/* Mask bits for fields in Word 0x0a of the EEPROM */
|
1517 |
|
|
#define EEPROM_WORD0A_ILOS 0x0010
|
1518 |
|
|
#define EEPROM_WORD0A_SWDPIO 0x01E0
|
1519 |
|
|
#define EEPROM_WORD0A_LRST 0x0200
|
1520 |
|
|
#define EEPROM_WORD0A_FD 0x0400
|
1521 |
|
|
#define EEPROM_WORD0A_66MHZ 0x0800
|
1522 |
|
|
|
1523 |
|
|
/* Mask bits for fields in Word 0x0f of the EEPROM */
|
1524 |
|
|
#define EEPROM_WORD0F_PAUSE_MASK 0x3000
|
1525 |
|
|
#define EEPROM_WORD0F_PAUSE 0x1000
|
1526 |
|
|
#define EEPROM_WORD0F_ASM_DIR 0x2000
|
1527 |
|
|
#define EEPROM_WORD0F_ANE 0x0800
|
1528 |
|
|
#define EEPROM_WORD0F_SWPDIO_EXT 0x00F0
|
1529 |
|
|
|
1530 |
|
|
/* For checksumming, the sum of all words in the EEPROM should equal 0xBABA. */
|
1531 |
|
|
#define EEPROM_SUM 0xBABA
|
1532 |
|
|
|
1533 |
|
|
/* EEPROM Map defines (WORD OFFSETS)*/
|
1534 |
|
|
#define EEPROM_NODE_ADDRESS_BYTE_0 0
|
1535 |
|
|
#define EEPROM_PBA_BYTE_1 8
|
1536 |
|
|
|
1537 |
|
|
#define EEPROM_RESERVED_WORD 0xFFFF
|
1538 |
|
|
|
1539 |
|
|
/* EEPROM Map Sizes (Byte Counts) */
|
1540 |
|
|
#define PBA_SIZE 4
|
1541 |
|
|
|
1542 |
|
|
/* Collision related configuration parameters */
|
1543 |
|
|
#define E1000_COLLISION_THRESHOLD 16
|
1544 |
|
|
#define E1000_CT_SHIFT 4
|
1545 |
|
|
#define E1000_COLLISION_DISTANCE 64
|
1546 |
|
|
#define E1000_FDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
|
1547 |
|
|
#define E1000_HDX_COLLISION_DISTANCE E1000_COLLISION_DISTANCE
|
1548 |
|
|
#define E1000_COLD_SHIFT 12
|
1549 |
|
|
|
1550 |
|
|
/* Number of Transmit and Receive Descriptors must be a multiple of 8 */
|
1551 |
|
|
#define REQ_TX_DESCRIPTOR_MULTIPLE 8
|
1552 |
|
|
#define REQ_RX_DESCRIPTOR_MULTIPLE 8
|
1553 |
|
|
|
1554 |
|
|
/* Default values for the transmit IPG register */
|
1555 |
|
|
#define DEFAULT_82542_TIPG_IPGT 10
|
1556 |
|
|
#define DEFAULT_82543_TIPG_IPGT_FIBER 9
|
1557 |
|
|
#define DEFAULT_82543_TIPG_IPGT_COPPER 8
|
1558 |
|
|
|
1559 |
|
|
#define E1000_TIPG_IPGT_MASK 0x000003FF
|
1560 |
|
|
#define E1000_TIPG_IPGR1_MASK 0x000FFC00
|
1561 |
|
|
#define E1000_TIPG_IPGR2_MASK 0x3FF00000
|
1562 |
|
|
|
1563 |
|
|
#define DEFAULT_82542_TIPG_IPGR1 2
|
1564 |
|
|
#define DEFAULT_82543_TIPG_IPGR1 8
|
1565 |
|
|
#define E1000_TIPG_IPGR1_SHIFT 10
|
1566 |
|
|
|
1567 |
|
|
#define DEFAULT_82542_TIPG_IPGR2 10
|
1568 |
|
|
#define DEFAULT_82543_TIPG_IPGR2 6
|
1569 |
|
|
#define E1000_TIPG_IPGR2_SHIFT 20
|
1570 |
|
|
|
1571 |
|
|
#define E1000_TXDMAC_DPP 0x00000001
|
1572 |
|
|
|
1573 |
|
|
/* Adaptive IFS defines */
|
1574 |
|
|
#define TX_THRESHOLD_START 8
|
1575 |
|
|
#define TX_THRESHOLD_INCREMENT 10
|
1576 |
|
|
#define TX_THRESHOLD_DECREMENT 1
|
1577 |
|
|
#define TX_THRESHOLD_STOP 190
|
1578 |
|
|
#define TX_THRESHOLD_DISABLE 0
|
1579 |
|
|
#define TX_THRESHOLD_TIMER_MS 10000
|
1580 |
|
|
#define MIN_NUM_XMITS 1000
|
1581 |
|
|
#define IFS_MAX 80
|
1582 |
|
|
#define IFS_STEP 10
|
1583 |
|
|
#define IFS_MIN 40
|
1584 |
|
|
#define IFS_RATIO 4
|
1585 |
|
|
|
1586 |
|
|
/* PBA constants */
|
1587 |
|
|
#define E1000_PBA_16K 0x0010 /* 16KB, default TX allocation */
|
1588 |
|
|
#define E1000_PBA_22K 0x0016
|
1589 |
|
|
#define E1000_PBA_24K 0x0018
|
1590 |
|
|
#define E1000_PBA_30K 0x001E
|
1591 |
|
|
#define E1000_PBA_40K 0x0028
|
1592 |
|
|
#define E1000_PBA_48K 0x0030 /* 48KB, default RX allocation */
|
1593 |
|
|
|
1594 |
|
|
/* Flow Control Constants */
|
1595 |
|
|
#define FLOW_CONTROL_ADDRESS_LOW 0x00C28001
|
1596 |
|
|
#define FLOW_CONTROL_ADDRESS_HIGH 0x00000100
|
1597 |
|
|
#define FLOW_CONTROL_TYPE 0x8808
|
1598 |
|
|
|
1599 |
|
|
/* The historical defaults for the flow control values are given below. */
|
1600 |
|
|
#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */
|
1601 |
|
|
#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */
|
1602 |
|
|
#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */
|
1603 |
|
|
|
1604 |
|
|
/* PCIX Config space */
|
1605 |
|
|
#define PCIX_COMMAND_REGISTER 0xE6
|
1606 |
|
|
#define PCIX_STATUS_REGISTER_LO 0xE8
|
1607 |
|
|
#define PCIX_STATUS_REGISTER_HI 0xEA
|
1608 |
|
|
|
1609 |
|
|
#define PCIX_COMMAND_MMRBC_MASK 0x000C
|
1610 |
|
|
#define PCIX_COMMAND_MMRBC_SHIFT 0x2
|
1611 |
|
|
#define PCIX_STATUS_HI_MMRBC_MASK 0x0060
|
1612 |
|
|
#define PCIX_STATUS_HI_MMRBC_SHIFT 0x5
|
1613 |
|
|
#define PCIX_STATUS_HI_MMRBC_4K 0x3
|
1614 |
|
|
#define PCIX_STATUS_HI_MMRBC_2K 0x2
|
1615 |
|
|
|
1616 |
|
|
|
1617 |
|
|
/* Number of bits required to shift right the "pause" bits from the
|
1618 |
|
|
* EEPROM (bits 13:12) to the "pause" (bits 8:7) field in the TXCW register.
|
1619 |
|
|
*/
|
1620 |
|
|
#define PAUSE_SHIFT 5
|
1621 |
|
|
|
1622 |
|
|
/* Number of bits required to shift left the "SWDPIO" bits from the
|
1623 |
|
|
* EEPROM (bits 8:5) to the "SWDPIO" (bits 25:22) field in the CTRL register.
|
1624 |
|
|
*/
|
1625 |
|
|
#define SWDPIO_SHIFT 17
|
1626 |
|
|
|
1627 |
|
|
/* Number of bits required to shift left the "SWDPIO_EXT" bits from the
|
1628 |
|
|
* EEPROM word F (bits 7:4) to the bits 11:8 of The Extended CTRL register.
|
1629 |
|
|
*/
|
1630 |
|
|
#define SWDPIO__EXT_SHIFT 4
|
1631 |
|
|
|
1632 |
|
|
/* Number of bits required to shift left the "ILOS" bit from the EEPROM
|
1633 |
|
|
* (bit 4) to the "ILOS" (bit 7) field in the CTRL register.
|
1634 |
|
|
*/
|
1635 |
|
|
#define ILOS_SHIFT 3
|
1636 |
|
|
|
1637 |
|
|
|
1638 |
|
|
#define RECEIVE_BUFFER_ALIGN_SIZE (256)
|
1639 |
|
|
|
1640 |
|
|
/* Number of milliseconds we wait for auto-negotiation to complete */
|
1641 |
|
|
#define LINK_UP_TIMEOUT 500
|
1642 |
|
|
|
1643 |
|
|
#define E1000_TX_BUFFER_SIZE ((uint32_t)1514)
|
1644 |
|
|
|
1645 |
|
|
/* The carrier extension symbol, as received by the NIC. */
|
1646 |
|
|
#define CARRIER_EXTENSION 0x0F
|
1647 |
|
|
|
1648 |
|
|
/* TBI_ACCEPT macro definition:
|
1649 |
|
|
*
|
1650 |
|
|
* This macro requires:
|
1651 |
|
|
* adapter = a pointer to struct e1000_hw
|
1652 |
|
|
* status = the 8 bit status field of the RX descriptor with EOP set
|
1653 |
|
|
* error = the 8 bit error field of the RX descriptor with EOP set
|
1654 |
|
|
* length = the sum of all the length fields of the RX descriptors that
|
1655 |
|
|
* make up the current frame
|
1656 |
|
|
* last_byte = the last byte of the frame DMAed by the hardware
|
1657 |
|
|
* max_frame_length = the maximum frame length we want to accept.
|
1658 |
|
|
* min_frame_length = the minimum frame length we want to accept.
|
1659 |
|
|
*
|
1660 |
|
|
* This macro is a conditional that should be used in the interrupt
|
1661 |
|
|
* handler's Rx processing routine when RxErrors have been detected.
|
1662 |
|
|
*
|
1663 |
|
|
* Typical use:
|
1664 |
|
|
* ...
|
1665 |
|
|
* if (TBI_ACCEPT) {
|
1666 |
|
|
* accept_frame = TRUE;
|
1667 |
|
|
* e1000_tbi_adjust_stats(adapter, MacAddress);
|
1668 |
|
|
* frame_length--;
|
1669 |
|
|
* } else {
|
1670 |
|
|
* accept_frame = FALSE;
|
1671 |
|
|
* }
|
1672 |
|
|
* ...
|
1673 |
|
|
*/
|
1674 |
|
|
|
1675 |
|
|
#define TBI_ACCEPT(adapter, status, errors, length, last_byte) \
|
1676 |
|
|
((adapter)->tbi_compatibility_on && \
|
1677 |
|
|
(((errors) & E1000_RXD_ERR_FRAME_ERR_MASK) == E1000_RXD_ERR_CE) && \
|
1678 |
|
|
((last_byte) == CARRIER_EXTENSION) && \
|
1679 |
|
|
(((status) & E1000_RXD_STAT_VP) ? \
|
1680 |
|
|
(((length) > ((adapter)->min_frame_size - VLAN_TAG_SIZE)) && \
|
1681 |
|
|
((length) <= ((adapter)->max_frame_size + 1))) : \
|
1682 |
|
|
(((length) > (adapter)->min_frame_size) && \
|
1683 |
|
|
((length) <= ((adapter)->max_frame_size + VLAN_TAG_SIZE + 1)))))
|
1684 |
|
|
|
1685 |
|
|
|
1686 |
|
|
/* Structures, enums, and macros for the PHY */
|
1687 |
|
|
|
1688 |
|
|
/* Bit definitions for the Management Data IO (MDIO) and Management Data
|
1689 |
|
|
* Clock (MDC) pins in the Device Control Register.
|
1690 |
|
|
*/
|
1691 |
|
|
#define E1000_CTRL_PHY_RESET_DIR E1000_CTRL_SWDPIO0
|
1692 |
|
|
#define E1000_CTRL_PHY_RESET E1000_CTRL_SWDPIN0
|
1693 |
|
|
#define E1000_CTRL_MDIO_DIR E1000_CTRL_SWDPIO2
|
1694 |
|
|
#define E1000_CTRL_MDIO E1000_CTRL_SWDPIN2
|
1695 |
|
|
#define E1000_CTRL_MDC_DIR E1000_CTRL_SWDPIO3
|
1696 |
|
|
#define E1000_CTRL_MDC E1000_CTRL_SWDPIN3
|
1697 |
|
|
#define E1000_CTRL_PHY_RESET_DIR4 E1000_CTRL_EXT_SDP4_DIR
|
1698 |
|
|
#define E1000_CTRL_PHY_RESET4 E1000_CTRL_EXT_SDP4_DATA
|
1699 |
|
|
|
1700 |
|
|
/* PHY 1000 MII Register/Bit Definitions */
|
1701 |
|
|
/* PHY Registers defined by IEEE */
|
1702 |
|
|
#define PHY_CTRL 0x00 /* Control Register */
|
1703 |
|
|
#define PHY_STATUS 0x01 /* Status Regiser */
|
1704 |
|
|
#define PHY_ID1 0x02 /* Phy Id Reg (word 1) */
|
1705 |
|
|
#define PHY_ID2 0x03 /* Phy Id Reg (word 2) */
|
1706 |
|
|
#define PHY_AUTONEG_ADV 0x04 /* Autoneg Advertisement */
|
1707 |
|
|
#define PHY_LP_ABILITY 0x05 /* Link Partner Ability (Base Page) */
|
1708 |
|
|
#define PHY_AUTONEG_EXP 0x06 /* Autoneg Expansion Reg */
|
1709 |
|
|
#define PHY_NEXT_PAGE_TX 0x07 /* Next Page TX */
|
1710 |
|
|
#define PHY_LP_NEXT_PAGE 0x08 /* Link Partner Next Page */
|
1711 |
|
|
#define PHY_1000T_CTRL 0x09 /* 1000Base-T Control Reg */
|
1712 |
|
|
#define PHY_1000T_STATUS 0x0A /* 1000Base-T Status Reg */
|
1713 |
|
|
#define PHY_EXT_STATUS 0x0F /* Extended Status Reg */
|
1714 |
|
|
|
1715 |
|
|
/* M88E1000 Specific Registers */
|
1716 |
|
|
#define M88E1000_PHY_SPEC_CTRL 0x10 /* PHY Specific Control Register */
|
1717 |
|
|
#define M88E1000_PHY_SPEC_STATUS 0x11 /* PHY Specific Status Register */
|
1718 |
|
|
#define M88E1000_INT_ENABLE 0x12 /* Interrupt Enable Register */
|
1719 |
|
|
#define M88E1000_INT_STATUS 0x13 /* Interrupt Status Register */
|
1720 |
|
|
#define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */
|
1721 |
|
|
#define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */
|
1722 |
|
|
|
1723 |
|
|
#define M88E1000_PHY_EXT_CTRL 0x1A /* PHY extend control register */
|
1724 |
|
|
#define M88E1000_PHY_PAGE_SELECT 0x1D /* Reg 29 for page number setting */
|
1725 |
|
|
#define M88E1000_PHY_GEN_CONTROL 0x1E /* Its meaning depends on reg 29 */
|
1726 |
|
|
#define M88E1000_PHY_VCO_REG_BIT8 0x100 /* Bits 8 & 11 are adjusted for */
|
1727 |
|
|
#define M88E1000_PHY_VCO_REG_BIT11 0x800 /* improved BER performance */
|
1728 |
|
|
|
1729 |
|
|
#define IGP01E1000_IEEE_REGS_PAGE 0x0000
|
1730 |
|
|
#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300
|
1731 |
|
|
#define IGP01E1000_IEEE_FORCE_GIGA 0x0140
|
1732 |
|
|
|
1733 |
|
|
/* IGP01E1000 Specific Registers */
|
1734 |
|
|
#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */
|
1735 |
|
|
#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */
|
1736 |
|
|
#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */
|
1737 |
|
|
#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */
|
1738 |
|
|
#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */
|
1739 |
|
|
#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */
|
1740 |
|
|
#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */
|
1741 |
|
|
|
1742 |
|
|
/* IGP01E1000 AGC Registers - stores the cable length values*/
|
1743 |
|
|
#define IGP01E1000_PHY_AGC_A 0x1172
|
1744 |
|
|
#define IGP01E1000_PHY_AGC_B 0x1272
|
1745 |
|
|
#define IGP01E1000_PHY_AGC_C 0x1472
|
1746 |
|
|
#define IGP01E1000_PHY_AGC_D 0x1872
|
1747 |
|
|
|
1748 |
|
|
/* IGP01E1000 DSP Reset Register */
|
1749 |
|
|
#define IGP01E1000_PHY_DSP_RESET 0x1F33
|
1750 |
|
|
#define IGP01E1000_PHY_DSP_SET 0x1F71
|
1751 |
|
|
#define IGP01E1000_PHY_DSP_FFE 0x1F35
|
1752 |
|
|
|
1753 |
|
|
#define IGP01E1000_PHY_CHANNEL_NUM 4
|
1754 |
|
|
#define IGP01E1000_PHY_AGC_PARAM_A 0x1171
|
1755 |
|
|
#define IGP01E1000_PHY_AGC_PARAM_B 0x1271
|
1756 |
|
|
#define IGP01E1000_PHY_AGC_PARAM_C 0x1471
|
1757 |
|
|
#define IGP01E1000_PHY_AGC_PARAM_D 0x1871
|
1758 |
|
|
|
1759 |
|
|
#define IGP01E1000_PHY_EDAC_MU_INDEX 0xC000
|
1760 |
|
|
#define IGP01E1000_PHY_EDAC_SIGN_EXT_9_BITS 0x8000
|
1761 |
|
|
|
1762 |
|
|
#define IGP01E1000_PHY_ANALOG_TX_STATE 0x2890
|
1763 |
|
|
#define IGP01E1000_PHY_ANALOG_CLASS_A 0x2000
|
1764 |
|
|
#define IGP01E1000_PHY_FORCE_ANALOG_ENABLE 0x0004
|
1765 |
|
|
#define IGP01E1000_PHY_DSP_FFE_CM_CP 0x0069
|
1766 |
|
|
|
1767 |
|
|
#define IGP01E1000_PHY_DSP_FFE_DEFAULT 0x002A
|
1768 |
|
|
/* IGP01E1000 PCS Initialization register - stores the polarity status when
|
1769 |
|
|
* speed = 1000 Mbps. */
|
1770 |
|
|
#define IGP01E1000_PHY_PCS_INIT_REG 0x00B4
|
1771 |
|
|
#define IGP01E1000_PHY_PCS_CTRL_REG 0x00B5
|
1772 |
|
|
|
1773 |
|
|
#define IGP01E1000_ANALOG_REGS_PAGE 0x20C0
|
1774 |
|
|
|
1775 |
|
|
#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */
|
1776 |
|
|
#define MAX_PHY_MULTI_PAGE_REG 0xF /*Registers that are equal on all pages*/
|
1777 |
|
|
/* PHY Control Register */
|
1778 |
|
|
#define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */
|
1779 |
|
|
#define MII_CR_COLL_TEST_ENABLE 0x0080 /* Collision test enable */
|
1780 |
|
|
#define MII_CR_FULL_DUPLEX 0x0100 /* FDX =1, half duplex =0 */
|
1781 |
|
|
#define MII_CR_RESTART_AUTO_NEG 0x0200 /* Restart auto negotiation */
|
1782 |
|
|
#define MII_CR_ISOLATE 0x0400 /* Isolate PHY from MII */
|
1783 |
|
|
#define MII_CR_POWER_DOWN 0x0800 /* Power down */
|
1784 |
|
|
#define MII_CR_AUTO_NEG_EN 0x1000 /* Auto Neg Enable */
|
1785 |
|
|
#define MII_CR_SPEED_SELECT_LSB 0x2000 /* bits 6,13: 10=1000, 01=100, 00=10 */
|
1786 |
|
|
#define MII_CR_LOOPBACK 0x4000 /* 0 = normal, 1 = loopback */
|
1787 |
|
|
#define MII_CR_RESET 0x8000 /* 0 = normal, 1 = PHY reset */
|
1788 |
|
|
|
1789 |
|
|
/* PHY Status Register */
|
1790 |
|
|
#define MII_SR_EXTENDED_CAPS 0x0001 /* Extended register capabilities */
|
1791 |
|
|
#define MII_SR_JABBER_DETECT 0x0002 /* Jabber Detected */
|
1792 |
|
|
#define MII_SR_LINK_STATUS 0x0004 /* Link Status 1 = link */
|
1793 |
|
|
#define MII_SR_AUTONEG_CAPS 0x0008 /* Auto Neg Capable */
|
1794 |
|
|
#define MII_SR_REMOTE_FAULT 0x0010 /* Remote Fault Detect */
|
1795 |
|
|
#define MII_SR_AUTONEG_COMPLETE 0x0020 /* Auto Neg Complete */
|
1796 |
|
|
#define MII_SR_PREAMBLE_SUPPRESS 0x0040 /* Preamble may be suppressed */
|
1797 |
|
|
#define MII_SR_EXTENDED_STATUS 0x0100 /* Ext. status info in Reg 0x0F */
|
1798 |
|
|
#define MII_SR_100T2_HD_CAPS 0x0200 /* 100T2 Half Duplex Capable */
|
1799 |
|
|
#define MII_SR_100T2_FD_CAPS 0x0400 /* 100T2 Full Duplex Capable */
|
1800 |
|
|
#define MII_SR_10T_HD_CAPS 0x0800 /* 10T Half Duplex Capable */
|
1801 |
|
|
#define MII_SR_10T_FD_CAPS 0x1000 /* 10T Full Duplex Capable */
|
1802 |
|
|
#define MII_SR_100X_HD_CAPS 0x2000 /* 100X Half Duplex Capable */
|
1803 |
|
|
#define MII_SR_100X_FD_CAPS 0x4000 /* 100X Full Duplex Capable */
|
1804 |
|
|
#define MII_SR_100T4_CAPS 0x8000 /* 100T4 Capable */
|
1805 |
|
|
|
1806 |
|
|
/* Autoneg Advertisement Register */
|
1807 |
|
|
#define NWAY_AR_SELECTOR_FIELD 0x0001 /* indicates IEEE 802.3 CSMA/CD */
|
1808 |
|
|
#define NWAY_AR_10T_HD_CAPS 0x0020 /* 10T Half Duplex Capable */
|
1809 |
|
|
#define NWAY_AR_10T_FD_CAPS 0x0040 /* 10T Full Duplex Capable */
|
1810 |
|
|
#define NWAY_AR_100TX_HD_CAPS 0x0080 /* 100TX Half Duplex Capable */
|
1811 |
|
|
#define NWAY_AR_100TX_FD_CAPS 0x0100 /* 100TX Full Duplex Capable */
|
1812 |
|
|
#define NWAY_AR_100T4_CAPS 0x0200 /* 100T4 Capable */
|
1813 |
|
|
#define NWAY_AR_PAUSE 0x0400 /* Pause operation desired */
|
1814 |
|
|
#define NWAY_AR_ASM_DIR 0x0800 /* Asymmetric Pause Direction bit */
|
1815 |
|
|
#define NWAY_AR_REMOTE_FAULT 0x2000 /* Remote Fault detected */
|
1816 |
|
|
#define NWAY_AR_NEXT_PAGE 0x8000 /* Next Page ability supported */
|
1817 |
|
|
|
1818 |
|
|
/* Link Partner Ability Register (Base Page) */
|
1819 |
|
|
#define NWAY_LPAR_SELECTOR_FIELD 0x0000 /* LP protocol selector field */
|
1820 |
|
|
#define NWAY_LPAR_10T_HD_CAPS 0x0020 /* LP is 10T Half Duplex Capable */
|
1821 |
|
|
#define NWAY_LPAR_10T_FD_CAPS 0x0040 /* LP is 10T Full Duplex Capable */
|
1822 |
|
|
#define NWAY_LPAR_100TX_HD_CAPS 0x0080 /* LP is 100TX Half Duplex Capable */
|
1823 |
|
|
#define NWAY_LPAR_100TX_FD_CAPS 0x0100 /* LP is 100TX Full Duplex Capable */
|
1824 |
|
|
#define NWAY_LPAR_100T4_CAPS 0x0200 /* LP is 100T4 Capable */
|
1825 |
|
|
#define NWAY_LPAR_PAUSE 0x0400 /* LP Pause operation desired */
|
1826 |
|
|
#define NWAY_LPAR_ASM_DIR 0x0800 /* LP Asymmetric Pause Direction bit */
|
1827 |
|
|
#define NWAY_LPAR_REMOTE_FAULT 0x2000 /* LP has detected Remote Fault */
|
1828 |
|
|
#define NWAY_LPAR_ACKNOWLEDGE 0x4000 /* LP has rx'd link code word */
|
1829 |
|
|
#define NWAY_LPAR_NEXT_PAGE 0x8000 /* Next Page ability supported */
|
1830 |
|
|
|
1831 |
|
|
/* Autoneg Expansion Register */
|
1832 |
|
|
#define NWAY_ER_LP_NWAY_CAPS 0x0001 /* LP has Auto Neg Capability */
|
1833 |
|
|
#define NWAY_ER_PAGE_RXD 0x0002 /* LP is 10T Half Duplex Capable */
|
1834 |
|
|
#define NWAY_ER_NEXT_PAGE_CAPS 0x0004 /* LP is 10T Full Duplex Capable */
|
1835 |
|
|
#define NWAY_ER_LP_NEXT_PAGE_CAPS 0x0008 /* LP is 100TX Half Duplex Capable */
|
1836 |
|
|
#define NWAY_ER_PAR_DETECT_FAULT 0x0010 /* LP is 100TX Full Duplex Capable */
|
1837 |
|
|
|
1838 |
|
|
/* Next Page TX Register */
|
1839 |
|
|
#define NPTX_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
|
1840 |
|
|
#define NPTX_TOGGLE 0x0800 /* Toggles between exchanges
|
1841 |
|
|
* of different NP
|
1842 |
|
|
*/
|
1843 |
|
|
#define NPTX_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
|
1844 |
|
|
* 0 = cannot comply with msg
|
1845 |
|
|
*/
|
1846 |
|
|
#define NPTX_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
|
1847 |
|
|
#define NPTX_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
|
1848 |
|
|
* 0 = sending last NP
|
1849 |
|
|
*/
|
1850 |
|
|
|
1851 |
|
|
/* Link Partner Next Page Register */
|
1852 |
|
|
#define LP_RNPR_MSG_CODE_FIELD 0x0001 /* NP msg code or unformatted data */
|
1853 |
|
|
#define LP_RNPR_TOGGLE 0x0800 /* Toggles between exchanges
|
1854 |
|
|
* of different NP
|
1855 |
|
|
*/
|
1856 |
|
|
#define LP_RNPR_ACKNOWLDGE2 0x1000 /* 1 = will comply with msg
|
1857 |
|
|
* 0 = cannot comply with msg
|
1858 |
|
|
*/
|
1859 |
|
|
#define LP_RNPR_MSG_PAGE 0x2000 /* formatted(1)/unformatted(0) pg */
|
1860 |
|
|
#define LP_RNPR_ACKNOWLDGE 0x4000 /* 1 = ACK / 0 = NO ACK */
|
1861 |
|
|
#define LP_RNPR_NEXT_PAGE 0x8000 /* 1 = addition NP will follow
|
1862 |
|
|
* 0 = sending last NP
|
1863 |
|
|
*/
|
1864 |
|
|
|
1865 |
|
|
/* 1000BASE-T Control Register */
|
1866 |
|
|
#define CR_1000T_ASYM_PAUSE 0x0080 /* Advertise asymmetric pause bit */
|
1867 |
|
|
#define CR_1000T_HD_CAPS 0x0100 /* Advertise 1000T HD capability */
|
1868 |
|
|
#define CR_1000T_FD_CAPS 0x0200 /* Advertise 1000T FD capability */
|
1869 |
|
|
#define CR_1000T_REPEATER_DTE 0x0400 /* 1=Repeater/switch device port */
|
1870 |
|
|
/* 0=DTE device */
|
1871 |
|
|
#define CR_1000T_MS_VALUE 0x0800 /* 1=Configure PHY as Master */
|
1872 |
|
|
/* 0=Configure PHY as Slave */
|
1873 |
|
|
#define CR_1000T_MS_ENABLE 0x1000 /* 1=Master/Slave manual config value */
|
1874 |
|
|
/* 0=Automatic Master/Slave config */
|
1875 |
|
|
#define CR_1000T_TEST_MODE_NORMAL 0x0000 /* Normal Operation */
|
1876 |
|
|
#define CR_1000T_TEST_MODE_1 0x2000 /* Transmit Waveform test */
|
1877 |
|
|
#define CR_1000T_TEST_MODE_2 0x4000 /* Master Transmit Jitter test */
|
1878 |
|
|
#define CR_1000T_TEST_MODE_3 0x6000 /* Slave Transmit Jitter test */
|
1879 |
|
|
#define CR_1000T_TEST_MODE_4 0x8000 /* Transmitter Distortion test */
|
1880 |
|
|
|
1881 |
|
|
/* 1000BASE-T Status Register */
|
1882 |
|
|
#define SR_1000T_IDLE_ERROR_CNT 0x00FF /* Num idle errors since last read */
|
1883 |
|
|
#define SR_1000T_ASYM_PAUSE_DIR 0x0100 /* LP asymmetric pause direction bit */
|
1884 |
|
|
#define SR_1000T_LP_HD_CAPS 0x0400 /* LP is 1000T HD capable */
|
1885 |
|
|
#define SR_1000T_LP_FD_CAPS 0x0800 /* LP is 1000T FD capable */
|
1886 |
|
|
#define SR_1000T_REMOTE_RX_STATUS 0x1000 /* Remote receiver OK */
|
1887 |
|
|
#define SR_1000T_LOCAL_RX_STATUS 0x2000 /* Local receiver OK */
|
1888 |
|
|
#define SR_1000T_MS_CONFIG_RES 0x4000 /* 1=Local TX is Master, 0=Slave */
|
1889 |
|
|
#define SR_1000T_MS_CONFIG_FAULT 0x8000 /* Master/Slave config fault */
|
1890 |
|
|
#define SR_1000T_REMOTE_RX_STATUS_SHIFT 12
|
1891 |
|
|
#define SR_1000T_LOCAL_RX_STATUS_SHIFT 13
|
1892 |
|
|
#define SR_1000T_PHY_EXCESSIVE_IDLE_ERR_COUNT 5
|
1893 |
|
|
#define FFE_IDLE_ERR_COUNT_TIMEOUT_20 20
|
1894 |
|
|
#define FFE_IDLE_ERR_COUNT_TIMEOUT_100 100
|
1895 |
|
|
|
1896 |
|
|
/* Extended Status Register */
|
1897 |
|
|
#define IEEE_ESR_1000T_HD_CAPS 0x1000 /* 1000T HD capable */
|
1898 |
|
|
#define IEEE_ESR_1000T_FD_CAPS 0x2000 /* 1000T FD capable */
|
1899 |
|
|
#define IEEE_ESR_1000X_HD_CAPS 0x4000 /* 1000X HD capable */
|
1900 |
|
|
#define IEEE_ESR_1000X_FD_CAPS 0x8000 /* 1000X FD capable */
|
1901 |
|
|
|
1902 |
|
|
#define PHY_TX_POLARITY_MASK 0x0100 /* register 10h bit 8 (polarity bit) */
|
1903 |
|
|
#define PHY_TX_NORMAL_POLARITY 0 /* register 10h bit 8 (normal polarity) */
|
1904 |
|
|
|
1905 |
|
|
#define AUTO_POLARITY_DISABLE 0x0010 /* register 11h bit 4 */
|
1906 |
|
|
/* (0=enable, 1=disable) */
|
1907 |
|
|
|
1908 |
|
|
/* M88E1000 PHY Specific Control Register */
|
1909 |
|
|
#define M88E1000_PSCR_JABBER_DISABLE 0x0001 /* 1=Jabber Function disabled */
|
1910 |
|
|
#define M88E1000_PSCR_POLARITY_REVERSAL 0x0002 /* 1=Polarity Reversal enabled */
|
1911 |
|
|
#define M88E1000_PSCR_SQE_TEST 0x0004 /* 1=SQE Test enabled */
|
1912 |
|
|
#define M88E1000_PSCR_CLK125_DISABLE 0x0010 /* 1=CLK125 low,
|
1913 |
|
|
* 0=CLK125 toggling
|
1914 |
|
|
*/
|
1915 |
|
|
#define M88E1000_PSCR_MDI_MANUAL_MODE 0x0000 /* MDI Crossover Mode bits 6:5 */
|
1916 |
|
|
/* Manual MDI configuration */
|
1917 |
|
|
#define M88E1000_PSCR_MDIX_MANUAL_MODE 0x0020 /* Manual MDIX configuration */
|
1918 |
|
|
#define M88E1000_PSCR_AUTO_X_1000T 0x0040 /* 1000BASE-T: Auto crossover,
|
1919 |
|
|
* 100BASE-TX/10BASE-T:
|
1920 |
|
|
* MDI Mode
|
1921 |
|
|
*/
|
1922 |
|
|
#define M88E1000_PSCR_AUTO_X_MODE 0x0060 /* Auto crossover enabled
|
1923 |
|
|
* all speeds.
|
1924 |
|
|
*/
|
1925 |
|
|
#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE 0x0080
|
1926 |
|
|
/* 1=Enable Extended 10BASE-T distance
|
1927 |
|
|
* (Lower 10BASE-T RX Threshold)
|
1928 |
|
|
* 0=Normal 10BASE-T RX Threshold */
|
1929 |
|
|
#define M88E1000_PSCR_MII_5BIT_ENABLE 0x0100
|
1930 |
|
|
/* 1=5-Bit interface in 100BASE-TX
|
1931 |
|
|
* 0=MII interface in 100BASE-TX */
|
1932 |
|
|
#define M88E1000_PSCR_SCRAMBLER_DISABLE 0x0200 /* 1=Scrambler disable */
|
1933 |
|
|
#define M88E1000_PSCR_FORCE_LINK_GOOD 0x0400 /* 1=Force link good */
|
1934 |
|
|
#define M88E1000_PSCR_ASSERT_CRS_ON_TX 0x0800 /* 1=Assert CRS on Transmit */
|
1935 |
|
|
|
1936 |
|
|
#define M88E1000_PSCR_POLARITY_REVERSAL_SHIFT 1
|
1937 |
|
|
#define M88E1000_PSCR_AUTO_X_MODE_SHIFT 5
|
1938 |
|
|
#define M88E1000_PSCR_10BT_EXT_DIST_ENABLE_SHIFT 7
|
1939 |
|
|
|
1940 |
|
|
/* M88E1000 PHY Specific Status Register */
|
1941 |
|
|
#define M88E1000_PSSR_JABBER 0x0001 /* 1=Jabber */
|
1942 |
|
|
#define M88E1000_PSSR_REV_POLARITY 0x0002 /* 1=Polarity reversed */
|
1943 |
|
|
#define M88E1000_PSSR_DOWNSHIFT 0x0020 /* 1=Downshifted */
|
1944 |
|
|
#define M88E1000_PSSR_MDIX 0x0040 /* 1=MDIX; 0=MDI */
|
1945 |
|
|
#define M88E1000_PSSR_CABLE_LENGTH 0x0380 /* 0=<50M;1=50-80M;2=80-110M;
|
1946 |
|
|
* 3=110-140M;4=>140M */
|
1947 |
|
|
#define M88E1000_PSSR_LINK 0x0400 /* 1=Link up, 0=Link down */
|
1948 |
|
|
#define M88E1000_PSSR_SPD_DPLX_RESOLVED 0x0800 /* 1=Speed & Duplex resolved */
|
1949 |
|
|
#define M88E1000_PSSR_PAGE_RCVD 0x1000 /* 1=Page received */
|
1950 |
|
|
#define M88E1000_PSSR_DPLX 0x2000 /* 1=Duplex 0=Half Duplex */
|
1951 |
|
|
#define M88E1000_PSSR_SPEED 0xC000 /* Speed, bits 14:15 */
|
1952 |
|
|
#define M88E1000_PSSR_10MBS 0x0000 /* 00=10Mbs */
|
1953 |
|
|
#define M88E1000_PSSR_100MBS 0x4000 /* 01=100Mbs */
|
1954 |
|
|
#define M88E1000_PSSR_1000MBS 0x8000 /* 10=1000Mbs */
|
1955 |
|
|
|
1956 |
|
|
#define M88E1000_PSSR_REV_POLARITY_SHIFT 1
|
1957 |
|
|
#define M88E1000_PSSR_DOWNSHIFT_SHIFT 5
|
1958 |
|
|
#define M88E1000_PSSR_MDIX_SHIFT 6
|
1959 |
|
|
#define M88E1000_PSSR_CABLE_LENGTH_SHIFT 7
|
1960 |
|
|
|
1961 |
|
|
/* M88E1000 Extended PHY Specific Control Register */
|
1962 |
|
|
#define M88E1000_EPSCR_FIBER_LOOPBACK 0x4000 /* 1=Fiber loopback */
|
1963 |
|
|
#define M88E1000_EPSCR_DOWN_NO_IDLE 0x8000 /* 1=Lost lock detect enabled.
|
1964 |
|
|
* Will assert lost lock and bring
|
1965 |
|
|
* link down if idle not seen
|
1966 |
|
|
* within 1ms in 1000BASE-T
|
1967 |
|
|
*/
|
1968 |
|
|
/* Number of times we will attempt to autonegotiate before downshifting if we
|
1969 |
|
|
* are the master */
|
1970 |
|
|
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_MASK 0x0C00
|
1971 |
|
|
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_1X 0x0000
|
1972 |
|
|
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_2X 0x0400
|
1973 |
|
|
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_3X 0x0800
|
1974 |
|
|
#define M88E1000_EPSCR_MASTER_DOWNSHIFT_4X 0x0C00
|
1975 |
|
|
/* Number of times we will attempt to autonegotiate before downshifting if we
|
1976 |
|
|
* are the slave */
|
1977 |
|
|
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_MASK 0x0300
|
1978 |
|
|
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_DIS 0x0000
|
1979 |
|
|
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_1X 0x0100
|
1980 |
|
|
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_2X 0x0200
|
1981 |
|
|
#define M88E1000_EPSCR_SLAVE_DOWNSHIFT_3X 0x0300
|
1982 |
|
|
#define M88E1000_EPSCR_TX_CLK_2_5 0x0060 /* 2.5 MHz TX_CLK */
|
1983 |
|
|
#define M88E1000_EPSCR_TX_CLK_25 0x0070 /* 25 MHz TX_CLK */
|
1984 |
|
|
#define M88E1000_EPSCR_TX_CLK_0 0x0000 /* NO TX_CLK */
|
1985 |
|
|
|
1986 |
|
|
/* IGP01E1000 Specific Port Config Register - R/W */
|
1987 |
|
|
#define IGP01E1000_PSCFR_AUTO_MDIX_PAR_DETECT 0x0010
|
1988 |
|
|
#define IGP01E1000_PSCFR_PRE_EN 0x0020
|
1989 |
|
|
#define IGP01E1000_PSCFR_SMART_SPEED 0x0080
|
1990 |
|
|
#define IGP01E1000_PSCFR_DISABLE_TPLOOPBACK 0x0100
|
1991 |
|
|
#define IGP01E1000_PSCFR_DISABLE_JABBER 0x0400
|
1992 |
|
|
#define IGP01E1000_PSCFR_DISABLE_TRANSMIT 0x2000
|
1993 |
|
|
|
1994 |
|
|
/* IGP01E1000 Specific Port Status Register - R/O */
|
1995 |
|
|
#define IGP01E1000_PSSR_AUTONEG_FAILED 0x0001 /* RO LH SC */
|
1996 |
|
|
#define IGP01E1000_PSSR_POLARITY_REVERSED 0x0002
|
1997 |
|
|
#define IGP01E1000_PSSR_CABLE_LENGTH 0x007C
|
1998 |
|
|
#define IGP01E1000_PSSR_FULL_DUPLEX 0x0200
|
1999 |
|
|
#define IGP01E1000_PSSR_LINK_UP 0x0400
|
2000 |
|
|
#define IGP01E1000_PSSR_MDIX 0x0800
|
2001 |
|
|
#define IGP01E1000_PSSR_SPEED_MASK 0xC000 /* speed bits mask */
|
2002 |
|
|
#define IGP01E1000_PSSR_SPEED_10MBPS 0x4000
|
2003 |
|
|
#define IGP01E1000_PSSR_SPEED_100MBPS 0x8000
|
2004 |
|
|
#define IGP01E1000_PSSR_SPEED_1000MBPS 0xC000
|
2005 |
|
|
#define IGP01E1000_PSSR_CABLE_LENGTH_SHIFT 0x0002 /* shift right 2 */
|
2006 |
|
|
#define IGP01E1000_PSSR_MDIX_SHIFT 0x000B /* shift right 11 */
|
2007 |
|
|
|
2008 |
|
|
/* IGP01E1000 Specific Port Control Register - R/W */
|
2009 |
|
|
#define IGP01E1000_PSCR_TP_LOOPBACK 0x0001
|
2010 |
|
|
#define IGP01E1000_PSCR_CORRECT_NC_SCMBLR 0x0200
|
2011 |
|
|
#define IGP01E1000_PSCR_TEN_CRS_SELECT 0x0400
|
2012 |
|
|
#define IGP01E1000_PSCR_FLIP_CHIP 0x0800
|
2013 |
|
|
#define IGP01E1000_PSCR_AUTO_MDIX 0x1000
|
2014 |
|
|
#define IGP01E1000_PSCR_FORCE_MDI_MDIX 0x2000 /* 0-MDI, 1-MDIX */
|
2015 |
|
|
|
2016 |
|
|
/* IGP01E1000 Specific Port Link Health Register */
|
2017 |
|
|
#define IGP01E1000_PLHR_SS_DOWNGRADE 0x8000
|
2018 |
|
|
#define IGP01E1000_PLHR_GIG_SCRAMBLER_ERROR 0x4000
|
2019 |
|
|
#define IGP01E1000_PLHR_GIG_REM_RCVR_NOK 0x0800 /* LH */
|
2020 |
|
|
#define IGP01E1000_PLHR_IDLE_ERROR_CNT_OFLOW 0x0400 /* LH */
|
2021 |
|
|
#define IGP01E1000_PLHR_DATA_ERR_1 0x0200 /* LH */
|
2022 |
|
|
#define IGP01E1000_PLHR_DATA_ERR_0 0x0100
|
2023 |
|
|
#define IGP01E1000_PLHR_AUTONEG_FAULT 0x0010
|
2024 |
|
|
#define IGP01E1000_PLHR_AUTONEG_ACTIVE 0x0008
|
2025 |
|
|
#define IGP01E1000_PLHR_VALID_CHANNEL_D 0x0004
|
2026 |
|
|
#define IGP01E1000_PLHR_VALID_CHANNEL_C 0x0002
|
2027 |
|
|
#define IGP01E1000_PLHR_VALID_CHANNEL_B 0x0001
|
2028 |
|
|
#define IGP01E1000_PLHR_VALID_CHANNEL_A 0x0000
|
2029 |
|
|
|
2030 |
|
|
/* IGP01E1000 Channel Quality Register */
|
2031 |
|
|
#define IGP01E1000_MSE_CHANNEL_D 0x000F
|
2032 |
|
|
#define IGP01E1000_MSE_CHANNEL_C 0x00F0
|
2033 |
|
|
#define IGP01E1000_MSE_CHANNEL_B 0x0F00
|
2034 |
|
|
#define IGP01E1000_MSE_CHANNEL_A 0xF000
|
2035 |
|
|
|
2036 |
|
|
/* IGP01E1000 DSP reset macros */
|
2037 |
|
|
#define DSP_RESET_ENABLE 0x0
|
2038 |
|
|
#define DSP_RESET_DISABLE 0x2
|
2039 |
|
|
#define E1000_MAX_DSP_RESETS 10
|
2040 |
|
|
|
2041 |
|
|
/* IGP01E1000 AGC Registers */
|
2042 |
|
|
|
2043 |
|
|
#define IGP01E1000_AGC_LENGTH_SHIFT 7 /* Coarse - 13:11, Fine - 10:7 */
|
2044 |
|
|
|
2045 |
|
|
/* 7 bits (3 Coarse + 4 Fine) --> 128 optional values */
|
2046 |
|
|
#define IGP01E1000_AGC_LENGTH_TABLE_SIZE 128
|
2047 |
|
|
|
2048 |
|
|
/* The precision of the length is +/- 10 meters */
|
2049 |
|
|
#define IGP01E1000_AGC_RANGE 10
|
2050 |
|
|
|
2051 |
|
|
/* IGP01E1000 PCS Initialization register */
|
2052 |
|
|
/* bits 3:6 in the PCS registers stores the channels polarity */
|
2053 |
|
|
#define IGP01E1000_PHY_POLARITY_MASK 0x0078
|
2054 |
|
|
|
2055 |
|
|
/* IGP01E1000 GMII FIFO Register */
|
2056 |
|
|
#define IGP01E1000_GMII_FLEX_SPD 0x10 /* Enable flexible speed
|
2057 |
|
|
* on Link-Up */
|
2058 |
|
|
#define IGP01E1000_GMII_SPD 0x20 /* Enable SPD */
|
2059 |
|
|
|
2060 |
|
|
/* IGP01E1000 Analog Register */
|
2061 |
|
|
#define IGP01E1000_ANALOG_SPARE_FUSE_STATUS 0x20D1
|
2062 |
|
|
#define IGP01E1000_ANALOG_FUSE_STATUS 0x20D0
|
2063 |
|
|
#define IGP01E1000_ANALOG_FUSE_CONTROL 0x20DC
|
2064 |
|
|
#define IGP01E1000_ANALOG_FUSE_BYPASS 0x20DE
|
2065 |
|
|
|
2066 |
|
|
#define IGP01E1000_ANALOG_FUSE_POLY_MASK 0xF000
|
2067 |
|
|
#define IGP01E1000_ANALOG_FUSE_FINE_MASK 0x0F80
|
2068 |
|
|
#define IGP01E1000_ANALOG_FUSE_COARSE_MASK 0x0070
|
2069 |
|
|
#define IGP01E1000_ANALOG_SPARE_FUSE_ENABLED 0x0100
|
2070 |
|
|
#define IGP01E1000_ANALOG_FUSE_ENABLE_SW_CONTROL 0x0002
|
2071 |
|
|
|
2072 |
|
|
#define IGP01E1000_ANALOG_FUSE_COARSE_THRESH 0x0040
|
2073 |
|
|
#define IGP01E1000_ANALOG_FUSE_COARSE_10 0x0010
|
2074 |
|
|
#define IGP01E1000_ANALOG_FUSE_FINE_1 0x0080
|
2075 |
|
|
#define IGP01E1000_ANALOG_FUSE_FINE_10 0x0500
|
2076 |
|
|
|
2077 |
|
|
/* Bit definitions for valid PHY IDs. */
|
2078 |
|
|
#define M88E1000_E_PHY_ID 0x01410C50
|
2079 |
|
|
#define M88E1000_I_PHY_ID 0x01410C30
|
2080 |
|
|
#define M88E1011_I_PHY_ID 0x01410C20
|
2081 |
|
|
#define IGP01E1000_I_PHY_ID 0x02A80380
|
2082 |
|
|
#define M88E1000_12_PHY_ID M88E1000_E_PHY_ID
|
2083 |
|
|
#define M88E1000_14_PHY_ID M88E1000_E_PHY_ID
|
2084 |
|
|
#define M88E1011_I_REV_4 0x04
|
2085 |
|
|
|
2086 |
|
|
/* Miscellaneous PHY bit definitions. */
|
2087 |
|
|
#define PHY_PREAMBLE 0xFFFFFFFF
|
2088 |
|
|
#define PHY_SOF 0x01
|
2089 |
|
|
#define PHY_OP_READ 0x02
|
2090 |
|
|
#define PHY_OP_WRITE 0x01
|
2091 |
|
|
#define PHY_TURNAROUND 0x02
|
2092 |
|
|
#define PHY_PREAMBLE_SIZE 32
|
2093 |
|
|
#define MII_CR_SPEED_1000 0x0040
|
2094 |
|
|
#define MII_CR_SPEED_100 0x2000
|
2095 |
|
|
#define MII_CR_SPEED_10 0x0000
|
2096 |
|
|
#define E1000_PHY_ADDRESS 0x01
|
2097 |
|
|
#define PHY_AUTO_NEG_TIME 45 /* 4.5 Seconds */
|
2098 |
|
|
#define PHY_FORCE_TIME 20 /* 2.0 Seconds */
|
2099 |
|
|
#define PHY_REVISION_MASK 0xFFFFFFF0
|
2100 |
|
|
#define DEVICE_SPEED_MASK 0x00000300 /* Device Ctrl Reg Speed Mask */
|
2101 |
|
|
#define REG4_SPEED_MASK 0x01E0
|
2102 |
|
|
#define REG9_SPEED_MASK 0x0300
|
2103 |
|
|
#define ADVERTISE_10_HALF 0x0001
|
2104 |
|
|
#define ADVERTISE_10_FULL 0x0002
|
2105 |
|
|
#define ADVERTISE_100_HALF 0x0004
|
2106 |
|
|
#define ADVERTISE_100_FULL 0x0008
|
2107 |
|
|
#define ADVERTISE_1000_HALF 0x0010
|
2108 |
|
|
#define ADVERTISE_1000_FULL 0x0020
|
2109 |
|
|
#define AUTONEG_ADVERTISE_SPEED_DEFAULT 0x002F /* Everything but 1000-Half */
|
2110 |
|
|
#define AUTONEG_ADVERTISE_10_100_ALL 0x000F /* All 10/100 speeds*/
|
2111 |
|
|
#define AUTONEG_ADVERTISE_10_ALL 0x0003 /* 10Mbps Full & Half speeds*/
|
2112 |
|
|
|
2113 |
|
|
#endif /* _E1000_HW_H_ */
|