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1275 |
phoenix |
/*
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* mace.h - definitions for the registers in the Am79C940 MACE
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* (Medium Access Control for Ethernet) controller.
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*
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* Copyright (C) 1996 Paul Mackerras.
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*
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* This program is free software; you can redistribute it and/or
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* modify it under the terms of the GNU General Public License
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* as published by the Free Software Foundation; either version
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* 2 of the License, or (at your option) any later version.
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*/
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#define REG(x) volatile unsigned char x; char x ## _pad[15]
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struct mace {
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REG(rcvfifo); /* receive FIFO */
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REG(xmtfifo); /* transmit FIFO */
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REG(xmtfc); /* transmit frame control */
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REG(xmtfs); /* transmit frame status */
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REG(xmtrc); /* transmit retry count */
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REG(rcvfc); /* receive frame control */
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REG(rcvfs); /* receive frame status (4 bytes) */
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REG(fifofc); /* FIFO frame count */
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REG(ir); /* interrupt register */
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REG(imr); /* interrupt mask register */
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REG(pr); /* poll register */
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REG(biucc); /* bus interface unit config control */
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REG(fifocc); /* FIFO configuration control */
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REG(maccc); /* medium access control config control */
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REG(plscc); /* phys layer signalling config control */
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REG(phycc); /* physical configuration control */
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REG(chipid_lo); /* chip ID, lsb */
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REG(chipid_hi); /* chip ID, msb */
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REG(iac); /* internal address config */
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REG(reg19);
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REG(ladrf); /* logical address filter (8 bytes) */
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REG(padr); /* physical address (6 bytes) */
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REG(reg22);
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REG(reg23);
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REG(mpc); /* missed packet count (clears when read) */
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REG(reg25);
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REG(rntpc); /* runt packet count (clears when read) */
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REG(rcvcc); /* recv collision count (clears when read) */
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REG(reg28);
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REG(utr); /* user test reg */
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REG(reg30);
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REG(reg31);
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};
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/* Bits in XMTFC */
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#define DRTRY 0x80 /* don't retry transmission after collision */
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#define DXMTFCS 0x08 /* don't append FCS to transmitted frame */
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#define AUTO_PAD_XMIT 0x01 /* auto-pad short packets on transmission */
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/* Bits in XMTFS: only valid when XMTSV is set in PR and XMTFS */
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#define XMTSV 0x80 /* transmit status (i.e. XMTFS) valid */
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#define UFLO 0x40 /* underflow - xmit fifo ran dry */
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#define LCOL 0x20 /* late collision (transmission aborted) */
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#define MORE 0x10 /* 2 or more retries needed to xmit frame */
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#define ONE 0x08 /* 1 retry needed to xmit frame */
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#define DEFER 0x04 /* MACE had to defer xmission (enet busy) */
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#define LCAR 0x02 /* loss of carrier (transmission aborted) */
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#define RTRY 0x01 /* too many retries (transmission aborted) */
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/* Bits in XMTRC: only valid when XMTSV is set in PR (and XMTFS) */
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#define EXDEF 0x80 /* had to defer for excessive time */
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#define RETRY_MASK 0x0f /* number of retries (0 - 15) */
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/* Bits in RCVFC */
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#define LLRCV 0x08 /* low latency receive: early DMA request */
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#define M_RBAR 0x04 /* sets function of EAM/R pin */
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#define AUTO_STRIP_RCV 0x01 /* auto-strip short LLC frames on recv */
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/*
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* Bits in RCVFS. After a frame is received, four bytes of status
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* are automatically read from this register and appended to the frame
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* data in memory. These are:
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* Byte 0 and 1: message byte count and frame status
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* Byte 2: runt packet count
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* Byte 3: receive collision count
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*/
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#define RS_OFLO 0x8000 /* receive FIFO overflowed */
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#define RS_CLSN 0x4000 /* received frame suffered (late) collision */
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#define RS_FRAMERR 0x2000 /* framing error flag */
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#define RS_FCSERR 0x1000 /* frame had FCS error */
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#define RS_COUNT 0x0fff /* mask for byte count field */
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/* Bits (fields) in FIFOFC */
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#define RCVFC_SH 4 /* receive frame count in FIFO */
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#define RCVFC_MASK 0x0f
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#define XMTFC_SH 0 /* transmit frame count in FIFO */
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#define XMTFC_MASK 0x0f
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/*
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* Bits in IR and IMR. The IR clears itself when read.
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* Setting a bit in the IMR will disable the corresponding interrupt.
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*/
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#define JABBER 0x80 /* jabber error - 10baseT xmission too long */
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#define BABBLE 0x40 /* babble - xmitter xmitting for too long */
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#define CERR 0x20 /* collision err - no SQE test (heartbeat) */
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#define RCVCCO 0x10 /* RCVCC overflow */
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#define RNTPCO 0x08 /* RNTPC overflow */
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#define MPCO 0x04 /* MPC overflow */
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#define RCVINT 0x02 /* receive interrupt */
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#define XMTINT 0x01 /* transmitter interrupt */
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/* Bits in PR */
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#define XMTSV 0x80 /* XMTFS valid (same as in XMTFS) */
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#define TDTREQ 0x40 /* set when xmit fifo is requesting data */
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#define RDTREQ 0x20 /* set when recv fifo requests data xfer */
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/* Bits in BIUCC */
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#define BSWP 0x40 /* byte swap, i.e. big-endian bus */
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#define XMTSP_4 0x00 /* start xmitting when 4 bytes in FIFO */
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#define XMTSP_16 0x10 /* start xmitting when 16 bytes in FIFO */
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#define XMTSP_64 0x20 /* start xmitting when 64 bytes in FIFO */
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#define XMTSP_112 0x30 /* start xmitting when 112 bytes in FIFO */
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#define SWRST 0x01 /* software reset */
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/* Bits in FIFOCC */
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#define XMTFW_8 0x00 /* xmit fifo watermark = 8 words free */
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#define XMTFW_16 0x40 /* 16 words free */
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#define XMTFW_32 0x80 /* 32 words free */
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#define RCVFW_16 0x00 /* recv fifo watermark = 16 bytes avail */
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#define RCVFW_32 0x10 /* 32 bytes avail */
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#define RCVFW_64 0x20 /* 64 bytes avail */
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#define XMTFWU 0x08 /* xmit fifo watermark update enable */
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#define RCVFWU 0x04 /* recv fifo watermark update enable */
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#define XMTBRST 0x02 /* enable transmit burst mode */
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#define RCVBRST 0x01 /* enable receive burst mode */
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/* Bits in MACCC */
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#define PROM 0x80 /* promiscuous mode */
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#define DXMT2PD 0x40 /* disable xmit two-part deferral algorithm */
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#define EMBA 0x20 /* enable modified backoff algorithm */
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#define DRCVPA 0x08 /* disable receiving physical address */
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#define DRCVBC 0x04 /* disable receiving broadcasts */
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#define ENXMT 0x02 /* enable transmitter */
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#define ENRCV 0x01 /* enable receiver */
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/* Bits in PLSCC */
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#define XMTSEL 0x08 /* select DO+/DO- state when idle */
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#define PORTSEL_AUI 0x00 /* select AUI port */
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#define PORTSEL_10T 0x02 /* select 10Base-T port */
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#define PORTSEL_DAI 0x04 /* select DAI port */
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#define PORTSEL_GPSI 0x06 /* select GPSI port */
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#define ENPLSIO 0x01 /* enable optional PLS I/O pins */
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/* Bits in PHYCC */
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#define LNKFL 0x80 /* reports 10Base-T link failure */
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#define DLNKTST 0x40 /* disable 10Base-T link test */
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#define REVPOL 0x20 /* 10Base-T receiver polarity reversed */
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#define DAPC 0x10 /* disable auto receiver polarity correction */
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#define LRT 0x08 /* low receive threshold for long links */
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#define ASEL 0x04 /* auto-select AUI or 10Base-T port */
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#define RWAKE 0x02 /* remote wake function */
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#define AWAKE 0x01 /* auto wake function */
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/* Bits in IAC */
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#define ADDRCHG 0x80 /* request address change */
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#define PHYADDR 0x04 /* access physical address */
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#define LOGADDR 0x02 /* access multicast filter */
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/* Bits in UTR */
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#define RTRE 0x80 /* reserved test register enable. DON'T SET. */
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#define RTRD 0x40 /* reserved test register disable. Sticky */
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#define RPAC 0x20 /* accept runt packets */
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#define FCOLL 0x10 /* force collision */
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#define RCVFCSE 0x08 /* receive FCS enable */
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#define LOOP_NONE 0x00 /* no loopback */
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#define LOOP_EXT 0x02 /* external loopback */
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#define LOOP_INT 0x04 /* internal loopback, excludes MENDEC */
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#define LOOP_MENDEC 0x06 /* internal loopback, includes MENDEC */
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