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/* xircom_tulip_cb.c: A Xircom CBE-100 ethernet driver for Linux. */

/*

        Written/copyright 1994-1999 by Donald Becker.

        This software may be used and distributed according to the terms

        of the GNU General Public License, incorporated herein by reference.

        The author may be reached as becker@scyld.com, or C/O

        Scyld Computing Corporation

        410 Severn Ave., Suite 210

        Annapolis MD 21403

        -----------------------------------------------------------

        Linux kernel-specific changes:

        LK1.0 (Ion Badulescu)

        - Major cleanup

        - Use 2.4 PCI API

        - Support ethtool

        - Rewrite perfect filter/hash code

        - Use interrupts for media changes

        LK1.1 (Ion Badulescu)

        - Disallow negotiation of unsupported full-duplex modes

*/

#define DRV_NAME        "xircom_tulip_cb"

#define DRV_VERSION     "0.91+LK1.1"

#define DRV_RELDATE     "October 11, 2001"

#define CARDBUS 1

/* A few user-configurable values. */

/* Maximum events (Rx packets, etc.) to handle at each interrupt. */

static int max_interrupt_work = 25;

#define MAX_UNITS 4

/* Used to pass the full-duplex flag, etc. */

static int full_duplex[MAX_UNITS];

static int options[MAX_UNITS];

static int mtu[MAX_UNITS];                      /* Jumbo MTU for interfaces. */

/* Keep the ring sizes a power of two for efficiency.

   Making the Tx ring too large decreases the effectiveness of channel

   bonding and packet priority.

   There are no ill effects from too-large receive rings. */

#define TX_RING_SIZE    16

#define RX_RING_SIZE    32

/* Set the copy breakpoint for the copy-only-tiny-buffer Rx structure. */

#ifdef __alpha__

static int rx_copybreak = 1518;

#else

static int rx_copybreak = 100;

#endif

/*

  Set the bus performance register.

        Typical: Set 16 longword cache alignment, no burst limit.

        Cache alignment bits 15:14           Burst length 13:8

                0000    No alignment  0x00000000 unlimited              0800 8 longwords

                4000    8  longwords            0100 1 longword         1000 16 longwords

                8000    16 longwords            0200 2 longwords        2000 32 longwords

                C000    32  longwords           0400 4 longwords

        Warning: many older 486 systems are broken and require setting 0x00A04800

           8 longword cache alignment, 8 longword burst.

        ToDo: Non-Intel setting could be better.

*/

#if defined(__alpha__) || defined(__ia64__) || defined(__x86_64__)

static int csr0 = 0x01A00000 | 0xE000;

#elif defined(__powerpc__)

static int csr0 = 0x01B00000 | 0x8000;

#elif defined(__sparc__)

static int csr0 = 0x01B00080 | 0x8000;

#elif defined(__i386__)

static int csr0 = 0x01A00000 | 0x8000;

#else

#warning Processor architecture undefined!

static int csr0 = 0x00A00000 | 0x4800;

#endif

/* Operational parameters that usually are not changed. */

/* Time in jiffies before concluding the transmitter is hung. */

#define TX_TIMEOUT              (4 * HZ)

#define PKT_BUF_SZ              1536                    /* Size of each temporary Rx buffer.*/

#define PKT_SETUP_SZ            192                     /* Size of the setup frame */

/* PCI registers */

#define PCI_POWERMGMT   0x40

#include <linux/config.h>

#include <linux/module.h>

#include <linux/kernel.h>

#include <linux/pci.h>

#include <linux/netdevice.h>

#include <linux/etherdevice.h>

#include <linux/delay.h>

#include <linux/init.h>

#include <linux/mii.h>

#include <linux/ethtool.h>

#include <linux/crc32.h>

#include <asm/io.h>

#include <asm/processor.h>      /* Processor type for cache alignment. */

#include <asm/uaccess.h>

/* These identify the driver base version and may not be removed. */

static char version[] __devinitdata =

KERN_INFO DRV_NAME ".c derived from tulip.c:v0.91 4/14/99 becker@scyld.com\n"

KERN_INFO " unofficial 2.4.x kernel port, version " DRV_VERSION ", " DRV_RELDATE "\n";

MODULE_AUTHOR("Donald Becker <becker@scyld.com>");

MODULE_DESCRIPTION("Xircom CBE-100 ethernet driver");

MODULE_LICENSE("GPL v2");

MODULE_PARM(debug, "i");

MODULE_PARM(max_interrupt_work, "i");

MODULE_PARM(rx_copybreak, "i");

MODULE_PARM(csr0, "i");

MODULE_PARM(options, "1-" __MODULE_STRING(MAX_UNITS) "i");

MODULE_PARM(full_duplex, "1-" __MODULE_STRING(MAX_UNITS) "i");

#define RUN_AT(x) (jiffies + (x))

#define xircom_debug debug

#ifdef XIRCOM_DEBUG

static int xircom_debug = XIRCOM_DEBUG;

#else

static int xircom_debug = 1;

#endif

/*

                                Theory of Operation

I. Board Compatibility

This device driver was forked from the driver for the DECchip "Tulip",

Digital's single-chip ethernet controllers for PCI.  It supports Xircom's

almost-Tulip-compatible CBE-100 CardBus adapters.

II. Board-specific settings

PCI bus devices are configured by the system at boot time, so no jumpers

need to be set on the board.  The system BIOS preferably should assign the

PCI INTA signal to an otherwise unused system IRQ line.

III. Driver operation

IIIa. Ring buffers

The Xircom can use either ring buffers or lists of Tx and Rx descriptors.

This driver uses statically allocated rings of Rx and Tx descriptors, set at

compile time by RX/TX_RING_SIZE.  This version of the driver allocates skbuffs

for the Rx ring buffers at open() time and passes the skb->data field to the

Xircom as receive data buffers.  When an incoming frame is less than

RX_COPYBREAK bytes long, a fresh skbuff is allocated and the frame is

copied to the new skbuff.  When the incoming frame is larger, the skbuff is

passed directly up the protocol stack and replaced by a newly allocated

skbuff.

The RX_COPYBREAK value is chosen to trade-off the memory wasted by

using a full-sized skbuff for small frames vs. the copying costs of larger

frames.  For small frames the copying cost is negligible (esp. considering

that we are pre-loading the cache with immediately useful header

information).  For large frames the copying cost is non-trivial, and the

larger copy might flush the cache of useful data.  A subtle aspect of this

choice is that the Xircom only receives into longword aligned buffers, thus

the IP header at offset 14 isn't longword aligned for further processing.

Copied frames are put into the new skbuff at an offset of "+2", thus copying

has the beneficial effect of aligning the IP header and preloading the

cache.

IIIC. Synchronization

The driver runs as two independent, single-threaded flows of control.  One

is the send-packet routine, which enforces single-threaded use by the

dev->tbusy flag.  The other thread is the interrupt handler, which is single

threaded by the hardware and other software.

The send packet thread has partial control over the Tx ring and 'dev->tbusy'

flag.  It sets the tbusy flag whenever it's queuing a Tx packet. If the next

queue slot is empty, it clears the tbusy flag when finished otherwise it sets

the 'tp->tx_full' flag.

The interrupt handler has exclusive control over the Rx ring and records stats

from the Tx ring.  (The Tx-done interrupt can't be selectively turned off, so

we can't avoid the interrupt overhead by having the Tx routine reap the Tx

stats.)  After reaping the stats, it marks the queue entry as empty by setting

the 'base' to zero.      Iff the 'tp->tx_full' flag is set, it clears both the

tx_full and tbusy flags.

IV. Notes

IVb. References

http://cesdis.gsfc.nasa.gov/linux/misc/NWay.html

http://www.digital.com  (search for current 21*4* datasheets and "21X4 SROM")

http://www.national.com/pf/DP/DP83840A.html

IVc. Errata

*/

/* A full-duplex map for media types. */

enum MediaIs {

        MediaIsFD = 1, MediaAlwaysFD=2, MediaIsMII=4, MediaIsFx=8,

        MediaIs100=16};

static const char media_cap[] =

{0,0,0,16,  3,19,16,24,  27,4,7,5, 0,20,23,20 };

/* Offsets to the Command and Status Registers, "CSRs".  All accesses

   must be longword instructions and quadword aligned. */

enum xircom_offsets {

        CSR0=0,    CSR1=0x08, CSR2=0x10, CSR3=0x18, CSR4=0x20, CSR5=0x28,

        CSR6=0x30, CSR7=0x38, CSR8=0x40, CSR9=0x48, CSR10=0x50, CSR11=0x58,

        CSR12=0x60, CSR13=0x68, CSR14=0x70, CSR15=0x78, CSR16=0x04, };

/* The bits in the CSR5 status registers, mostly interrupt sources. */

enum status_bits {

        LinkChange=0x08000000,

        NormalIntr=0x10000, NormalIntrMask=0x00014045,

        AbnormalIntr=0x8000, AbnormalIntrMask=0x0a00a5a2,

        ReservedIntrMask=0xe0001a18,

        EarlyRxIntr=0x4000, BusErrorIntr=0x2000,

        EarlyTxIntr=0x400, RxDied=0x100, RxNoBuf=0x80, RxIntr=0x40,

        TxFIFOUnderflow=0x20, TxNoBuf=0x04, TxDied=0x02, TxIntr=0x01,

};

enum csr0_control_bits {

        EnableMWI=0x01000000, EnableMRL=0x00800000,

        EnableMRM=0x00200000, EqualBusPrio=0x02,

        SoftwareReset=0x01,

};

enum csr6_control_bits {

        ReceiveAllBit=0x40000000, AllMultiBit=0x80, PromiscBit=0x40,

        HashFilterBit=0x01, FullDuplexBit=0x0200,

        TxThresh10=0x400000, TxStoreForw=0x200000,

        TxThreshMask=0xc000, TxThreshShift=14,

        EnableTx=0x2000, EnableRx=0x02,

        ReservedZeroMask=0x8d930134, ReservedOneMask=0x320c0000,

        EnableTxRx=(EnableTx | EnableRx),

};

enum tbl_flag {

        HAS_MII=1, HAS_ACPI=2,

};

static struct xircom_chip_table {

        char *chip_name;

        int valid_intrs;                        /* CSR7 interrupt enable settings */

        int flags;

} xircom_tbl[] = {

  { "Xircom Cardbus Adapter",

        LinkChange | NormalIntr | AbnormalIntr | BusErrorIntr |

        RxDied | RxNoBuf | RxIntr | TxFIFOUnderflow | TxNoBuf | TxDied | TxIntr,

        HAS_MII | HAS_ACPI, },

  { NULL, },

};

/* This matches the table above. */

enum chips {

        X3201_3,

};

/* The Xircom Rx and Tx buffer descriptors. */

struct xircom_rx_desc {

        s32 status;

        s32 length;

        u32 buffer1, buffer2;

};

struct xircom_tx_desc {

        s32 status;

        s32 length;

        u32 buffer1, buffer2;                           /* We use only buffer 1.  */

};

enum tx_desc0_status_bits {

        Tx0DescOwned=0x80000000, Tx0DescError=0x8000, Tx0NoCarrier=0x0800,

        Tx0LateColl=0x0200, Tx0ManyColl=0x0100, Tx0Underflow=0x02,

};

enum tx_desc1_status_bits {

        Tx1ComplIntr=0x80000000, Tx1LastSeg=0x40000000, Tx1FirstSeg=0x20000000,

        Tx1SetupPkt=0x08000000, Tx1DisableCRC=0x04000000, Tx1RingWrap=0x02000000,

        Tx1ChainDesc=0x01000000, Tx1NoPad=0x800000, Tx1HashSetup=0x400000,

        Tx1WholePkt=(Tx1FirstSeg | Tx1LastSeg),

};

enum rx_desc0_status_bits {

        Rx0DescOwned=0x80000000, Rx0DescError=0x8000, Rx0NoSpace=0x4000,

        Rx0Runt=0x0800, Rx0McastPkt=0x0400, Rx0FirstSeg=0x0200, Rx0LastSeg=0x0100,

        Rx0HugeFrame=0x80, Rx0CRCError=0x02,

        Rx0WholePkt=(Rx0FirstSeg | Rx0LastSeg),

};

enum rx_desc1_status_bits {

        Rx1RingWrap=0x02000000, Rx1ChainDesc=0x01000000,

};

struct xircom_private {

        struct xircom_rx_desc rx_ring[RX_RING_SIZE];

        struct xircom_tx_desc tx_ring[TX_RING_SIZE];

        /* The saved address of a sent-in-place packet/buffer, for skfree(). */

        struct sk_buff* tx_skbuff[TX_RING_SIZE];

#ifdef CARDBUS

        /* The X3201-3 requires 4-byte aligned tx bufs */

        struct sk_buff* tx_aligned_skbuff[TX_RING_SIZE];

#endif

        /* The addresses of receive-in-place skbuffs. */

        struct sk_buff* rx_skbuff[RX_RING_SIZE];

        u16 setup_frame[PKT_SETUP_SZ / sizeof(u16)];    /* Pseudo-Tx frame to init address table. */

        int chip_id;

        struct net_device_stats stats;

        unsigned int cur_rx, cur_tx;            /* The next free ring entry */

        unsigned int dirty_rx, dirty_tx;        /* The ring entries to be free()ed. */

        unsigned int tx_full:1;                         /* The Tx queue is full. */

        unsigned int speed100:1;

        unsigned int full_duplex:1;                     /* Full-duplex operation requested. */

        unsigned int autoneg:1;

        unsigned int default_port:4;            /* Last dev->if_port value. */

        unsigned int open:1;

        unsigned int csr0;                                      /* CSR0 setting. */

        unsigned int csr6;                                      /* Current CSR6 control settings. */

        u16 to_advertise;                                       /* NWay capabilities advertised.  */

        u16 advertising[4];

        signed char phys[4], mii_cnt;           /* MII device addresses. */

        int saved_if_port;

        struct pci_dev *pdev;

        spinlock_t lock;

};

static int mdio_read(struct net_device *dev, int phy_id, int location);

static void mdio_write(struct net_device *dev, int phy_id, int location, int value);

static void xircom_up(struct net_device *dev);

static void xircom_down(struct net_device *dev);

static int xircom_open(struct net_device *dev);

static void xircom_tx_timeout(struct net_device *dev);

static void xircom_init_ring(struct net_device *dev);

static int xircom_start_xmit(struct sk_buff *skb, struct net_device *dev);

static int xircom_rx(struct net_device *dev);

static void xircom_interrupt(int irq, void *dev_instance, struct pt_regs *regs);

static int xircom_close(struct net_device *dev);

static struct net_device_stats *xircom_get_stats(struct net_device *dev);

static int xircom_ioctl(struct net_device *dev, struct ifreq *rq, int cmd);

static void set_rx_mode(struct net_device *dev);

static void check_duplex(struct net_device *dev);

/* The Xircom cards are picky about when certain bits in CSR6 can be

   manipulated.  Keith Owens <kaos@ocs.com.au>. */

static void outl_CSR6(u32 newcsr6, long ioaddr)

{

        const int strict_bits =

                TxThresh10 | TxStoreForw | TxThreshMask | EnableTxRx | FullDuplexBit;

    int csr5, csr5_22_20, csr5_19_17, currcsr6, attempts = 200;

    unsigned long flags;

    save_flags(flags);

    cli();

        /* mask out the reserved bits that always read 0 on the Xircom cards */

        newcsr6 &= ~ReservedZeroMask;

        /* or in the reserved bits that always read 1 */

        newcsr6 |= ReservedOneMask;

    currcsr6 = inl(ioaddr + CSR6);

    if (((newcsr6 & strict_bits) == (currcsr6 & strict_bits)) ||

        ((currcsr6 & ~EnableTxRx) == 0)) {

                outl(newcsr6, ioaddr + CSR6);   /* safe */

                restore_flags(flags);

                return;

    }

    /* make sure the transmitter and receiver are stopped first */

    currcsr6 &= ~EnableTxRx;

    while (1) {

                csr5 = inl(ioaddr + CSR5);

                if (csr5 == 0xffffffff)

                        break;  /* cannot read csr5, card removed? */

                csr5_22_20 = csr5 & 0x700000;

                csr5_19_17 = csr5 & 0x0e0000;

                if ((csr5_22_20 == 0 || csr5_22_20 == 0x600000) &&

                        (csr5_19_17 == 0 || csr5_19_17 == 0x80000 || csr5_19_17 == 0xc0000))

                        break;  /* both are stopped or suspended */

                if (!--attempts) {

                        printk(KERN_INFO DRV_NAME ": outl_CSR6 too many attempts,"

                                   "csr5=0x%08x\n", csr5);

                        outl(newcsr6, ioaddr + CSR6);  /* unsafe but do it anyway */

                        restore_flags(flags);

                        return;

                }

                outl(currcsr6, ioaddr + CSR6);

                udelay(1);

    }

    /* now it is safe to change csr6 */

    outl(newcsr6, ioaddr + CSR6);

    restore_flags(flags);

}

static void __devinit read_mac_address(struct net_device *dev)

{

        long ioaddr = dev->base_addr;

        int i, j;

        unsigned char tuple, link, data_id, data_count;

        /* Xircom has its address stored in the CIS;

         * we access it through the boot rom interface for now

         * this might not work, as the CIS is not parsed but I

         * (danilo) use the offset I found on my card's CIS !!!

         *

         * Doug Ledford: I changed this routine around so that it

         * walks the CIS memory space, parsing the config items, and

         * finds the proper lan_node_id tuple and uses the data

         * stored there.

         */

        outl(1 << 12, ioaddr + CSR9); /* enable boot rom access */

        for (i = 0x100; i < 0x1f7; i += link+2) {

                outl(i, ioaddr + CSR10);

                tuple = inl(ioaddr + CSR9) & 0xff;

                outl(i + 1, ioaddr + CSR10);

                link = inl(ioaddr + CSR9) & 0xff;

                outl(i + 2, ioaddr + CSR10);

                data_id = inl(ioaddr + CSR9) & 0xff;

                outl(i + 3, ioaddr + CSR10);

                data_count = inl(ioaddr + CSR9) & 0xff;

                if ( (tuple == 0x22) &&

                         (data_id == 0x04) && (data_count == 0x06) ) {

                        /*

                         * This is it.  We have the data we want.

                         */

                        for (j = 0; j < 6; j++) {

                                outl(i + j + 4, ioaddr + CSR10);

                                dev->dev_addr[j] = inl(ioaddr + CSR9) & 0xff;

                        }

                        break;

                } else if (link == 0) {

                        break;

                }

        }

}

/*

 * locate the MII interfaces and initialize them.

 * we disable full-duplex modes here,

 * because we don't know how to handle them.

 */

static void find_mii_transceivers(struct net_device *dev)

{

        struct xircom_private *tp = dev->priv;

        int phy, phy_idx;

        if (media_cap[tp->default_port] & MediaIsMII) {

                u16 media2advert[] = { 0x20, 0x40, 0x03e0, 0x60, 0x80, 0x100, 0x200 };

                tp->to_advertise = media2advert[tp->default_port - 9];

        } else

                tp->to_advertise =

                        /*ADVERTISE_100BASE4 | ADVERTISE_100FULL |*/ ADVERTISE_100HALF |

                        /*ADVERTISE_10FULL |*/ ADVERTISE_10HALF | ADVERTISE_CSMA;

        /* Find the connected MII xcvrs.

           Doing this in open() would allow detecting external xcvrs later,

           but takes much time. */

        for (phy = 0, phy_idx = 0; phy < 32 && phy_idx < sizeof(tp->phys); phy++) {

                int mii_status = mdio_read(dev, phy, MII_BMSR);

                if ((mii_status & (BMSR_100BASE4 | BMSR_100HALF | BMSR_10HALF)) == BMSR_100BASE4 ||

                        ((mii_status & BMSR_100BASE4) == 0 &&

                         (mii_status & (BMSR_100FULL | BMSR_100HALF | BMSR_10FULL | BMSR_10HALF)) != 0)) {

                        int mii_reg0 = mdio_read(dev, phy, MII_BMCR);

                        int mii_advert = mdio_read(dev, phy, MII_ADVERTISE);

                        int reg4 = ((mii_status >> 6) & tp->to_advertise) | ADVERTISE_CSMA;

                        tp->phys[phy_idx] = phy;

                        tp->advertising[phy_idx++] = reg4;

                        printk(KERN_INFO "%s:  MII transceiver #%d "

                                   "config %4.4x status %4.4x advertising %4.4x.\n",

                                   dev->name, phy, mii_reg0, mii_status, mii_advert);

                }

        }

        tp->mii_cnt = phy_idx;

        if (phy_idx == 0) {

                printk(KERN_INFO "%s: ***WARNING***: No MII transceiver found!\n",

                           dev->name);

                tp->phys[0] = 0;

        }

}

/*

 * To quote Arjan van de Ven:

 *   tranceiver_voodoo() enables the external UTP plug thingy.

 *   it's called voodoo as I stole this code and cannot cross-reference

 *   it with the specification.

 * Actually it seems to go like this:

 * - GPIO2 enables the MII itself so we can talk to it. The MII gets reset

 *   so any prior MII settings are lost.

 * - GPIO0 enables the TP port so the MII can talk to the network.

 * - a software reset will reset both GPIO pins.

 * I also moved the software reset here, because doing it in xircom_up()

 * required enabling the GPIO pins each time, which reset the MII each time.

 * Thus we couldn't control the MII -- which sucks because we don't know

 * how to handle full-duplex modes so we *must* disable them.

 */

static void transceiver_voodoo(struct net_device *dev)

{

        struct xircom_private *tp = dev->priv;

        long ioaddr = dev->base_addr;

        /* Reset the chip, holding bit 0 set at least 50 PCI cycles. */

        outl(SoftwareReset, ioaddr + CSR0);

        udelay(2);

        /* Deassert reset. */

        outl(tp->csr0, ioaddr + CSR0);

        /* Reset the xcvr interface and turn on heartbeat. */

        outl(0x0008, ioaddr + CSR15);

        udelay(5);  /* The delays are Xircom-recommended to give the

                                 * chipset time to reset the actual hardware

                                 * on the PCMCIA card

                                 */

        outl(0xa8050000, ioaddr + CSR15);

        udelay(5);

        outl(0xa00f0000, ioaddr + CSR15);

        udelay(5);

        outl_CSR6(0, ioaddr);

        //outl_CSR6(FullDuplexBit, ioaddr);

}

static int __devinit xircom_init_one(struct pci_dev *pdev, const struct pci_device_id *id)

{

        struct net_device *dev;

        struct xircom_private *tp;

        static int board_idx = -1;

        int chip_idx = id->driver_data;

        long ioaddr;

        int i;

        u8 chip_rev;

/* when built into the kernel, we only print version if device is found */

#ifndef MODULE

        static int printed_version;

        if (!printed_version++)

                printk(version);

#endif

        //printk(KERN_INFO "xircom_init_one(%s)\n", pdev->slot_name);

        board_idx++;

        if (pci_enable_device(pdev))

                return -ENODEV;

        pci_set_master(pdev);

        ioaddr = pci_resource_start(pdev, 0);

        dev = alloc_etherdev(sizeof(*tp));

        if (!dev) {

                printk (KERN_ERR DRV_NAME "%d: cannot alloc etherdev, aborting\n", board_idx);

                return -ENOMEM;

        }

        SET_MODULE_OWNER(dev);

        dev->base_addr = ioaddr;

        dev->irq = pdev->irq;

        if (pci_request_regions(pdev, dev->name)) {

                printk (KERN_ERR DRV_NAME " %d: cannot reserve PCI resources, aborting\n", board_idx);

                goto err_out_free_netdev;

        }

        /* Bring the chip out of sleep mode.

           Caution: Snooze mode does not work with some boards! */

        if (xircom_tbl[chip_idx].flags & HAS_ACPI)

                pci_write_config_dword(pdev, PCI_POWERMGMT, 0);

        /* Stop the chip's Tx and Rx processes. */

        outl_CSR6(inl(ioaddr + CSR6) & ~EnableTxRx, ioaddr);

        /* Clear the missed-packet counter. */

        (volatile int)inl(ioaddr + CSR8);

        tp = dev->priv;

        tp->lock = SPIN_LOCK_UNLOCKED;

        tp->pdev = pdev;

        tp->chip_id = chip_idx;

        /* BugFixes: The 21143-TD hangs with PCI Write-and-Invalidate cycles. */

        /* XXX: is this necessary for Xircom? */

        tp->csr0 = csr0 & ~EnableMWI;

        pci_set_drvdata(pdev, dev);

        /* The lower four bits are the media type. */

        if (board_idx >= 0 && board_idx < MAX_UNITS) {

                tp->default_port = options[board_idx] & 15;

                if ((options[board_idx] & 0x90) || full_duplex[board_idx] > 0)

                        tp->full_duplex = 1;

                if (mtu[board_idx] > 0)

                        dev->mtu = mtu[board_idx];

        }

        if (dev->mem_start)

                tp->default_port = dev->mem_start;

        if (tp->default_port) {

                if (media_cap[tp->default_port] & MediaAlwaysFD)

                        tp->full_duplex = 1;

        }

        if (tp->full_duplex)

                tp->autoneg = 0;

        else

                tp->autoneg = 1;

        tp->speed100 = 1;

        /* The Xircom-specific entries in the device structure. */

        dev->open = &xircom_open;

        dev->hard_start_xmit = &xircom_start_xmit;

        dev->stop = &xircom_close;

        dev->get_stats = &xircom_get_stats;

        dev->do_ioctl = &xircom_ioctl;

#ifdef HAVE_MULTICAST

        dev->set_multicast_list = &set_rx_mode;

#endif

        dev->tx_timeout = xircom_tx_timeout;

        dev->watchdog_timeo = TX_TIMEOUT;

        transceiver_voodoo(dev);

        read_mac_address(dev);

        if (register_netdev(dev))

                goto err_out_cleardev;

        pci_read_config_byte(pdev, PCI_REVISION_ID, &chip_rev);

        printk(KERN_INFO "%s: %s rev %d at %#3lx,",

               dev->name, xircom_tbl[chip_idx].chip_name, chip_rev, ioaddr);

        for (i = 0; i < 6; i++)

                printk("%c%2.2X", i ? ':' : ' ', dev->dev_addr[i]);

        printk(", IRQ %d.\n", dev->irq);

        if (xircom_tbl[chip_idx].flags & HAS_MII) {

                find_mii_transceivers(dev);

                check_duplex(dev);

        }

        return 0;

err_out_cleardev:

        pci_set_drvdata(pdev, NULL);

        pci_release_regions(pdev);

err_out_free_netdev:

        unregister_netdev(dev);

        kfree(dev);

        return -ENODEV;

}

/* MII transceiver control section.

   Read and write the MII registers using software-generated serial

   MDIO protocol.  See the MII specifications or DP83840A data sheet

   for details. */

/* The maximum data clock rate is 2.5 Mhz.  The minimum timing is usually

   met by back-to-back PCI I/O cycles, but we insert a delay to avoid

   "overclocking" issues or future 66Mhz PCI. */

#define mdio_delay() inl(mdio_addr)

/* Read and write the MII registers using software-generated serial

   MDIO protocol.  It is just different enough from the EEPROM protocol

   to not share code.  The maxium data clock rate is 2.5 Mhz. */

#define MDIO_SHIFT_CLK  0x10000

#define MDIO_DATA_WRITE0 0x00000

#define MDIO_DATA_WRITE1 0x20000

#define MDIO_ENB                0x00000         /* Ignore the 0x02000 databook setting. */

#define MDIO_ENB_IN             0x40000

#define MDIO_DATA_READ  0x80000