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phoenix |
/* $Id: sunbmac.h,v 1.1.1.1 2004-04-15 01:40:21 phoenix Exp $
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* sunbmac.h: Defines for the Sun "Big MAC" 100baseT ethernet cards.
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*
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* Copyright (C) 1997 David S. Miller (davem@caip.rutgers.edu)
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*/
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#ifndef _SUNBMAC_H
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#define _SUNBMAC_H
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/* QEC global registers. */
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#define GLOB_CTRL 0x00UL /* Control */
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#define GLOB_STAT 0x04UL /* Status */
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#define GLOB_PSIZE 0x08UL /* Packet Size */
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#define GLOB_MSIZE 0x0cUL /* Local-mem size (64K) */
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#define GLOB_RSIZE 0x10UL /* Receive partition size */
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#define GLOB_TSIZE 0x14UL /* Transmit partition size */
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#define GLOB_REG_SIZE 0x18UL
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| 19 |
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#define GLOB_CTRL_MMODE 0x40000000 /* MACE qec mode */
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#define GLOB_CTRL_BMODE 0x10000000 /* BigMAC qec mode */
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#define GLOB_CTRL_EPAR 0x00000020 /* Enable parity */
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#define GLOB_CTRL_ACNTRL 0x00000018 /* SBUS arbitration control */
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#define GLOB_CTRL_B64 0x00000004 /* 64 byte dvma bursts */
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#define GLOB_CTRL_B32 0x00000002 /* 32 byte dvma bursts */
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#define GLOB_CTRL_B16 0x00000000 /* 16 byte dvma bursts */
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#define GLOB_CTRL_RESET 0x00000001 /* Reset the QEC */
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| 28 |
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#define GLOB_STAT_TX 0x00000008 /* BigMAC Transmit IRQ */
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#define GLOB_STAT_RX 0x00000004 /* BigMAC Receive IRQ */
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#define GLOB_STAT_BM 0x00000002 /* BigMAC Global IRQ */
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#define GLOB_STAT_ER 0x00000001 /* BigMAC Error IRQ */
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#define GLOB_PSIZE_2048 0x00 /* 2k packet size */
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#define GLOB_PSIZE_4096 0x01 /* 4k packet size */
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#define GLOB_PSIZE_6144 0x10 /* 6k packet size */
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#define GLOB_PSIZE_8192 0x11 /* 8k packet size */
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/* QEC BigMAC channel registers. */
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#define CREG_CTRL 0x00UL /* Control */
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#define CREG_STAT 0x04UL /* Status */
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#define CREG_RXDS 0x08UL /* RX descriptor ring ptr */
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#define CREG_TXDS 0x0cUL /* TX descriptor ring ptr */
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#define CREG_RIMASK 0x10UL /* RX Interrupt Mask */
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#define CREG_TIMASK 0x14UL /* TX Interrupt Mask */
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#define CREG_QMASK 0x18UL /* QEC Error Interrupt Mask */
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#define CREG_BMASK 0x1cUL /* BigMAC Error Interrupt Mask*/
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#define CREG_RXWBUFPTR 0x20UL /* Local memory rx write ptr */
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#define CREG_RXRBUFPTR 0x24UL /* Local memory rx read ptr */
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#define CREG_TXWBUFPTR 0x28UL /* Local memory tx write ptr */
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#define CREG_TXRBUFPTR 0x2cUL /* Local memory tx read ptr */
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#define CREG_CCNT 0x30UL /* Collision Counter */
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#define CREG_REG_SIZE 0x34UL
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#define CREG_CTRL_TWAKEUP 0x00000001 /* Transmitter Wakeup, 'go'. */
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#define CREG_STAT_BERROR 0x80000000 /* BigMAC error */
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#define CREG_STAT_TXIRQ 0x00200000 /* Transmit Interrupt */
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#define CREG_STAT_TXDERROR 0x00080000 /* TX Descriptor is bogus */
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#define CREG_STAT_TXLERR 0x00040000 /* Late Transmit Error */
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#define CREG_STAT_TXPERR 0x00020000 /* Transmit Parity Error */
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#define CREG_STAT_TXSERR 0x00010000 /* Transmit SBUS error ack */
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#define CREG_STAT_RXIRQ 0x00000020 /* Receive Interrupt */
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#define CREG_STAT_RXDROP 0x00000010 /* Dropped a RX'd packet */
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#define CREG_STAT_RXSMALL 0x00000008 /* Receive buffer too small */
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#define CREG_STAT_RXLERR 0x00000004 /* Receive Late Error */
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#define CREG_STAT_RXPERR 0x00000002 /* Receive Parity Error */
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#define CREG_STAT_RXSERR 0x00000001 /* Receive SBUS Error ACK */
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#define CREG_STAT_ERRORS (CREG_STAT_BERROR|CREG_STAT_TXDERROR|CREG_STAT_TXLERR| \
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CREG_STAT_TXPERR|CREG_STAT_TXSERR|CREG_STAT_RXDROP| \
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CREG_STAT_RXSMALL|CREG_STAT_RXLERR|CREG_STAT_RXPERR| \
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CREG_STAT_RXSERR)
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#define CREG_QMASK_TXDERROR 0x00080000 /* TXD error */
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#define CREG_QMASK_TXLERR 0x00040000 /* TX late error */
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#define CREG_QMASK_TXPERR 0x00020000 /* TX parity error */
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#define CREG_QMASK_TXSERR 0x00010000 /* TX sbus error ack */
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#define CREG_QMASK_RXDROP 0x00000010 /* RX drop */
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#define CREG_QMASK_RXBERROR 0x00000008 /* RX buffer error */
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#define CREG_QMASK_RXLEERR 0x00000004 /* RX late error */
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#define CREG_QMASK_RXPERR 0x00000002 /* RX parity error */
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#define CREG_QMASK_RXSERR 0x00000001 /* RX sbus error ack */
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/* BIGMAC core registers */
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#define BMAC_XIFCFG 0x000UL /* XIF config register */
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/* 0x004-->0x0fc, reserved */
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#define BMAC_STATUS 0x100UL /* Status register, clear on read */
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#define BMAC_IMASK 0x104UL /* Interrupt mask register */
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/* 0x108-->0x204, reserved */
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| 90 |
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#define BMAC_TXSWRESET 0x208UL /* Transmitter software reset */
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#define BMAC_TXCFG 0x20cUL /* Transmitter config register */
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#define BMAC_IGAP1 0x210UL /* Inter-packet gap 1 */
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#define BMAC_IGAP2 0x214UL /* Inter-packet gap 2 */
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#define BMAC_ALIMIT 0x218UL /* Transmit attempt limit */
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#define BMAC_STIME 0x21cUL /* Transmit slot time */
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#define BMAC_PLEN 0x220UL /* Size of transmit preamble */
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#define BMAC_PPAT 0x224UL /* Pattern for transmit preamble */
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#define BMAC_TXDELIM 0x228UL /* Transmit delimiter */
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#define BMAC_JSIZE 0x22cUL /* Toe jam... */
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#define BMAC_TXPMAX 0x230UL /* Transmit max pkt size */
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#define BMAC_TXPMIN 0x234UL /* Transmit min pkt size */
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| 102 |
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#define BMAC_PATTEMPT 0x238UL /* Count of transmit peak attempts */
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#define BMAC_DTCTR 0x23cUL /* Transmit defer timer */
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#define BMAC_NCCTR 0x240UL /* Transmit normal-collision counter */
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#define BMAC_FCCTR 0x244UL /* Transmit first-collision counter */
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#define BMAC_EXCTR 0x248UL /* Transmit excess-collision counter */
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#define BMAC_LTCTR 0x24cUL /* Transmit late-collision counter */
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| 108 |
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#define BMAC_RSEED 0x250UL /* Transmit random number seed */
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| 109 |
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#define BMAC_TXSMACHINE 0x254UL /* Transmit state machine */
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| 110 |
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/* 0x258-->0x304, reserved */
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| 111 |
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#define BMAC_RXSWRESET 0x308UL /* Receiver software reset */
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#define BMAC_RXCFG 0x30cUL /* Receiver config register */
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#define BMAC_RXPMAX 0x310UL /* Receive max pkt size */
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| 114 |
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#define BMAC_RXPMIN 0x314UL /* Receive min pkt size */
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| 115 |
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#define BMAC_MACADDR2 0x318UL /* Ether address register 2 */
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#define BMAC_MACADDR1 0x31cUL /* Ether address register 1 */
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#define BMAC_MACADDR0 0x320UL /* Ether address register 0 */
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#define BMAC_FRCTR 0x324UL /* Receive frame receive counter */
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#define BMAC_GLECTR 0x328UL /* Receive giant-length error counter */
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| 120 |
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#define BMAC_UNALECTR 0x32cUL /* Receive unaligned error counter */
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#define BMAC_RCRCECTR 0x330UL /* Receive CRC error counter */
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| 122 |
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#define BMAC_RXSMACHINE 0x334UL /* Receiver state machine */
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#define BMAC_RXCVALID 0x338UL /* Receiver code violation */
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/* 0x33c, reserved */
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#define BMAC_HTABLE3 0x340UL /* Hash table 3 */
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#define BMAC_HTABLE2 0x344UL /* Hash table 2 */
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| 127 |
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#define BMAC_HTABLE1 0x348UL /* Hash table 1 */
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| 128 |
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#define BMAC_HTABLE0 0x34cUL /* Hash table 0 */
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#define BMAC_AFILTER2 0x350UL /* Address filter 2 */
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#define BMAC_AFILTER1 0x354UL /* Address filter 1 */
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#define BMAC_AFILTER0 0x358UL /* Address filter 0 */
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#define BMAC_AFMASK 0x35cUL /* Address filter mask */
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#define BMAC_REG_SIZE 0x360UL
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/* BigMac XIF config register. */
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#define BIGMAC_XCFG_ODENABLE 0x00000001 /* Output driver enable */
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#define BIGMAC_XCFG_RESV 0x00000002 /* Reserved, write always as 1 */
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#define BIGMAC_XCFG_MLBACK 0x00000004 /* Loopback-mode MII enable */
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#define BIGMAC_XCFG_SMODE 0x00000008 /* Enable serial mode */
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/* BigMAC status register. */
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#define BIGMAC_STAT_GOTFRAME 0x00000001 /* Received a frame */
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#define BIGMAC_STAT_RCNTEXP 0x00000002 /* Receive frame counter expired */
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#define BIGMAC_STAT_ACNTEXP 0x00000004 /* Align-error counter expired */
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#define BIGMAC_STAT_CCNTEXP 0x00000008 /* CRC-error counter expired */
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#define BIGMAC_STAT_LCNTEXP 0x00000010 /* Length-error counter expired */
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#define BIGMAC_STAT_RFIFOVF 0x00000020 /* Receive FIFO overflow */
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#define BIGMAC_STAT_CVCNTEXP 0x00000040 /* Code-violation counter expired */
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#define BIGMAC_STAT_SENTFRAME 0x00000100 /* Transmitted a frame */
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#define BIGMAC_STAT_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
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#define BIGMAC_STAT_MAXPKTERR 0x00000400 /* Max-packet size error */
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#define BIGMAC_STAT_NCNTEXP 0x00000800 /* Normal-collision counter expired */
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#define BIGMAC_STAT_ECNTEXP 0x00001000 /* Excess-collision counter expired */
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#define BIGMAC_STAT_LCCNTEXP 0x00002000 /* Late-collision counter expired */
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#define BIGMAC_STAT_FCNTEXP 0x00004000 /* First-collision counter expired */
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#define BIGMAC_STAT_DTIMEXP 0x00008000 /* Defer-timer expired */
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| 158 |
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/* BigMAC interrupt mask register. */
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| 159 |
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#define BIGMAC_IMASK_GOTFRAME 0x00000001 /* Received a frame */
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| 160 |
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#define BIGMAC_IMASK_RCNTEXP 0x00000002 /* Receive frame counter expired */
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#define BIGMAC_IMASK_ACNTEXP 0x00000004 /* Align-error counter expired */
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#define BIGMAC_IMASK_CCNTEXP 0x00000008 /* CRC-error counter expired */
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#define BIGMAC_IMASK_LCNTEXP 0x00000010 /* Length-error counter expired */
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#define BIGMAC_IMASK_RFIFOVF 0x00000020 /* Receive FIFO overflow */
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#define BIGMAC_IMASK_CVCNTEXP 0x00000040 /* Code-violation counter expired */
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#define BIGMAC_IMASK_SENTFRAME 0x00000100 /* Transmitted a frame */
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#define BIGMAC_IMASK_TFIFO_UND 0x00000200 /* Transmit FIFO underrun */
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#define BIGMAC_IMASK_MAXPKTERR 0x00000400 /* Max-packet size error */
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#define BIGMAC_IMASK_NCNTEXP 0x00000800 /* Normal-collision counter expired */
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#define BIGMAC_IMASK_ECNTEXP 0x00001000 /* Excess-collision counter expired */
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#define BIGMAC_IMASK_LCCNTEXP 0x00002000 /* Late-collision counter expired */
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#define BIGMAC_IMASK_FCNTEXP 0x00004000 /* First-collision counter expired */
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#define BIGMAC_IMASK_DTIMEXP 0x00008000 /* Defer-timer expired */
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| 174 |
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| 175 |
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/* BigMac transmit config register. */
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| 176 |
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#define BIGMAC_TXCFG_ENABLE 0x00000001 /* Enable the transmitter */
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#define BIGMAC_TXCFG_FIFO 0x00000010 /* Default tx fthresh... */
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| 178 |
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#define BIGMAC_TXCFG_SMODE 0x00000020 /* Enable slow transmit mode */
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| 179 |
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#define BIGMAC_TXCFG_CIGN 0x00000040 /* Ignore transmit collisions */
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| 180 |
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#define BIGMAC_TXCFG_FCSOFF 0x00000080 /* Do not emit FCS */
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| 181 |
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#define BIGMAC_TXCFG_DBACKOFF 0x00000100 /* Disable backoff */
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| 182 |
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#define BIGMAC_TXCFG_FULLDPLX 0x00000200 /* Enable full-duplex */
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| 183 |
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| 184 |
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/* BigMac receive config register. */
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| 185 |
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#define BIGMAC_RXCFG_ENABLE 0x00000001 /* Enable the receiver */
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| 186 |
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#define BIGMAC_RXCFG_FIFO 0x0000000e /* Default rx fthresh... */
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#define BIGMAC_RXCFG_PSTRIP 0x00000020 /* Pad byte strip enable */
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| 188 |
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#define BIGMAC_RXCFG_PMISC 0x00000040 /* Enable promiscous mode */
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| 189 |
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#define BIGMAC_RXCFG_DERR 0x00000080 /* Disable error checking */
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| 190 |
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#define BIGMAC_RXCFG_DCRCS 0x00000100 /* Disable CRC stripping */
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| 191 |
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#define BIGMAC_RXCFG_ME 0x00000200 /* Receive packets addressed to me */
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| 192 |
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#define BIGMAC_RXCFG_PGRP 0x00000400 /* Enable promisc group mode */
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| 193 |
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#define BIGMAC_RXCFG_HENABLE 0x00000800 /* Enable the hash filter */
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| 194 |
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#define BIGMAC_RXCFG_AENABLE 0x00001000 /* Enable the address filter */
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| 196 |
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/* The BigMAC PHY transceiver. Not nearly as sophisticated as the happy meal
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* one. But it does have the "bit banger", oh baby.
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*/
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| 199 |
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#define TCVR_TPAL 0x00UL
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| 200 |
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#define TCVR_MPAL 0x04UL
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| 201 |
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#define TCVR_REG_SIZE 0x08UL
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| 202 |
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| 203 |
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/* Frame commands. */
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| 204 |
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#define FRAME_WRITE 0x50020000
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| 205 |
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#define FRAME_READ 0x60020000
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| 206 |
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| 207 |
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/* Tranceiver registers. */
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| 208 |
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#define TCVR_PAL_SERIAL 0x00000001 /* Enable serial mode */
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| 209 |
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#define TCVR_PAL_EXTLBACK 0x00000002 /* Enable external loopback */
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| 210 |
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#define TCVR_PAL_MSENSE 0x00000004 /* Media sense */
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| 211 |
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#define TCVR_PAL_LTENABLE 0x00000008 /* Link test enable */
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| 212 |
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#define TCVR_PAL_LTSTATUS 0x00000010 /* Link test status (P1 only) */
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| 213 |
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| 214 |
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/* Management PAL. */
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| 215 |
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#define MGMT_PAL_DCLOCK 0x00000001 /* Data clock */
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| 216 |
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#define MGMT_PAL_OENAB 0x00000002 /* Output enabler */
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| 217 |
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#define MGMT_PAL_MDIO 0x00000004 /* MDIO Data/attached */
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| 218 |
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#define MGMT_PAL_TIMEO 0x00000008 /* Transmit enable timeout error */
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| 219 |
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#define MGMT_PAL_EXT_MDIO MGMT_PAL_MDIO
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| 220 |
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#define MGMT_PAL_INT_MDIO MGMT_PAL_TIMEO
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| 221 |
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| 222 |
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/* Here are some PHY addresses. */
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| 223 |
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#define BIGMAC_PHY_EXTERNAL 0 /* External transceiver */
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| 224 |
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#define BIGMAC_PHY_INTERNAL 1 /* Internal transceiver */
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| 225 |
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| 226 |
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/* PHY registers */
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| 227 |
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#define BIGMAC_BMCR 0x00 /* Basic mode control register */
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| 228 |
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#define BIGMAC_BMSR 0x01 /* Basic mode status register */
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| 229 |
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| 230 |
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/* BMCR bits */
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| 231 |
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#define BMCR_ISOLATE 0x0400 /* Disconnect DP83840 from MII */
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| 232 |
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#define BMCR_PDOWN 0x0800 /* Powerdown the DP83840 */
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| 233 |
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#define BMCR_ANENABLE 0x1000 /* Enable auto negotiation */
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| 234 |
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#define BMCR_SPEED100 0x2000 /* Select 100Mbps */
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| 235 |
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#define BMCR_LOOPBACK 0x4000 /* TXD loopback bits */
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| 236 |
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#define BMCR_RESET 0x8000 /* Reset the DP83840 */
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| 237 |
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| 238 |
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/* BMSR bits */
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| 239 |
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#define BMSR_ERCAP 0x0001 /* Ext-reg capability */
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| 240 |
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#define BMSR_JCD 0x0002 /* Jabber detected */
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| 241 |
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#define BMSR_LSTATUS 0x0004 /* Link status */
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| 242 |
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| 243 |
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/* Ring descriptors and such, same as Quad Ethernet. */
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| 244 |
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struct be_rxd {
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| 245 |
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u32 rx_flags;
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| 246 |
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u32 rx_addr;
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| 247 |
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};
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| 248 |
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| 249 |
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#define RXD_OWN 0x80000000 /* Ownership. */
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| 250 |
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#define RXD_UPDATE 0x10000000 /* Being Updated? */
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| 251 |
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#define RXD_LENGTH 0x000007ff /* Packet Length. */
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| 252 |
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| 253 |
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struct be_txd {
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| 254 |
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u32 tx_flags;
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| 255 |
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u32 tx_addr;
|
| 256 |
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};
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| 257 |
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| 258 |
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#define TXD_OWN 0x80000000 /* Ownership. */
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| 259 |
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#define TXD_SOP 0x40000000 /* Start Of Packet */
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| 260 |
|
|
#define TXD_EOP 0x20000000 /* End Of Packet */
|
| 261 |
|
|
#define TXD_UPDATE 0x10000000 /* Being Updated? */
|
| 262 |
|
|
#define TXD_LENGTH 0x000007ff /* Packet Length. */
|
| 263 |
|
|
|
| 264 |
|
|
#define TX_RING_MAXSIZE 256
|
| 265 |
|
|
#define RX_RING_MAXSIZE 256
|
| 266 |
|
|
|
| 267 |
|
|
#define TX_RING_SIZE 256
|
| 268 |
|
|
#define RX_RING_SIZE 256
|
| 269 |
|
|
|
| 270 |
|
|
#define NEXT_RX(num) (((num) + 1) & (RX_RING_SIZE - 1))
|
| 271 |
|
|
#define NEXT_TX(num) (((num) + 1) & (TX_RING_SIZE - 1))
|
| 272 |
|
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#define PREV_RX(num) (((num) - 1) & (RX_RING_SIZE - 1))
|
| 273 |
|
|
#define PREV_TX(num) (((num) - 1) & (TX_RING_SIZE - 1))
|
| 274 |
|
|
|
| 275 |
|
|
#define TX_BUFFS_AVAIL(bp) \
|
| 276 |
|
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(((bp)->tx_old <= (bp)->tx_new) ? \
|
| 277 |
|
|
(bp)->tx_old + (TX_RING_SIZE - 1) - (bp)->tx_new : \
|
| 278 |
|
|
(bp)->tx_old - (bp)->tx_new - 1)
|
| 279 |
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|
|
| 280 |
|
|
|
| 281 |
|
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#define RX_COPY_THRESHOLD 256
|
| 282 |
|
|
#define RX_BUF_ALLOC_SIZE (ETH_FRAME_LEN + (64 * 3))
|
| 283 |
|
|
|
| 284 |
|
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struct bmac_init_block {
|
| 285 |
|
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struct be_rxd be_rxd[RX_RING_MAXSIZE];
|
| 286 |
|
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struct be_txd be_txd[TX_RING_MAXSIZE];
|
| 287 |
|
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};
|
| 288 |
|
|
|
| 289 |
|
|
#define bib_offset(mem, elem) \
|
| 290 |
|
|
((__u32)((unsigned long)(&(((struct bmac_init_block *)0)->mem[elem]))))
|
| 291 |
|
|
|
| 292 |
|
|
/* Now software state stuff. */
|
| 293 |
|
|
enum bigmac_transceiver {
|
| 294 |
|
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external = 0,
|
| 295 |
|
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internal = 1,
|
| 296 |
|
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none = 2,
|
| 297 |
|
|
};
|
| 298 |
|
|
|
| 299 |
|
|
/* Timer state engine. */
|
| 300 |
|
|
enum bigmac_timer_state {
|
| 301 |
|
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ltrywait = 1, /* Forcing try of all modes, from fastest to slowest. */
|
| 302 |
|
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asleep = 2, /* Timer inactive. */
|
| 303 |
|
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};
|
| 304 |
|
|
|
| 305 |
|
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struct bigmac {
|
| 306 |
|
|
unsigned long gregs; /* QEC Global Registers */
|
| 307 |
|
|
unsigned long creg; /* QEC BigMAC Channel Registers */
|
| 308 |
|
|
unsigned long bregs; /* BigMAC Registers */
|
| 309 |
|
|
unsigned long tregs; /* BigMAC Transceiver */
|
| 310 |
|
|
struct bmac_init_block *bmac_block; /* RX and TX descriptors */
|
| 311 |
|
|
__u32 bblock_dvma; /* RX and TX descriptors */
|
| 312 |
|
|
|
| 313 |
|
|
spinlock_t lock;
|
| 314 |
|
|
|
| 315 |
|
|
struct sk_buff *rx_skbs[RX_RING_SIZE];
|
| 316 |
|
|
struct sk_buff *tx_skbs[TX_RING_SIZE];
|
| 317 |
|
|
|
| 318 |
|
|
int rx_new, tx_new, rx_old, tx_old;
|
| 319 |
|
|
|
| 320 |
|
|
int board_rev; /* BigMAC board revision. */
|
| 321 |
|
|
|
| 322 |
|
|
enum bigmac_transceiver tcvr_type;
|
| 323 |
|
|
unsigned int bigmac_bursts;
|
| 324 |
|
|
unsigned int paddr;
|
| 325 |
|
|
unsigned short sw_bmsr; /* SW copy of PHY BMSR */
|
| 326 |
|
|
unsigned short sw_bmcr; /* SW copy of PHY BMCR */
|
| 327 |
|
|
struct timer_list bigmac_timer;
|
| 328 |
|
|
enum bigmac_timer_state timer_state;
|
| 329 |
|
|
unsigned int timer_ticks;
|
| 330 |
|
|
|
| 331 |
|
|
struct net_device_stats enet_stats;
|
| 332 |
|
|
struct sbus_dev *qec_sdev;
|
| 333 |
|
|
struct sbus_dev *bigmac_sdev;
|
| 334 |
|
|
struct net_device *dev;
|
| 335 |
|
|
struct bigmac *next_module;
|
| 336 |
|
|
};
|
| 337 |
|
|
|
| 338 |
|
|
/* We use this to acquire receive skb's that we can DMA directly into. */
|
| 339 |
|
|
#define ALIGNED_RX_SKB_ADDR(addr) \
|
| 340 |
|
|
((((unsigned long)(addr) + (64 - 1)) & ~(64 - 1)) - (unsigned long)(addr))
|
| 341 |
|
|
|
| 342 |
|
|
static inline struct sk_buff *big_mac_alloc_skb(unsigned int length, int gfp_flags)
|
| 343 |
|
|
{
|
| 344 |
|
|
struct sk_buff *skb;
|
| 345 |
|
|
|
| 346 |
|
|
skb = alloc_skb(length + 64, gfp_flags);
|
| 347 |
|
|
if(skb) {
|
| 348 |
|
|
int offset = ALIGNED_RX_SKB_ADDR(skb->data);
|
| 349 |
|
|
|
| 350 |
|
|
if(offset)
|
| 351 |
|
|
skb_reserve(skb, offset);
|
| 352 |
|
|
}
|
| 353 |
|
|
return skb;
|
| 354 |
|
|
}
|
| 355 |
|
|
|
| 356 |
|
|
#endif /* !(_SUNBMAC_H) */
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