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1275 |
phoenix |
/*
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* 3c359.c (c) 2000 Mike Phillips (mikep@linuxtr.net) All Rights Reserved
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*
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* Linux driver for 3Com 3c359 Tokenlink Velocity XL PCI NIC
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*
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* Base Driver Olympic:
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* Written 1999 Peter De Schrijver & Mike Phillips
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*
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* This software may be used and distributed according to the terms
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* of the GNU General Public License, incorporated herein by reference.
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*
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* 7/17/00 - Clean up, version number 0.9.0. Ready to release to the world.
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*
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* 2/16/01 - Port up to kernel 2.4.2 ready for submission into the kernel.
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* 3/05/01 - Last clean up stuff before submission.
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* 2/15/01 - Finally, update to new pci api.
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*
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* To Do:
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*/
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/*
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* Technical Card Details
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*
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* All access to data is done with 16/8 bit transfers. The transfer
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* method really sucks. You can only read or write one location at a time.
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*
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* Also, the microcode for the card must be uploaded if the card does not have
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* the flashrom on board. This is a 28K bloat in the driver when compiled
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* as a module.
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*
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* Rx is very simple, status into a ring of descriptors, dma data transfer,
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* interrupts to tell us when a packet is received.
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*
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* Tx is a little more interesting. Similar scenario, descriptor and dma data
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* transfers, but we don't have to interrupt the card to tell it another packet
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* is ready for transmission, we are just doing simple memory writes, not io or mmio
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* writes. The card can be set up to simply poll on the next
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* descriptor pointer and when this value is non-zero will automatically download
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* the next packet. The card then interrupts us when the packet is done.
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*
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*/
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#define XL_DEBUG 0
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#include <linux/config.h>
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#include <linux/module.h>
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#include <linux/kernel.h>
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#include <linux/sched.h>
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#include <linux/errno.h>
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#include <linux/timer.h>
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#include <linux/in.h>
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#include <linux/ioport.h>
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#include <linux/string.h>
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#include <linux/proc_fs.h>
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#include <linux/ptrace.h>
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#include <linux/skbuff.h>
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#include <linux/interrupt.h>
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#include <linux/delay.h>
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#include <linux/netdevice.h>
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#include <linux/trdevice.h>
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#include <linux/stddef.h>
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#include <linux/init.h>
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#include <linux/pci.h>
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#include <linux/spinlock.h>
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#include <net/checksum.h>
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#include <asm/io.h>
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#include <asm/system.h>
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#include <asm/bitops.h>
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#include "3c359.h"
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static char version[] __devinitdata =
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"3c359.c v1.2.0 2/17/01 - Mike Phillips (mikep@linuxtr.net)" ;
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MODULE_AUTHOR("Mike Phillips <mikep@linuxtr.net>") ;
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MODULE_DESCRIPTION("3Com 3C359 Velocity XL Token Ring Adapter Driver \n") ;
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/* Module paramters */
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/* Ring Speed 0,4,16
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* 0 = Autosense
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* 4,16 = Selected speed only, no autosense
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* This allows the card to be the first on the ring
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* and become the active monitor.
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*
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* WARNING: Some hubs will allow you to insert
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* at the wrong speed.
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*
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* The adapter will _not_ fail to open if there are no
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* active monitors on the ring, it will simply open up in
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* its last known ringspeed if no ringspeed is specified.
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*/
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static int ringspeed[XL_MAX_ADAPTERS] = {0,} ;
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MODULE_PARM(ringspeed, "1-" __MODULE_STRING(XL_MAX_ADAPTERS) "i");
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MODULE_PARM_DESC(ringspeed,"3c359: Ringspeed selection - 4,16 or 0") ;
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/* Packet buffer size */
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static int pkt_buf_sz[XL_MAX_ADAPTERS] = {0,} ;
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MODULE_PARM(pkt_buf_sz, "1-" __MODULE_STRING(XL_MAX_ADAPTERS) "i") ;
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MODULE_PARM_DESC(pkt_buf_sz,"3c359: Initial buffer size") ;
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/* Message Level */
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static int message_level[XL_MAX_ADAPTERS] = {0,} ;
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MODULE_PARM(message_level, "1-" __MODULE_STRING(XL_MAX_ADAPTERS) "i") ;
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MODULE_PARM_DESC(message_level, "3c359: Level of reported messages \n") ;
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/*
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* This is a real nasty way of doing this, but otherwise you
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* will be stuck with 1555 lines of hex #'s in the code.
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*/
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#include "3c359_microcode.h"
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static struct pci_device_id xl_pci_tbl[] __devinitdata =
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{
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{PCI_VENDOR_ID_3COM,PCI_DEVICE_ID_3COM_3C359, PCI_ANY_ID, PCI_ANY_ID, },
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{ } /* terminate list */
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};
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MODULE_DEVICE_TABLE(pci,xl_pci_tbl) ;
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static int xl_init(struct net_device *dev);
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static int xl_open(struct net_device *dev);
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static int xl_open_hw(struct net_device *dev) ;
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static int xl_hw_reset(struct net_device *dev);
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static int xl_xmit(struct sk_buff *skb, struct net_device *dev);
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static void xl_dn_comp(struct net_device *dev);
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static int xl_close(struct net_device *dev);
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static void xl_set_rx_mode(struct net_device *dev);
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static void xl_interrupt(int irq, void *dev_id, struct pt_regs *regs);
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static struct net_device_stats * xl_get_stats(struct net_device *dev);
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static int xl_set_mac_address(struct net_device *dev, void *addr) ;
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static void xl_arb_cmd(struct net_device *dev);
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static void xl_asb_cmd(struct net_device *dev) ;
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static void xl_srb_cmd(struct net_device *dev, int srb_cmd) ;
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static void xl_wait_misr_flags(struct net_device *dev) ;
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static int xl_change_mtu(struct net_device *dev, int mtu);
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static void xl_srb_bh(struct net_device *dev) ;
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static void xl_asb_bh(struct net_device *dev) ;
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static void xl_reset(struct net_device *dev) ;
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static void xl_freemem(struct net_device *dev) ;
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/* EEProm Access Functions */
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static u16 xl_ee_read(struct net_device *dev, int ee_addr) ;
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static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value) ;
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/* Debugging functions */
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#if XL_DEBUG
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static void print_tx_state(struct net_device *dev) ;
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static void print_rx_state(struct net_device *dev) ;
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static void print_tx_state(struct net_device *dev)
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{
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struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
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struct xl_tx_desc *txd ;
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u8 *xl_mmio = xl_priv->xl_mmio ;
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int i ;
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printk("tx_ring_head: %d, tx_ring_tail: %d, free_ent: %d \n",xl_priv->tx_ring_head,
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xl_priv->tx_ring_tail, xl_priv->free_ring_entries) ;
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printk("Ring , Address , FSH , DnNextPtr, Buffer, Buffer_Len \n");
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for (i = 0; i < 16; i++) {
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txd = &(xl_priv->xl_tx_ring[i]) ;
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printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(txd),
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txd->framestartheader, txd->dnnextptr, txd->buffer, txd->buffer_length ) ;
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}
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printk("DNLISTPTR = %04x \n", readl(xl_mmio + MMIO_DNLISTPTR) );
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printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
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printk("Queue status = %0x \n",netif_running(dev) ) ;
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}
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static void print_rx_state(struct net_device *dev)
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{
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struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
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struct xl_rx_desc *rxd ;
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u8 *xl_mmio = xl_priv->xl_mmio ;
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int i ;
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printk("rx_ring_tail: %d \n", xl_priv->rx_ring_tail) ;
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printk("Ring , Address , FrameState , UPNextPtr, FragAddr, Frag_Len \n");
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for (i = 0; i < 16; i++) {
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/* rxd = (struct xl_rx_desc *)xl_priv->rx_ring_dma_addr + (i * sizeof(struct xl_rx_desc)) ; */
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rxd = &(xl_priv->xl_rx_ring[i]) ;
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printk("%d, %08lx, %08x, %08x, %08x, %08x \n", i, virt_to_bus(rxd),
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rxd->framestatus, rxd->upnextptr, rxd->upfragaddr, rxd->upfraglen ) ;
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}
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printk("UPLISTPTR = %04x \n", readl(xl_mmio + MMIO_UPLISTPTR) );
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printk("DmaCtl = %04x \n", readl(xl_mmio + MMIO_DMA_CTRL) );
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printk("Queue status = %0x \n",netif_running(dev) ) ;
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}
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#endif
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/*
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* Read values from the on-board EEProm. This looks very strange
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* but you have to wait for the EEProm to get/set the value before
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* passing/getting the next value from the nic. As with all requests
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* on this nic it has to be done in two stages, a) tell the nic which
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* memory address you want to access and b) pass/get the value from the nic.
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* With the EEProm, you have to wait before and inbetween access a) and b).
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* As this is only read at initialization time and the wait period is very
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* small we shouldn't have to worry about scheduling issues.
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*/
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static u16 xl_ee_read(struct net_device *dev, int ee_addr)
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{
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struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
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u8 *xl_mmio = xl_priv->xl_mmio ;
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/* Wait for EEProm to not be busy */
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writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
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/* Tell EEProm what we want to do and where */
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writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
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229 |
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/* Wait for EEProm to not be busy */
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writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
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/* Tell EEProm what we want to do and where */
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writel(IO_WORD_WRITE | EECONTROL , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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writew(EEREAD + ee_addr, xl_mmio + MMIO_MACDATA) ;
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/* Finally read the value from the EEProm */
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writel(IO_WORD_READ | EEDATA , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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return readw(xl_mmio + MMIO_MACDATA) ;
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240 |
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}
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241 |
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242 |
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/*
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243 |
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* Write values to the onboard eeprom. As with eeprom read you need to
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* set which location to write, wait, value to write, wait, with the
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* added twist of having to enable eeprom writes as well.
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*/
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247 |
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248 |
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static void xl_ee_write(struct net_device *dev, int ee_addr, u16 ee_value)
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{
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250 |
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struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
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u8 *xl_mmio = xl_priv->xl_mmio ;
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253 |
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/* Wait for EEProm to not be busy */
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254 |
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writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
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256 |
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257 |
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/* Enable write/erase */
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writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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259 |
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writew(EE_ENABLE_WRITE, xl_mmio + MMIO_MACDATA) ;
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260 |
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261 |
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/* Wait for EEProm to not be busy */
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262 |
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writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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263 |
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while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
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264 |
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265 |
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/* Put the value we want to write into EEDATA */
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266 |
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writel(IO_WORD_WRITE | EEDATA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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267 |
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writew(ee_value, xl_mmio + MMIO_MACDATA) ;
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268 |
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269 |
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/* Tell EEProm to write eevalue into ee_addr */
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270 |
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writel(IO_WORD_WRITE | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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271 |
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writew(EEWRITE + ee_addr, xl_mmio + MMIO_MACDATA) ;
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272 |
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273 |
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/* Wait for EEProm to not be busy, to ensure write gets done */
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274 |
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writel(IO_WORD_READ | EECONTROL, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
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275 |
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while ( readw(xl_mmio + MMIO_MACDATA) & EEBUSY ) ;
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276 |
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277 |
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return ;
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278 |
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}
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279 |
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|
280 |
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int __devinit xl_probe(struct pci_dev *pdev, const struct pci_device_id *ent)
|
281 |
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{
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282 |
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struct net_device *dev ;
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283 |
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struct xl_private *xl_priv ;
|
284 |
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static int card_no = -1 ;
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285 |
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int i ;
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286 |
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287 |
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card_no++ ;
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288 |
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289 |
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if (pci_enable_device(pdev)) {
|
290 |
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return -ENODEV ;
|
291 |
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}
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292 |
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|
293 |
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pci_set_master(pdev);
|
294 |
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|
295 |
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if ((i = pci_request_regions(pdev,"3c359"))) {
|
296 |
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return i ;
|
297 |
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} ;
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298 |
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|
299 |
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/*
|
300 |
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* Allowing init_trdev to allocate the dev->priv structure will align xl_private
|
301 |
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* on a 32 bytes boundary which we need for the rx/tx descriptors
|
302 |
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*/
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303 |
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|
304 |
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dev = alloc_trdev(sizeof(struct xl_private)) ;
|
305 |
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if (!dev) {
|
306 |
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pci_release_regions(pdev) ;
|
307 |
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return -ENOMEM ;
|
308 |
|
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}
|
309 |
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xl_priv = dev->priv ;
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310 |
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311 |
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#if XL_DEBUG
|
312 |
|
|
printk("pci_device: %p, dev:%p, dev->priv: %p, ba[0]: %10x, ba[1]:%10x\n",
|
313 |
|
|
pdev, dev, dev->priv, (unsigned int)pdev->resource[0].start, (unsigned int)pdev->resource[1].start) ;
|
314 |
|
|
#endif
|
315 |
|
|
|
316 |
|
|
dev->irq=pdev->irq;
|
317 |
|
|
dev->base_addr=pci_resource_start(pdev,0) ;
|
318 |
|
|
dev->init=NULL ; /* Must be null with new api, otherwise get called twice */
|
319 |
|
|
xl_priv->xl_card_name = (char *)pdev->name ;
|
320 |
|
|
xl_priv->xl_mmio=ioremap(pci_resource_start(pdev,1), XL_IO_SPACE);
|
321 |
|
|
xl_priv->pdev = pdev ;
|
322 |
|
|
|
323 |
|
|
if ((pkt_buf_sz[card_no] < 100) || (pkt_buf_sz[card_no] > 18000) )
|
324 |
|
|
xl_priv->pkt_buf_sz = PKT_BUF_SZ ;
|
325 |
|
|
else
|
326 |
|
|
xl_priv->pkt_buf_sz = pkt_buf_sz[card_no] ;
|
327 |
|
|
|
328 |
|
|
dev->mtu = xl_priv->pkt_buf_sz - TR_HLEN ;
|
329 |
|
|
xl_priv->xl_ring_speed = ringspeed[card_no] ;
|
330 |
|
|
xl_priv->xl_message_level = message_level[card_no] ;
|
331 |
|
|
xl_priv->xl_functional_addr[0] = xl_priv->xl_functional_addr[1] = xl_priv->xl_functional_addr[2] = xl_priv->xl_functional_addr[3] = 0 ;
|
332 |
|
|
xl_priv->xl_copy_all_options = 0 ;
|
333 |
|
|
|
334 |
|
|
if((i = xl_init(dev))) {
|
335 |
|
|
iounmap(xl_priv->xl_mmio) ;
|
336 |
|
|
kfree(dev) ;
|
337 |
|
|
pci_release_regions(pdev) ;
|
338 |
|
|
return i ;
|
339 |
|
|
}
|
340 |
|
|
|
341 |
|
|
dev->open=&xl_open;
|
342 |
|
|
dev->hard_start_xmit=&xl_xmit;
|
343 |
|
|
dev->change_mtu=&xl_change_mtu;
|
344 |
|
|
dev->stop=&xl_close;
|
345 |
|
|
dev->do_ioctl=NULL;
|
346 |
|
|
dev->set_multicast_list=&xl_set_rx_mode;
|
347 |
|
|
dev->get_stats=&xl_get_stats ;
|
348 |
|
|
dev->set_mac_address=&xl_set_mac_address ;
|
349 |
|
|
SET_MODULE_OWNER(dev);
|
350 |
|
|
|
351 |
|
|
pci_set_drvdata(pdev,dev) ;
|
352 |
|
|
if ((i = register_netdev(dev))) {
|
353 |
|
|
printk(KERN_ERR "3C359, register netdev failed\n") ;
|
354 |
|
|
pci_set_drvdata(pdev,NULL) ;
|
355 |
|
|
iounmap(xl_priv->xl_mmio) ;
|
356 |
|
|
kfree(dev) ;
|
357 |
|
|
pci_release_regions(pdev) ;
|
358 |
|
|
return i ;
|
359 |
|
|
}
|
360 |
|
|
|
361 |
|
|
printk(KERN_INFO "3C359: %s registered as: %s\n",xl_priv->xl_card_name,dev->name) ;
|
362 |
|
|
|
363 |
|
|
return 0;
|
364 |
|
|
}
|
365 |
|
|
|
366 |
|
|
|
367 |
|
|
static int __init xl_init(struct net_device *dev)
|
368 |
|
|
{
|
369 |
|
|
struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
|
370 |
|
|
|
371 |
|
|
printk(KERN_INFO "%s \n", version);
|
372 |
|
|
printk(KERN_INFO "%s: I/O at %hx, MMIO at %p, using irq %d\n",
|
373 |
|
|
xl_priv->xl_card_name, (unsigned int)dev->base_addr ,xl_priv->xl_mmio, dev->irq);
|
374 |
|
|
|
375 |
|
|
spin_lock_init(&xl_priv->xl_lock) ;
|
376 |
|
|
|
377 |
|
|
return xl_hw_reset(dev) ;
|
378 |
|
|
|
379 |
|
|
}
|
380 |
|
|
|
381 |
|
|
|
382 |
|
|
/*
|
383 |
|
|
* Hardware reset. This needs to be a separate entity as we need to reset the card
|
384 |
|
|
* when we change the EEProm settings.
|
385 |
|
|
*/
|
386 |
|
|
|
387 |
|
|
static int xl_hw_reset(struct net_device *dev)
|
388 |
|
|
{
|
389 |
|
|
struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
|
390 |
|
|
u8 *xl_mmio = xl_priv->xl_mmio ;
|
391 |
|
|
unsigned long t ;
|
392 |
|
|
u16 i ;
|
393 |
|
|
u16 result_16 ;
|
394 |
|
|
u8 result_8 ;
|
395 |
|
|
u16 start ;
|
396 |
|
|
int j ;
|
397 |
|
|
|
398 |
|
|
/*
|
399 |
|
|
* Reset the card. If the card has got the microcode on board, we have
|
400 |
|
|
* missed the initialization interrupt, so we must always do this.
|
401 |
|
|
*/
|
402 |
|
|
|
403 |
|
|
writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
|
404 |
|
|
|
405 |
|
|
/*
|
406 |
|
|
* Must wait for cmdInProgress bit (12) to clear before continuing with
|
407 |
|
|
* card configuration.
|
408 |
|
|
*/
|
409 |
|
|
|
410 |
|
|
t=jiffies;
|
411 |
|
|
while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
|
412 |
|
|
schedule();
|
413 |
|
|
if(jiffies-t > 40*HZ) {
|
414 |
|
|
printk(KERN_ERR "%s: 3COM 3C359 Velocity XL card not responding to global reset.\n", dev->name);
|
415 |
|
|
return -ENODEV;
|
416 |
|
|
}
|
417 |
|
|
}
|
418 |
|
|
|
419 |
|
|
/*
|
420 |
|
|
* Enable pmbar by setting bit in CPAttention
|
421 |
|
|
*/
|
422 |
|
|
|
423 |
|
|
writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
424 |
|
|
result_8 = readb(xl_mmio + MMIO_MACDATA) ;
|
425 |
|
|
result_8 = result_8 | CPA_PMBARVIS ;
|
426 |
|
|
writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
427 |
|
|
writeb(result_8, xl_mmio + MMIO_MACDATA) ;
|
428 |
|
|
|
429 |
|
|
/*
|
430 |
|
|
* Read cpHold bit in pmbar, if cleared we have got Flashrom on board.
|
431 |
|
|
* If not, we need to upload the microcode to the card
|
432 |
|
|
*/
|
433 |
|
|
|
434 |
|
|
writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
|
435 |
|
|
|
436 |
|
|
#if XL_DEBUG
|
437 |
|
|
printk(KERN_INFO "Read from PMBAR = %04x \n", readw(xl_mmio + MMIO_MACDATA)) ;
|
438 |
|
|
#endif
|
439 |
|
|
|
440 |
|
|
if ( readw( (xl_mmio + MMIO_MACDATA)) & PMB_CPHOLD ) {
|
441 |
|
|
|
442 |
|
|
/* Set PmBar, privateMemoryBase bits (8:2) to 0 */
|
443 |
|
|
|
444 |
|
|
writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
|
445 |
|
|
result_16 = readw(xl_mmio + MMIO_MACDATA) ;
|
446 |
|
|
result_16 = result_16 & ~((0x7F) << 2) ;
|
447 |
|
|
writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
448 |
|
|
writew(result_16,xl_mmio + MMIO_MACDATA) ;
|
449 |
|
|
|
450 |
|
|
/* Set CPAttention, memWrEn bit */
|
451 |
|
|
|
452 |
|
|
writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
453 |
|
|
result_8 = readb(xl_mmio + MMIO_MACDATA) ;
|
454 |
|
|
result_8 = result_8 | CPA_MEMWREN ;
|
455 |
|
|
writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
456 |
|
|
writeb(result_8, xl_mmio + MMIO_MACDATA) ;
|
457 |
|
|
|
458 |
|
|
/*
|
459 |
|
|
* Now to write the microcode into the shared ram
|
460 |
|
|
* The microcode must finish at position 0xFFFF, so we must subtract
|
461 |
|
|
* to get the start position for the code
|
462 |
|
|
*/
|
463 |
|
|
|
464 |
|
|
start = (0xFFFF - (mc_size) + 1 ) ; /* Looks strange but ensures compiler only uses 16 bit unsigned int for this */
|
465 |
|
|
|
466 |
|
|
printk(KERN_INFO "3C359: Uploading Microcode: ");
|
467 |
|
|
|
468 |
|
|
for (i = start,j=0; (j < mc_size && i <= 0xffff) ; i++,j++) {
|
469 |
|
|
writel(MEM_BYTE_WRITE | 0XD0000 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
470 |
|
|
writeb(microcode[j],xl_mmio + MMIO_MACDATA) ;
|
471 |
|
|
if (j % 1024 == 0)
|
472 |
|
|
printk(".");
|
473 |
|
|
}
|
474 |
|
|
printk("\n") ;
|
475 |
|
|
|
476 |
|
|
for (i=0;i < 16; i++) {
|
477 |
|
|
writel( (MEM_BYTE_WRITE | 0xDFFF0) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
478 |
|
|
writeb(microcode[mc_size - 16 + i], xl_mmio + MMIO_MACDATA) ;
|
479 |
|
|
}
|
480 |
|
|
|
481 |
|
|
/*
|
482 |
|
|
* Have to write the start address of the upload to FFF4, but
|
483 |
|
|
* the address must be >> 4. You do not want to know how long
|
484 |
|
|
* it took me to discover this.
|
485 |
|
|
*/
|
486 |
|
|
|
487 |
|
|
writel(MEM_WORD_WRITE | 0xDFFF4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
488 |
|
|
writew(start >> 4, xl_mmio + MMIO_MACDATA);
|
489 |
|
|
|
490 |
|
|
/* Clear the CPAttention, memWrEn Bit */
|
491 |
|
|
|
492 |
|
|
writel( (IO_BYTE_READ | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
493 |
|
|
result_8 = readb(xl_mmio + MMIO_MACDATA) ;
|
494 |
|
|
result_8 = result_8 & ~CPA_MEMWREN ;
|
495 |
|
|
writel( (IO_BYTE_WRITE | CPATTENTION), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
496 |
|
|
writeb(result_8, xl_mmio + MMIO_MACDATA) ;
|
497 |
|
|
|
498 |
|
|
/* Clear the cpHold bit in pmbar */
|
499 |
|
|
|
500 |
|
|
writel( (IO_WORD_READ | PMBAR),xl_mmio + MMIO_MAC_ACCESS_CMD);
|
501 |
|
|
result_16 = readw(xl_mmio + MMIO_MACDATA) ;
|
502 |
|
|
result_16 = result_16 & ~PMB_CPHOLD ;
|
503 |
|
|
writel( (IO_WORD_WRITE | PMBAR), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
504 |
|
|
writew(result_16,xl_mmio + MMIO_MACDATA) ;
|
505 |
|
|
|
506 |
|
|
|
507 |
|
|
} /* If microcode upload required */
|
508 |
|
|
|
509 |
|
|
/*
|
510 |
|
|
* The card should now go though a self test procedure and get itself ready
|
511 |
|
|
* to be opened, we must wait for an srb response with the initialization
|
512 |
|
|
* information.
|
513 |
|
|
*/
|
514 |
|
|
|
515 |
|
|
#if XL_DEBUG
|
516 |
|
|
printk(KERN_INFO "%s: Microcode uploaded, must wait for the self test to complete\n", dev->name);
|
517 |
|
|
#endif
|
518 |
|
|
|
519 |
|
|
writew(SETINDENABLE | 0xFFF, xl_mmio + MMIO_COMMAND) ;
|
520 |
|
|
|
521 |
|
|
t=jiffies;
|
522 |
|
|
while ( !(readw(xl_mmio + MMIO_INTSTATUS_AUTO) & INTSTAT_SRB) ) {
|
523 |
|
|
schedule();
|
524 |
|
|
if(jiffies-t > 15*HZ) {
|
525 |
|
|
printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
|
526 |
|
|
return -ENODEV;
|
527 |
|
|
}
|
528 |
|
|
}
|
529 |
|
|
|
530 |
|
|
/*
|
531 |
|
|
* Write the RxBufArea with D000, RxEarlyThresh, TxStartThresh,
|
532 |
|
|
* DnPriReqThresh, read the tech docs if you want to know what
|
533 |
|
|
* values they need to be.
|
534 |
|
|
*/
|
535 |
|
|
|
536 |
|
|
writel(MMIO_WORD_WRITE | RXBUFAREA, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
537 |
|
|
writew(0xD000, xl_mmio + MMIO_MACDATA) ;
|
538 |
|
|
|
539 |
|
|
writel(MMIO_WORD_WRITE | RXEARLYTHRESH, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
540 |
|
|
writew(0X0020, xl_mmio + MMIO_MACDATA) ;
|
541 |
|
|
|
542 |
|
|
writew( SETTXSTARTTHRESH | 0x40 , xl_mmio + MMIO_COMMAND) ;
|
543 |
|
|
|
544 |
|
|
writeb(0x04, xl_mmio + MMIO_DNBURSTTHRESH) ;
|
545 |
|
|
writeb(0x04, xl_mmio + DNPRIREQTHRESH) ;
|
546 |
|
|
|
547 |
|
|
/*
|
548 |
|
|
* Read WRBR to provide the location of the srb block, have to use byte reads not word reads.
|
549 |
|
|
* Tech docs have this wrong !!!!
|
550 |
|
|
*/
|
551 |
|
|
|
552 |
|
|
writel(MMIO_BYTE_READ | WRBR, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
553 |
|
|
xl_priv->srb = readb(xl_mmio + MMIO_MACDATA) << 8 ;
|
554 |
|
|
writel( (MMIO_BYTE_READ | WRBR) + 1, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
555 |
|
|
xl_priv->srb = xl_priv->srb | readb(xl_mmio + MMIO_MACDATA) ;
|
556 |
|
|
|
557 |
|
|
#if XL_DEBUG
|
558 |
|
|
writel(IO_WORD_READ | SWITCHSETTINGS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
559 |
|
|
if ( readw(xl_mmio + MMIO_MACDATA) & 2) {
|
560 |
|
|
printk(KERN_INFO "Default ring speed 4 mbps \n") ;
|
561 |
|
|
} else {
|
562 |
|
|
printk(KERN_INFO "Default ring speed 16 mbps \n") ;
|
563 |
|
|
}
|
564 |
|
|
printk(KERN_INFO "%s: xl_priv->srb = %04x\n",xl_priv->xl_card_name, xl_priv->srb);
|
565 |
|
|
#endif
|
566 |
|
|
|
567 |
|
|
return 0;
|
568 |
|
|
}
|
569 |
|
|
|
570 |
|
|
static int xl_open(struct net_device *dev)
|
571 |
|
|
{
|
572 |
|
|
struct xl_private *xl_priv=(struct xl_private *)dev->priv;
|
573 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
574 |
|
|
u8 i ;
|
575 |
|
|
u16 hwaddr[3] ; /* Should be u8[6] but we get word return values */
|
576 |
|
|
int open_err ;
|
577 |
|
|
|
578 |
|
|
u16 switchsettings, switchsettings_eeprom ;
|
579 |
|
|
|
580 |
|
|
if(request_irq(dev->irq, &xl_interrupt, SA_SHIRQ , "3c359", dev)) {
|
581 |
|
|
return -EAGAIN;
|
582 |
|
|
}
|
583 |
|
|
|
584 |
|
|
/*
|
585 |
|
|
* Read the information from the EEPROM that we need. I know we
|
586 |
|
|
* should use ntohs, but the word gets stored reversed in the 16
|
587 |
|
|
* bit field anyway and it all works its self out when we memcpy
|
588 |
|
|
* it into dev->dev_addr.
|
589 |
|
|
*/
|
590 |
|
|
|
591 |
|
|
hwaddr[0] = xl_ee_read(dev,0x10) ;
|
592 |
|
|
hwaddr[1] = xl_ee_read(dev,0x11) ;
|
593 |
|
|
hwaddr[2] = xl_ee_read(dev,0x12) ;
|
594 |
|
|
|
595 |
|
|
/* Ring speed */
|
596 |
|
|
|
597 |
|
|
switchsettings_eeprom = xl_ee_read(dev,0x08) ;
|
598 |
|
|
switchsettings = switchsettings_eeprom ;
|
599 |
|
|
|
600 |
|
|
if (xl_priv->xl_ring_speed != 0) {
|
601 |
|
|
if (xl_priv->xl_ring_speed == 4)
|
602 |
|
|
switchsettings = switchsettings | 0x02 ;
|
603 |
|
|
else
|
604 |
|
|
switchsettings = switchsettings & ~0x02 ;
|
605 |
|
|
}
|
606 |
|
|
|
607 |
|
|
/* Only write EEProm if there has been a change */
|
608 |
|
|
if (switchsettings != switchsettings_eeprom) {
|
609 |
|
|
xl_ee_write(dev,0x08,switchsettings) ;
|
610 |
|
|
/* Hardware reset after changing EEProm */
|
611 |
|
|
xl_hw_reset(dev) ;
|
612 |
|
|
}
|
613 |
|
|
|
614 |
|
|
memcpy(dev->dev_addr,hwaddr,dev->addr_len) ;
|
615 |
|
|
|
616 |
|
|
open_err = xl_open_hw(dev) ;
|
617 |
|
|
|
618 |
|
|
/*
|
619 |
|
|
* This really needs to be cleaned up with better error reporting.
|
620 |
|
|
*/
|
621 |
|
|
|
622 |
|
|
if (open_err != 0) { /* Something went wrong with the open command */
|
623 |
|
|
if (open_err & 0x07) { /* Wrong speed, retry at different speed */
|
624 |
|
|
printk(KERN_WARNING "%s: Open Error, retrying at different ringspeed \n", dev->name) ;
|
625 |
|
|
switchsettings = switchsettings ^ 2 ;
|
626 |
|
|
xl_ee_write(dev,0x08,switchsettings) ;
|
627 |
|
|
xl_hw_reset(dev) ;
|
628 |
|
|
open_err = xl_open_hw(dev) ;
|
629 |
|
|
if (open_err != 0) {
|
630 |
|
|
printk(KERN_WARNING "%s: Open error returned a second time, we're bombing out now\n", dev->name);
|
631 |
|
|
free_irq(dev->irq,dev) ;
|
632 |
|
|
return -ENODEV ;
|
633 |
|
|
}
|
634 |
|
|
} else {
|
635 |
|
|
printk(KERN_WARNING "%s: Open Error = %04x\n", dev->name, open_err) ;
|
636 |
|
|
free_irq(dev->irq,dev) ;
|
637 |
|
|
return -ENODEV ;
|
638 |
|
|
}
|
639 |
|
|
}
|
640 |
|
|
|
641 |
|
|
/*
|
642 |
|
|
* Now to set up the Rx and Tx buffer structures
|
643 |
|
|
*/
|
644 |
|
|
/* These MUST be on 8 byte boundaries */
|
645 |
|
|
xl_priv->xl_tx_ring = kmalloc((sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) + 7, GFP_DMA | GFP_KERNEL) ;
|
646 |
|
|
xl_priv->xl_rx_ring = kmalloc((sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) +7, GFP_DMA | GFP_KERNEL) ;
|
647 |
|
|
memset(xl_priv->xl_tx_ring,0,sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE) ;
|
648 |
|
|
memset(xl_priv->xl_rx_ring,0,sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE) ;
|
649 |
|
|
|
650 |
|
|
/* Setup Rx Ring */
|
651 |
|
|
for (i=0 ; i < XL_RX_RING_SIZE ; i++) {
|
652 |
|
|
struct sk_buff *skb ;
|
653 |
|
|
|
654 |
|
|
skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
|
655 |
|
|
if (skb==NULL)
|
656 |
|
|
break ;
|
657 |
|
|
|
658 |
|
|
skb->dev = dev ;
|
659 |
|
|
xl_priv->xl_rx_ring[i].upfragaddr = pci_map_single(xl_priv->pdev, skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
|
660 |
|
|
xl_priv->xl_rx_ring[i].upfraglen = xl_priv->pkt_buf_sz | RXUPLASTFRAG;
|
661 |
|
|
xl_priv->rx_ring_skb[i] = skb ;
|
662 |
|
|
}
|
663 |
|
|
|
664 |
|
|
if (i==0) {
|
665 |
|
|
printk(KERN_WARNING "%s: Not enough memory to allocate rx buffers. Adapter disabled \n",dev->name) ;
|
666 |
|
|
free_irq(dev->irq,dev) ;
|
667 |
|
|
return -EIO ;
|
668 |
|
|
}
|
669 |
|
|
|
670 |
|
|
xl_priv->rx_ring_no = i ;
|
671 |
|
|
xl_priv->rx_ring_tail = 0 ;
|
672 |
|
|
xl_priv->rx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_rx_ring, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_TODEVICE) ;
|
673 |
|
|
for (i=0;i<(xl_priv->rx_ring_no-1);i++) {
|
674 |
|
|
xl_priv->xl_rx_ring[i].upnextptr = xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * (i+1)) ;
|
675 |
|
|
}
|
676 |
|
|
xl_priv->xl_rx_ring[i].upnextptr = 0 ;
|
677 |
|
|
|
678 |
|
|
writel(xl_priv->rx_ring_dma_addr, xl_mmio + MMIO_UPLISTPTR) ;
|
679 |
|
|
|
680 |
|
|
/* Setup Tx Ring */
|
681 |
|
|
|
682 |
|
|
xl_priv->tx_ring_dma_addr = pci_map_single(xl_priv->pdev,xl_priv->xl_tx_ring, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE,PCI_DMA_TODEVICE) ;
|
683 |
|
|
|
684 |
|
|
xl_priv->tx_ring_head = 1 ;
|
685 |
|
|
xl_priv->tx_ring_tail = 255 ; /* Special marker for first packet */
|
686 |
|
|
xl_priv->free_ring_entries = XL_TX_RING_SIZE ;
|
687 |
|
|
|
688 |
|
|
/*
|
689 |
|
|
* Setup the first dummy DPD entry for polling to start working.
|
690 |
|
|
*/
|
691 |
|
|
|
692 |
|
|
xl_priv->xl_tx_ring[0].framestartheader = TXDPDEMPTY ;
|
693 |
|
|
xl_priv->xl_tx_ring[0].buffer = 0 ;
|
694 |
|
|
xl_priv->xl_tx_ring[0].buffer_length = 0 ;
|
695 |
|
|
xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
|
696 |
|
|
|
697 |
|
|
writel(xl_priv->tx_ring_dma_addr, xl_mmio + MMIO_DNLISTPTR) ;
|
698 |
|
|
writel(DNUNSTALL, xl_mmio + MMIO_COMMAND) ;
|
699 |
|
|
writel(UPUNSTALL, xl_mmio + MMIO_COMMAND) ;
|
700 |
|
|
writel(DNENABLE, xl_mmio + MMIO_COMMAND) ;
|
701 |
|
|
writeb(0x40, xl_mmio + MMIO_DNPOLL) ;
|
702 |
|
|
|
703 |
|
|
/*
|
704 |
|
|
* Enable interrupts on the card
|
705 |
|
|
*/
|
706 |
|
|
|
707 |
|
|
writel(SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
|
708 |
|
|
writel(SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
|
709 |
|
|
|
710 |
|
|
netif_start_queue(dev) ;
|
711 |
|
|
return 0;
|
712 |
|
|
|
713 |
|
|
}
|
714 |
|
|
|
715 |
|
|
static int xl_open_hw(struct net_device *dev)
|
716 |
|
|
{
|
717 |
|
|
struct xl_private *xl_priv=(struct xl_private *)dev->priv;
|
718 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
719 |
|
|
u16 vsoff ;
|
720 |
|
|
char ver_str[33];
|
721 |
|
|
int open_err ;
|
722 |
|
|
int i ;
|
723 |
|
|
unsigned long t ;
|
724 |
|
|
|
725 |
|
|
/*
|
726 |
|
|
* Okay, let's build up the Open.NIC srb command
|
727 |
|
|
*
|
728 |
|
|
*/
|
729 |
|
|
|
730 |
|
|
writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
731 |
|
|
writeb(OPEN_NIC, xl_mmio + MMIO_MACDATA) ;
|
732 |
|
|
|
733 |
|
|
/*
|
734 |
|
|
* Use this as a test byte, if it comes back with the same value, the command didn't work
|
735 |
|
|
*/
|
736 |
|
|
|
737 |
|
|
writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb)+ 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
738 |
|
|
writeb(0xff,xl_mmio + MMIO_MACDATA) ;
|
739 |
|
|
|
740 |
|
|
/* Open options */
|
741 |
|
|
writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
742 |
|
|
writeb(0x00, xl_mmio + MMIO_MACDATA) ;
|
743 |
|
|
writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + 9, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
744 |
|
|
writeb(0x00, xl_mmio + MMIO_MACDATA) ;
|
745 |
|
|
|
746 |
|
|
/*
|
747 |
|
|
* Node address, be careful here, the docs say you can just put zeros here and it will use
|
748 |
|
|
* the hardware address, it doesn't, you must include the node address in the open command.
|
749 |
|
|
*/
|
750 |
|
|
|
751 |
|
|
if (xl_priv->xl_laa[0]) { /* If using a LAA address */
|
752 |
|
|
for (i=10;i<16;i++) {
|
753 |
|
|
writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
754 |
|
|
writeb(xl_priv->xl_laa[i],xl_mmio + MMIO_MACDATA) ;
|
755 |
|
|
}
|
756 |
|
|
memcpy(dev->dev_addr,xl_priv->xl_laa,dev->addr_len) ;
|
757 |
|
|
} else { /* Regular hardware address */
|
758 |
|
|
for (i=10;i<16;i++) {
|
759 |
|
|
writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
760 |
|
|
writeb(dev->dev_addr[i-10], xl_mmio + MMIO_MACDATA) ;
|
761 |
|
|
}
|
762 |
|
|
}
|
763 |
|
|
|
764 |
|
|
/* Default everything else to 0 */
|
765 |
|
|
for (i = 16; i < 34; i++) {
|
766 |
|
|
writel( (MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
767 |
|
|
writeb(0x00,xl_mmio + MMIO_MACDATA) ;
|
768 |
|
|
}
|
769 |
|
|
|
770 |
|
|
/*
|
771 |
|
|
* Set the csrb bit in the MISR register
|
772 |
|
|
*/
|
773 |
|
|
|
774 |
|
|
xl_wait_misr_flags(dev) ;
|
775 |
|
|
writel(MEM_BYTE_WRITE | MF_CSRB, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
776 |
|
|
writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
|
777 |
|
|
writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
778 |
|
|
writeb(MISR_CSRB , xl_mmio + MMIO_MACDATA) ;
|
779 |
|
|
|
780 |
|
|
/*
|
781 |
|
|
* Now wait for the command to run
|
782 |
|
|
*/
|
783 |
|
|
|
784 |
|
|
t=jiffies;
|
785 |
|
|
while (! (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
|
786 |
|
|
schedule();
|
787 |
|
|
if(jiffies-t > 40*HZ) {
|
788 |
|
|
printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
|
789 |
|
|
break ;
|
790 |
|
|
}
|
791 |
|
|
}
|
792 |
|
|
|
793 |
|
|
/*
|
794 |
|
|
* Let's interpret the open response
|
795 |
|
|
*/
|
796 |
|
|
|
797 |
|
|
writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb)+2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
798 |
|
|
if (readb(xl_mmio + MMIO_MACDATA)!=0) {
|
799 |
|
|
open_err = readb(xl_mmio + MMIO_MACDATA) << 8 ;
|
800 |
|
|
writel( (MEM_BYTE_READ | 0xD0000 | xl_priv->srb) + 7, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
801 |
|
|
open_err |= readb(xl_mmio + MMIO_MACDATA) ;
|
802 |
|
|
return open_err ;
|
803 |
|
|
} else {
|
804 |
|
|
writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 8, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
805 |
|
|
xl_priv->asb = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
|
806 |
|
|
printk(KERN_INFO "%s: Adapter Opened Details: ",dev->name) ;
|
807 |
|
|
printk("ASB: %04x",xl_priv->asb ) ;
|
808 |
|
|
writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 10, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
809 |
|
|
printk(", SRB: %04x",ntohs(readw(xl_mmio + MMIO_MACDATA)) ) ;
|
810 |
|
|
|
811 |
|
|
writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 12, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
812 |
|
|
xl_priv->arb = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
|
813 |
|
|
printk(", ARB: %04x \n",xl_priv->arb ) ;
|
814 |
|
|
writel( (MEM_WORD_READ | 0xD0000 | xl_priv->srb) + 14, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
815 |
|
|
vsoff = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
|
816 |
|
|
|
817 |
|
|
/*
|
818 |
|
|
* Interesting, sending the individual characters directly to printk was causing klogd to use
|
819 |
|
|
* use 100% of processor time, so we build up the string and print that instead.
|
820 |
|
|
*/
|
821 |
|
|
|
822 |
|
|
for (i=0;i<0x20;i++) {
|
823 |
|
|
writel( (MEM_BYTE_READ | 0xD0000 | vsoff) + i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
824 |
|
|
ver_str[i] = readb(xl_mmio + MMIO_MACDATA) ;
|
825 |
|
|
}
|
826 |
|
|
ver_str[i] = '\0' ;
|
827 |
|
|
printk(KERN_INFO "%s: Microcode version String: %s \n",dev->name,ver_str);
|
828 |
|
|
}
|
829 |
|
|
|
830 |
|
|
/*
|
831 |
|
|
* Issue the AckInterrupt
|
832 |
|
|
*/
|
833 |
|
|
writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
|
834 |
|
|
|
835 |
|
|
return 0 ;
|
836 |
|
|
}
|
837 |
|
|
|
838 |
|
|
/*
|
839 |
|
|
* There are two ways of implementing rx on the 359 NIC, either
|
840 |
|
|
* interrupt driven or polling. We are going to uses interrupts,
|
841 |
|
|
* it is the easier way of doing things.
|
842 |
|
|
*
|
843 |
|
|
* The Rx works with a ring of Rx descriptors. At initialise time the ring
|
844 |
|
|
* entries point to the next entry except for the last entry in the ring
|
845 |
|
|
* which points to 0. The card is programmed with the location of the first
|
846 |
|
|
* available descriptor and keeps reading the next_ptr until next_ptr is set
|
847 |
|
|
* to 0. Hopefully with a ring size of 16 the card will never get to read a next_ptr
|
848 |
|
|
* of 0. As the Rx interrupt is received we copy the frame up to the protocol layers
|
849 |
|
|
* and then point the end of the ring to our current position and point our current
|
850 |
|
|
* position to 0, therefore making the current position the last position on the ring.
|
851 |
|
|
* The last position on the ring therefore loops continually loops around the rx ring.
|
852 |
|
|
*
|
853 |
|
|
* rx_ring_tail is the position on the ring to process next. (Think of a snake, the head
|
854 |
|
|
* expands as the card adds new packets and we go around eating the tail processing the
|
855 |
|
|
* packets.)
|
856 |
|
|
*
|
857 |
|
|
* Undoubtably it could be streamlined and improved upon, but at the moment it works
|
858 |
|
|
* and the fast path through the routine is fine.
|
859 |
|
|
*
|
860 |
|
|
* adv_rx_ring could be inlined to increase performance, but its called a *lot* of times
|
861 |
|
|
* in xl_rx so would increase the size of the function significantly.
|
862 |
|
|
*/
|
863 |
|
|
|
864 |
|
|
static void adv_rx_ring(struct net_device *dev) /* Advance rx_ring, cut down on bloat in xl_rx */
|
865 |
|
|
{
|
866 |
|
|
struct xl_private *xl_priv=(struct xl_private *)dev->priv;
|
867 |
|
|
int prev_ring_loc ;
|
868 |
|
|
|
869 |
|
|
prev_ring_loc = (xl_priv->rx_ring_tail + XL_RX_RING_SIZE - 1) & (XL_RX_RING_SIZE - 1);
|
870 |
|
|
xl_priv->xl_rx_ring[prev_ring_loc].upnextptr = xl_priv->rx_ring_dma_addr + (sizeof (struct xl_rx_desc) * xl_priv->rx_ring_tail) ;
|
871 |
|
|
xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus = 0 ;
|
872 |
|
|
xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upnextptr = 0 ;
|
873 |
|
|
xl_priv->rx_ring_tail++ ;
|
874 |
|
|
xl_priv->rx_ring_tail &= (XL_RX_RING_SIZE-1) ;
|
875 |
|
|
|
876 |
|
|
return ;
|
877 |
|
|
}
|
878 |
|
|
|
879 |
|
|
static void xl_rx(struct net_device *dev)
|
880 |
|
|
{
|
881 |
|
|
struct xl_private *xl_priv=(struct xl_private *)dev->priv;
|
882 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
883 |
|
|
struct sk_buff *skb, *skb2 ;
|
884 |
|
|
int frame_length = 0, copy_len = 0 ;
|
885 |
|
|
int temp_ring_loc ;
|
886 |
|
|
|
887 |
|
|
/*
|
888 |
|
|
* Receive the next frame, loop around the ring until all frames
|
889 |
|
|
* have been received.
|
890 |
|
|
*/
|
891 |
|
|
|
892 |
|
|
while (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & (RXUPDCOMPLETE | RXUPDFULL) ) { /* Descriptor to process */
|
893 |
|
|
|
894 |
|
|
if (xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & RXUPDFULL ) { /* UpdFull, Multiple Descriptors used for the frame */
|
895 |
|
|
|
896 |
|
|
/*
|
897 |
|
|
* This is a pain, you need to go through all the descriptors until the last one
|
898 |
|
|
* for this frame to find the framelength
|
899 |
|
|
*/
|
900 |
|
|
|
901 |
|
|
temp_ring_loc = xl_priv->rx_ring_tail ;
|
902 |
|
|
|
903 |
|
|
while (xl_priv->xl_rx_ring[temp_ring_loc].framestatus & RXUPDFULL ) {
|
904 |
|
|
temp_ring_loc++ ;
|
905 |
|
|
temp_ring_loc &= (XL_RX_RING_SIZE-1) ;
|
906 |
|
|
}
|
907 |
|
|
|
908 |
|
|
frame_length = xl_priv->xl_rx_ring[temp_ring_loc].framestatus & 0x7FFF ;
|
909 |
|
|
|
910 |
|
|
skb = dev_alloc_skb(frame_length) ;
|
911 |
|
|
|
912 |
|
|
if (skb==NULL) { /* No memory for frame, still need to roll forward the rx ring */
|
913 |
|
|
printk(KERN_WARNING "%s: dev_alloc_skb failed - multi buffer !\n", dev->name) ;
|
914 |
|
|
while (xl_priv->rx_ring_tail != temp_ring_loc)
|
915 |
|
|
adv_rx_ring(dev) ;
|
916 |
|
|
|
917 |
|
|
adv_rx_ring(dev) ; /* One more time just for luck :) */
|
918 |
|
|
xl_priv->xl_stats.rx_dropped++ ;
|
919 |
|
|
|
920 |
|
|
writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
|
921 |
|
|
return ;
|
922 |
|
|
}
|
923 |
|
|
|
924 |
|
|
skb->dev = dev ;
|
925 |
|
|
|
926 |
|
|
while (xl_priv->rx_ring_tail != temp_ring_loc) {
|
927 |
|
|
copy_len = xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen & 0x7FFF ;
|
928 |
|
|
frame_length -= copy_len ;
|
929 |
|
|
pci_dma_sync_single(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
|
930 |
|
|
memcpy(skb_put(skb,copy_len), xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]->data, copy_len) ;
|
931 |
|
|
adv_rx_ring(dev) ;
|
932 |
|
|
}
|
933 |
|
|
|
934 |
|
|
/* Now we have found the last fragment */
|
935 |
|
|
pci_dma_sync_single(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
|
936 |
|
|
memcpy(skb_put(skb,copy_len), xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]->data, frame_length) ;
|
937 |
|
|
/* memcpy(skb_put(skb,frame_length), bus_to_virt(xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr), frame_length) ; */
|
938 |
|
|
adv_rx_ring(dev) ;
|
939 |
|
|
skb->protocol = tr_type_trans(skb,dev) ;
|
940 |
|
|
netif_rx(skb) ;
|
941 |
|
|
|
942 |
|
|
} else { /* Single Descriptor Used, simply swap buffers over, fast path */
|
943 |
|
|
|
944 |
|
|
frame_length = xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].framestatus & 0x7FFF ;
|
945 |
|
|
|
946 |
|
|
skb = dev_alloc_skb(xl_priv->pkt_buf_sz) ;
|
947 |
|
|
|
948 |
|
|
if (skb==NULL) { /* Still need to fix the rx ring */
|
949 |
|
|
printk(KERN_WARNING "%s: dev_alloc_skb failed in rx, single buffer \n",dev->name) ;
|
950 |
|
|
adv_rx_ring(dev) ;
|
951 |
|
|
xl_priv->xl_stats.rx_dropped++ ;
|
952 |
|
|
writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
|
953 |
|
|
return ;
|
954 |
|
|
}
|
955 |
|
|
|
956 |
|
|
skb->dev = dev ;
|
957 |
|
|
|
958 |
|
|
skb2 = xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] ;
|
959 |
|
|
pci_unmap_single(xl_priv->pdev, xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr, xl_priv->pkt_buf_sz,PCI_DMA_FROMDEVICE) ;
|
960 |
|
|
skb_put(skb2, frame_length) ;
|
961 |
|
|
skb2->protocol = tr_type_trans(skb2,dev) ;
|
962 |
|
|
|
963 |
|
|
xl_priv->rx_ring_skb[xl_priv->rx_ring_tail] = skb ;
|
964 |
|
|
xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr = pci_map_single(xl_priv->pdev,skb->data,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
|
965 |
|
|
xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfraglen = xl_priv->pkt_buf_sz | RXUPLASTFRAG ;
|
966 |
|
|
adv_rx_ring(dev) ;
|
967 |
|
|
xl_priv->xl_stats.rx_packets++ ;
|
968 |
|
|
xl_priv->xl_stats.rx_bytes += frame_length ;
|
969 |
|
|
|
970 |
|
|
netif_rx(skb2) ;
|
971 |
|
|
} /* if multiple buffers */
|
972 |
|
|
dev->last_rx = jiffies ;
|
973 |
|
|
} /* while packet to do */
|
974 |
|
|
|
975 |
|
|
/* Clear the updComplete interrupt */
|
976 |
|
|
writel(ACK_INTERRUPT | UPCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
|
977 |
|
|
return ;
|
978 |
|
|
}
|
979 |
|
|
|
980 |
|
|
/*
|
981 |
|
|
* This is ruthless, it doesn't care what state the card is in it will
|
982 |
|
|
* completely reset the adapter.
|
983 |
|
|
*/
|
984 |
|
|
|
985 |
|
|
static void xl_reset(struct net_device *dev)
|
986 |
|
|
{
|
987 |
|
|
struct xl_private *xl_priv=(struct xl_private *)dev->priv;
|
988 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
989 |
|
|
unsigned long t;
|
990 |
|
|
|
991 |
|
|
writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
|
992 |
|
|
|
993 |
|
|
/*
|
994 |
|
|
* Must wait for cmdInProgress bit (12) to clear before continuing with
|
995 |
|
|
* card configuration.
|
996 |
|
|
*/
|
997 |
|
|
|
998 |
|
|
t=jiffies;
|
999 |
|
|
while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
|
1000 |
|
|
if(jiffies-t > 40*HZ) {
|
1001 |
|
|
printk(KERN_ERR "3COM 3C359 Velocity XL card not responding.\n");
|
1002 |
|
|
break ;
|
1003 |
|
|
}
|
1004 |
|
|
}
|
1005 |
|
|
|
1006 |
|
|
}
|
1007 |
|
|
|
1008 |
|
|
static void xl_freemem(struct net_device *dev)
|
1009 |
|
|
{
|
1010 |
|
|
struct xl_private *xl_priv=(struct xl_private *)dev->priv ;
|
1011 |
|
|
int i ;
|
1012 |
|
|
|
1013 |
|
|
for (i=0;i<XL_RX_RING_SIZE;i++) {
|
1014 |
|
|
dev_kfree_skb_irq(xl_priv->rx_ring_skb[xl_priv->rx_ring_tail]) ;
|
1015 |
|
|
pci_unmap_single(xl_priv->pdev,xl_priv->xl_rx_ring[xl_priv->rx_ring_tail].upfragaddr,xl_priv->pkt_buf_sz, PCI_DMA_FROMDEVICE) ;
|
1016 |
|
|
xl_priv->rx_ring_tail++ ;
|
1017 |
|
|
xl_priv->rx_ring_tail &= XL_RX_RING_SIZE-1;
|
1018 |
|
|
}
|
1019 |
|
|
|
1020 |
|
|
/* unmap ring */
|
1021 |
|
|
pci_unmap_single(xl_priv->pdev,xl_priv->rx_ring_dma_addr, sizeof(struct xl_rx_desc) * XL_RX_RING_SIZE, PCI_DMA_FROMDEVICE) ;
|
1022 |
|
|
|
1023 |
|
|
pci_unmap_single(xl_priv->pdev,xl_priv->tx_ring_dma_addr, sizeof(struct xl_tx_desc) * XL_TX_RING_SIZE, PCI_DMA_TODEVICE) ;
|
1024 |
|
|
|
1025 |
|
|
kfree(xl_priv->xl_rx_ring) ;
|
1026 |
|
|
kfree(xl_priv->xl_tx_ring) ;
|
1027 |
|
|
|
1028 |
|
|
return ;
|
1029 |
|
|
}
|
1030 |
|
|
|
1031 |
|
|
static void xl_interrupt(int irq, void *dev_id, struct pt_regs *regs)
|
1032 |
|
|
{
|
1033 |
|
|
struct net_device *dev = (struct net_device *)dev_id;
|
1034 |
|
|
struct xl_private *xl_priv =(struct xl_private *)dev->priv;
|
1035 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
1036 |
|
|
u16 intstatus, macstatus ;
|
1037 |
|
|
|
1038 |
|
|
if (!dev) {
|
1039 |
|
|
printk(KERN_WARNING "Device structure dead, aaahhhh !\n") ;
|
1040 |
|
|
return ;
|
1041 |
|
|
}
|
1042 |
|
|
|
1043 |
|
|
intstatus = readw(xl_mmio + MMIO_INTSTATUS) ;
|
1044 |
|
|
|
1045 |
|
|
if (!(intstatus & 1)) /* We didn't generate the interrupt */
|
1046 |
|
|
return ;
|
1047 |
|
|
|
1048 |
|
|
spin_lock(&xl_priv->xl_lock) ;
|
1049 |
|
|
|
1050 |
|
|
/*
|
1051 |
|
|
* Process the interrupt
|
1052 |
|
|
*/
|
1053 |
|
|
/*
|
1054 |
|
|
* Something fishy going on here, we shouldn't get 0001 ints, not fatal though.
|
1055 |
|
|
*/
|
1056 |
|
|
if (intstatus == 0x0001) {
|
1057 |
|
|
writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
|
1058 |
|
|
printk(KERN_INFO "%s: 00001 int received \n",dev->name) ;
|
1059 |
|
|
} else {
|
1060 |
|
|
if (intstatus & (HOSTERRINT | SRBRINT | ARBCINT | UPCOMPINT | DNCOMPINT | HARDERRINT | (1<<8) | TXUNDERRUN | ASBFINT)) {
|
1061 |
|
|
|
1062 |
|
|
/*
|
1063 |
|
|
* Host Error.
|
1064 |
|
|
* It may be possible to recover from this, but usually it means something
|
1065 |
|
|
* is seriously fubar, so we just close the adapter.
|
1066 |
|
|
*/
|
1067 |
|
|
|
1068 |
|
|
if (intstatus & HOSTERRINT) {
|
1069 |
|
|
printk(KERN_WARNING "%s: Host Error, performing global reset, intstatus = %04x \n",dev->name,intstatus) ;
|
1070 |
|
|
writew( GLOBAL_RESET, xl_mmio + MMIO_COMMAND ) ;
|
1071 |
|
|
printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
|
1072 |
|
|
netif_stop_queue(dev) ;
|
1073 |
|
|
xl_freemem(dev) ;
|
1074 |
|
|
free_irq(dev->irq,dev);
|
1075 |
|
|
xl_reset(dev) ;
|
1076 |
|
|
writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
|
1077 |
|
|
spin_unlock(&xl_priv->xl_lock) ;
|
1078 |
|
|
return ;
|
1079 |
|
|
} /* Host Error */
|
1080 |
|
|
|
1081 |
|
|
if (intstatus & SRBRINT ) { /* Srbc interrupt */
|
1082 |
|
|
writel(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
|
1083 |
|
|
if (xl_priv->srb_queued)
|
1084 |
|
|
xl_srb_bh(dev) ;
|
1085 |
|
|
} /* SRBR Interrupt */
|
1086 |
|
|
|
1087 |
|
|
if (intstatus & TXUNDERRUN) { /* Issue DnReset command */
|
1088 |
|
|
writel(DNRESET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1089 |
|
|
while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) { /* Wait for command to run */
|
1090 |
|
|
/* !!! FIX-ME !!!!
|
1091 |
|
|
Must put a timeout check here ! */
|
1092 |
|
|
/* Empty Loop */
|
1093 |
|
|
}
|
1094 |
|
|
printk(KERN_WARNING "%s: TX Underrun received \n",dev->name) ;
|
1095 |
|
|
writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
|
1096 |
|
|
} /* TxUnderRun */
|
1097 |
|
|
|
1098 |
|
|
if (intstatus & ARBCINT ) { /* Arbc interrupt */
|
1099 |
|
|
xl_arb_cmd(dev) ;
|
1100 |
|
|
} /* Arbc */
|
1101 |
|
|
|
1102 |
|
|
if (intstatus & ASBFINT) {
|
1103 |
|
|
if (xl_priv->asb_queued == 1) {
|
1104 |
|
|
xl_asb_cmd(dev) ;
|
1105 |
|
|
} else if (xl_priv->asb_queued == 2) {
|
1106 |
|
|
xl_asb_bh(dev) ;
|
1107 |
|
|
} else {
|
1108 |
|
|
writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
|
1109 |
|
|
}
|
1110 |
|
|
} /* Asbf */
|
1111 |
|
|
|
1112 |
|
|
if (intstatus & UPCOMPINT ) /* UpComplete */
|
1113 |
|
|
xl_rx(dev) ;
|
1114 |
|
|
|
1115 |
|
|
if (intstatus & DNCOMPINT ) /* DnComplete */
|
1116 |
|
|
xl_dn_comp(dev) ;
|
1117 |
|
|
|
1118 |
|
|
if (intstatus & HARDERRINT ) { /* Hardware error */
|
1119 |
|
|
writel(MMIO_WORD_READ | MACSTATUS, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1120 |
|
|
macstatus = readw(xl_mmio + MMIO_MACDATA) ;
|
1121 |
|
|
printk(KERN_WARNING "%s: MacStatusError, details: ", dev->name);
|
1122 |
|
|
if (macstatus & (1<<14))
|
1123 |
|
|
printk(KERN_WARNING "tchk error: Unrecoverable error \n") ;
|
1124 |
|
|
if (macstatus & (1<<3))
|
1125 |
|
|
printk(KERN_WARNING "eint error: Internal watchdog timer expired \n") ;
|
1126 |
|
|
if (macstatus & (1<<2))
|
1127 |
|
|
printk(KERN_WARNING "aint error: Host tried to perform illegal operation \n") ;
|
1128 |
|
|
printk(KERN_WARNING "Instatus = %02x, macstatus = %02x\n",intstatus,macstatus) ;
|
1129 |
|
|
printk(KERN_WARNING "%s: Resetting hardware: \n", dev->name);
|
1130 |
|
|
netif_stop_queue(dev) ;
|
1131 |
|
|
xl_freemem(dev) ;
|
1132 |
|
|
free_irq(dev->irq,dev);
|
1133 |
|
|
unregister_trdev(dev) ;
|
1134 |
|
|
kfree(dev) ;
|
1135 |
|
|
xl_reset(dev) ;
|
1136 |
|
|
writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
|
1137 |
|
|
spin_unlock(&xl_priv->xl_lock) ;
|
1138 |
|
|
return ;
|
1139 |
|
|
}
|
1140 |
|
|
} else {
|
1141 |
|
|
printk(KERN_WARNING "%s: Received Unknown interrupt : %04x \n", dev->name, intstatus) ;
|
1142 |
|
|
writel(ACK_INTERRUPT | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
|
1143 |
|
|
}
|
1144 |
|
|
}
|
1145 |
|
|
|
1146 |
|
|
/* Turn interrupts back on */
|
1147 |
|
|
|
1148 |
|
|
writel( SETINDENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
|
1149 |
|
|
writel( SETINTENABLE | INT_MASK, xl_mmio + MMIO_COMMAND) ;
|
1150 |
|
|
|
1151 |
|
|
spin_unlock(&xl_priv->xl_lock) ;
|
1152 |
|
|
}
|
1153 |
|
|
|
1154 |
|
|
/*
|
1155 |
|
|
* Tx - Polling configuration
|
1156 |
|
|
*/
|
1157 |
|
|
|
1158 |
|
|
static int xl_xmit(struct sk_buff *skb, struct net_device *dev)
|
1159 |
|
|
{
|
1160 |
|
|
struct xl_private *xl_priv=(struct xl_private *)dev->priv;
|
1161 |
|
|
struct xl_tx_desc *txd ;
|
1162 |
|
|
int tx_head, tx_tail, tx_prev ;
|
1163 |
|
|
unsigned long flags ;
|
1164 |
|
|
|
1165 |
|
|
spin_lock_irqsave(&xl_priv->xl_lock,flags) ;
|
1166 |
|
|
|
1167 |
|
|
netif_stop_queue(dev) ;
|
1168 |
|
|
|
1169 |
|
|
if (xl_priv->free_ring_entries > 1 ) {
|
1170 |
|
|
/*
|
1171 |
|
|
* Set up the descriptor for the packet
|
1172 |
|
|
*/
|
1173 |
|
|
tx_head = xl_priv->tx_ring_head ;
|
1174 |
|
|
tx_tail = xl_priv->tx_ring_tail ;
|
1175 |
|
|
|
1176 |
|
|
txd = &(xl_priv->xl_tx_ring[tx_head]) ;
|
1177 |
|
|
txd->dnnextptr = 0 ;
|
1178 |
|
|
txd->framestartheader = skb->len | TXDNINDICATE ;
|
1179 |
|
|
txd->buffer = pci_map_single(xl_priv->pdev, skb->data, skb->len, PCI_DMA_TODEVICE) ;
|
1180 |
|
|
txd->buffer_length = skb->len | TXDNFRAGLAST ;
|
1181 |
|
|
xl_priv->tx_ring_skb[tx_head] = skb ;
|
1182 |
|
|
xl_priv->xl_stats.tx_packets++ ;
|
1183 |
|
|
xl_priv->xl_stats.tx_bytes += skb->len ;
|
1184 |
|
|
|
1185 |
|
|
/*
|
1186 |
|
|
* Set the nextptr of the previous descriptor equal to this descriptor, add XL_TX_RING_SIZE -1
|
1187 |
|
|
* to ensure no negative numbers in unsigned locations.
|
1188 |
|
|
*/
|
1189 |
|
|
|
1190 |
|
|
tx_prev = (xl_priv->tx_ring_head + XL_TX_RING_SIZE - 1) & (XL_TX_RING_SIZE - 1) ;
|
1191 |
|
|
|
1192 |
|
|
xl_priv->tx_ring_head++ ;
|
1193 |
|
|
xl_priv->tx_ring_head &= (XL_TX_RING_SIZE - 1) ;
|
1194 |
|
|
xl_priv->free_ring_entries-- ;
|
1195 |
|
|
|
1196 |
|
|
xl_priv->xl_tx_ring[tx_prev].dnnextptr = xl_priv->tx_ring_dma_addr + (sizeof (struct xl_tx_desc) * tx_head) ;
|
1197 |
|
|
|
1198 |
|
|
/* Sneaky, by doing a read on DnListPtr we can force the card to poll on the DnNextPtr */
|
1199 |
|
|
/* readl(xl_mmio + MMIO_DNLISTPTR) ; */
|
1200 |
|
|
|
1201 |
|
|
netif_wake_queue(dev) ;
|
1202 |
|
|
|
1203 |
|
|
spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
|
1204 |
|
|
|
1205 |
|
|
return 0;
|
1206 |
|
|
} else {
|
1207 |
|
|
spin_unlock_irqrestore(&xl_priv->xl_lock,flags) ;
|
1208 |
|
|
return 1;
|
1209 |
|
|
}
|
1210 |
|
|
|
1211 |
|
|
}
|
1212 |
|
|
|
1213 |
|
|
/*
|
1214 |
|
|
* The NIC has told us that a packet has been downloaded onto the card, we must
|
1215 |
|
|
* find out which packet it has done, clear the skb and information for the packet
|
1216 |
|
|
* then advance around the ring for all tranmitted packets
|
1217 |
|
|
*/
|
1218 |
|
|
|
1219 |
|
|
static void xl_dn_comp(struct net_device *dev)
|
1220 |
|
|
{
|
1221 |
|
|
struct xl_private *xl_priv=(struct xl_private *)dev->priv;
|
1222 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
1223 |
|
|
struct xl_tx_desc *txd ;
|
1224 |
|
|
|
1225 |
|
|
|
1226 |
|
|
if (xl_priv->tx_ring_tail == 255) {/* First time */
|
1227 |
|
|
xl_priv->xl_tx_ring[0].framestartheader = 0 ;
|
1228 |
|
|
xl_priv->xl_tx_ring[0].dnnextptr = 0 ;
|
1229 |
|
|
xl_priv->tx_ring_tail = 1 ;
|
1230 |
|
|
}
|
1231 |
|
|
|
1232 |
|
|
while (xl_priv->xl_tx_ring[xl_priv->tx_ring_tail].framestartheader & TXDNCOMPLETE ) {
|
1233 |
|
|
txd = &(xl_priv->xl_tx_ring[xl_priv->tx_ring_tail]) ;
|
1234 |
|
|
pci_unmap_single(xl_priv->pdev,txd->buffer, xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]->len, PCI_DMA_TODEVICE) ;
|
1235 |
|
|
txd->framestartheader = 0 ;
|
1236 |
|
|
txd->buffer = 0xdeadbeef ;
|
1237 |
|
|
txd->buffer_length = 0 ;
|
1238 |
|
|
dev_kfree_skb_irq(xl_priv->tx_ring_skb[xl_priv->tx_ring_tail]) ;
|
1239 |
|
|
xl_priv->tx_ring_tail++ ;
|
1240 |
|
|
xl_priv->tx_ring_tail &= (XL_TX_RING_SIZE - 1) ;
|
1241 |
|
|
xl_priv->free_ring_entries++ ;
|
1242 |
|
|
}
|
1243 |
|
|
|
1244 |
|
|
netif_wake_queue(dev) ;
|
1245 |
|
|
|
1246 |
|
|
writel(ACK_INTERRUPT | DNCOMPACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
|
1247 |
|
|
}
|
1248 |
|
|
|
1249 |
|
|
/*
|
1250 |
|
|
* Close the adapter properly.
|
1251 |
|
|
* This srb reply cannot be handled from interrupt context as we have
|
1252 |
|
|
* to free the interrupt from the driver.
|
1253 |
|
|
*/
|
1254 |
|
|
|
1255 |
|
|
static int xl_close(struct net_device *dev)
|
1256 |
|
|
{
|
1257 |
|
|
struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
|
1258 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
1259 |
|
|
unsigned long t ;
|
1260 |
|
|
|
1261 |
|
|
netif_stop_queue(dev) ;
|
1262 |
|
|
|
1263 |
|
|
/*
|
1264 |
|
|
* Close the adapter, need to stall the rx and tx queues.
|
1265 |
|
|
*/
|
1266 |
|
|
|
1267 |
|
|
writew(DNSTALL, xl_mmio + MMIO_COMMAND) ;
|
1268 |
|
|
t=jiffies;
|
1269 |
|
|
while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
|
1270 |
|
|
schedule();
|
1271 |
|
|
if(jiffies-t > 10*HZ) {
|
1272 |
|
|
printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNSTALL not responding.\n", dev->name);
|
1273 |
|
|
break ;
|
1274 |
|
|
}
|
1275 |
|
|
}
|
1276 |
|
|
writew(DNDISABLE, xl_mmio + MMIO_COMMAND) ;
|
1277 |
|
|
t=jiffies;
|
1278 |
|
|
while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
|
1279 |
|
|
schedule();
|
1280 |
|
|
if(jiffies-t > 10*HZ) {
|
1281 |
|
|
printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNDISABLE not responding.\n", dev->name);
|
1282 |
|
|
break ;
|
1283 |
|
|
}
|
1284 |
|
|
}
|
1285 |
|
|
writew(UPSTALL, xl_mmio + MMIO_COMMAND) ;
|
1286 |
|
|
t=jiffies;
|
1287 |
|
|
while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
|
1288 |
|
|
schedule();
|
1289 |
|
|
if(jiffies-t > 10*HZ) {
|
1290 |
|
|
printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPSTALL not responding.\n", dev->name);
|
1291 |
|
|
break ;
|
1292 |
|
|
}
|
1293 |
|
|
}
|
1294 |
|
|
|
1295 |
|
|
/* Turn off interrupts, we will still get the indication though
|
1296 |
|
|
* so we can trap it
|
1297 |
|
|
*/
|
1298 |
|
|
|
1299 |
|
|
writel(SETINTENABLE, xl_mmio + MMIO_COMMAND) ;
|
1300 |
|
|
|
1301 |
|
|
xl_srb_cmd(dev,CLOSE_NIC) ;
|
1302 |
|
|
|
1303 |
|
|
t=jiffies;
|
1304 |
|
|
while (!(readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_SRB)) {
|
1305 |
|
|
schedule();
|
1306 |
|
|
if(jiffies-t > 10*HZ) {
|
1307 |
|
|
printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-CLOSENIC not responding.\n", dev->name);
|
1308 |
|
|
break ;
|
1309 |
|
|
}
|
1310 |
|
|
}
|
1311 |
|
|
/* Read the srb response from the adapter */
|
1312 |
|
|
|
1313 |
|
|
writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD);
|
1314 |
|
|
if (readb(xl_mmio + MMIO_MACDATA) != CLOSE_NIC) {
|
1315 |
|
|
printk(KERN_INFO "%s: CLOSE_NIC did not get a CLOSE_NIC response \n",dev->name) ;
|
1316 |
|
|
} else {
|
1317 |
|
|
writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1318 |
|
|
if (readb(xl_mmio + MMIO_MACDATA)==0) {
|
1319 |
|
|
printk(KERN_INFO "%s: Adapter has been closed \n",dev->name) ;
|
1320 |
|
|
writew(ACK_INTERRUPT | SRBRACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
|
1321 |
|
|
|
1322 |
|
|
xl_freemem(dev) ;
|
1323 |
|
|
free_irq(dev->irq,dev) ;
|
1324 |
|
|
} else {
|
1325 |
|
|
printk(KERN_INFO "%s: Close nic command returned error code %02x\n",dev->name, readb(xl_mmio + MMIO_MACDATA)) ;
|
1326 |
|
|
}
|
1327 |
|
|
}
|
1328 |
|
|
|
1329 |
|
|
/* Reset the upload and download logic */
|
1330 |
|
|
|
1331 |
|
|
writew(UPRESET, xl_mmio + MMIO_COMMAND) ;
|
1332 |
|
|
t=jiffies;
|
1333 |
|
|
while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
|
1334 |
|
|
schedule();
|
1335 |
|
|
if(jiffies-t > 10*HZ) {
|
1336 |
|
|
printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-UPRESET not responding.\n", dev->name);
|
1337 |
|
|
break ;
|
1338 |
|
|
}
|
1339 |
|
|
}
|
1340 |
|
|
writew(DNRESET, xl_mmio + MMIO_COMMAND) ;
|
1341 |
|
|
t=jiffies;
|
1342 |
|
|
while (readw(xl_mmio + MMIO_INTSTATUS) & INTSTAT_CMD_IN_PROGRESS) {
|
1343 |
|
|
schedule();
|
1344 |
|
|
if(jiffies-t > 10*HZ) {
|
1345 |
|
|
printk(KERN_ERR "%s: 3COM 3C359 Velocity XL-DNRESET not responding.\n", dev->name);
|
1346 |
|
|
break ;
|
1347 |
|
|
}
|
1348 |
|
|
}
|
1349 |
|
|
xl_hw_reset(dev) ;
|
1350 |
|
|
return 0 ;
|
1351 |
|
|
}
|
1352 |
|
|
|
1353 |
|
|
static void xl_set_rx_mode(struct net_device *dev)
|
1354 |
|
|
{
|
1355 |
|
|
struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
|
1356 |
|
|
struct dev_mc_list *dmi ;
|
1357 |
|
|
unsigned char dev_mc_address[4] ;
|
1358 |
|
|
u16 options ;
|
1359 |
|
|
int i ;
|
1360 |
|
|
|
1361 |
|
|
if (dev->flags & IFF_PROMISC)
|
1362 |
|
|
options = 0x0004 ;
|
1363 |
|
|
else
|
1364 |
|
|
options = 0x0000 ;
|
1365 |
|
|
|
1366 |
|
|
if (options ^ xl_priv->xl_copy_all_options) { /* Changed, must send command */
|
1367 |
|
|
xl_priv->xl_copy_all_options = options ;
|
1368 |
|
|
xl_srb_cmd(dev, SET_RECEIVE_MODE) ;
|
1369 |
|
|
return ;
|
1370 |
|
|
}
|
1371 |
|
|
|
1372 |
|
|
dev_mc_address[0] = dev_mc_address[1] = dev_mc_address[2] = dev_mc_address[3] = 0 ;
|
1373 |
|
|
|
1374 |
|
|
for (i=0,dmi=dev->mc_list;i < dev->mc_count; i++,dmi = dmi->next) {
|
1375 |
|
|
dev_mc_address[0] |= dmi->dmi_addr[2] ;
|
1376 |
|
|
dev_mc_address[1] |= dmi->dmi_addr[3] ;
|
1377 |
|
|
dev_mc_address[2] |= dmi->dmi_addr[4] ;
|
1378 |
|
|
dev_mc_address[3] |= dmi->dmi_addr[5] ;
|
1379 |
|
|
}
|
1380 |
|
|
|
1381 |
|
|
if (memcmp(xl_priv->xl_functional_addr,dev_mc_address,4) != 0) { /* Options have changed, run the command */
|
1382 |
|
|
memcpy(xl_priv->xl_functional_addr, dev_mc_address,4) ;
|
1383 |
|
|
xl_srb_cmd(dev, SET_FUNC_ADDRESS) ;
|
1384 |
|
|
}
|
1385 |
|
|
return ;
|
1386 |
|
|
}
|
1387 |
|
|
|
1388 |
|
|
|
1389 |
|
|
/*
|
1390 |
|
|
* We issued an srb command and now we must read
|
1391 |
|
|
* the response from the completed command.
|
1392 |
|
|
*/
|
1393 |
|
|
|
1394 |
|
|
static void xl_srb_bh(struct net_device *dev)
|
1395 |
|
|
{
|
1396 |
|
|
struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
|
1397 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
1398 |
|
|
u8 srb_cmd, ret_code ;
|
1399 |
|
|
int i ;
|
1400 |
|
|
|
1401 |
|
|
writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1402 |
|
|
srb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
|
1403 |
|
|
writel((MEM_BYTE_READ | 0xd0000 | xl_priv->srb) +2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1404 |
|
|
ret_code = readb(xl_mmio + MMIO_MACDATA) ;
|
1405 |
|
|
|
1406 |
|
|
/* Ret_code is standard across all commands */
|
1407 |
|
|
|
1408 |
|
|
switch (ret_code) {
|
1409 |
|
|
case 1:
|
1410 |
|
|
printk(KERN_INFO "%s: Command: %d - Invalid Command code\n",dev->name,srb_cmd) ;
|
1411 |
|
|
break ;
|
1412 |
|
|
case 4:
|
1413 |
|
|
printk(KERN_INFO "%s: Command: %d - Adapter is closed, must be open for this command \n",dev->name,srb_cmd) ;
|
1414 |
|
|
break ;
|
1415 |
|
|
|
1416 |
|
|
case 6:
|
1417 |
|
|
printk(KERN_INFO "%s: Command: %d - Options Invalid for command \n",dev->name,srb_cmd) ;
|
1418 |
|
|
break ;
|
1419 |
|
|
|
1420 |
|
|
case 0: /* Successful command execution */
|
1421 |
|
|
switch (srb_cmd) {
|
1422 |
|
|
case READ_LOG: /* Returns 14 bytes of data from the NIC */
|
1423 |
|
|
if(xl_priv->xl_message_level)
|
1424 |
|
|
printk(KERN_INFO "%s: READ.LOG 14 bytes of data ",dev->name) ;
|
1425 |
|
|
/*
|
1426 |
|
|
* We still have to read the log even if message_level = 0 and we don't want
|
1427 |
|
|
* to see it
|
1428 |
|
|
*/
|
1429 |
|
|
for (i=0;i<14;i++) {
|
1430 |
|
|
writel(MEM_BYTE_READ | 0xd0000 | xl_priv->srb | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1431 |
|
|
if(xl_priv->xl_message_level)
|
1432 |
|
|
printk("%02x:",readb(xl_mmio + MMIO_MACDATA)) ;
|
1433 |
|
|
}
|
1434 |
|
|
printk("\n") ;
|
1435 |
|
|
break ;
|
1436 |
|
|
case SET_FUNC_ADDRESS:
|
1437 |
|
|
if(xl_priv->xl_message_level)
|
1438 |
|
|
printk(KERN_INFO "%s: Functional Address Set \n",dev->name) ;
|
1439 |
|
|
break ;
|
1440 |
|
|
case CLOSE_NIC:
|
1441 |
|
|
if(xl_priv->xl_message_level)
|
1442 |
|
|
printk(KERN_INFO "%s: Received CLOSE_NIC interrupt in interrupt handler \n",dev->name) ;
|
1443 |
|
|
break ;
|
1444 |
|
|
case SET_MULTICAST_MODE:
|
1445 |
|
|
if(xl_priv->xl_message_level)
|
1446 |
|
|
printk(KERN_INFO "%s: Multicast options successfully changed\n",dev->name) ;
|
1447 |
|
|
break ;
|
1448 |
|
|
case SET_RECEIVE_MODE:
|
1449 |
|
|
if(xl_priv->xl_message_level) {
|
1450 |
|
|
if (xl_priv->xl_copy_all_options == 0x0004)
|
1451 |
|
|
printk(KERN_INFO "%s: Entering promiscuous mode \n", dev->name) ;
|
1452 |
|
|
else
|
1453 |
|
|
printk(KERN_INFO "%s: Entering normal receive mode \n",dev->name) ;
|
1454 |
|
|
}
|
1455 |
|
|
break ;
|
1456 |
|
|
|
1457 |
|
|
} /* switch */
|
1458 |
|
|
break ;
|
1459 |
|
|
} /* switch */
|
1460 |
|
|
return ;
|
1461 |
|
|
}
|
1462 |
|
|
|
1463 |
|
|
static struct net_device_stats * xl_get_stats(struct net_device *dev)
|
1464 |
|
|
{
|
1465 |
|
|
struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
|
1466 |
|
|
return (struct net_device_stats *) &xl_priv->xl_stats;
|
1467 |
|
|
}
|
1468 |
|
|
|
1469 |
|
|
static int xl_set_mac_address (struct net_device *dev, void *addr)
|
1470 |
|
|
{
|
1471 |
|
|
struct sockaddr *saddr = addr ;
|
1472 |
|
|
struct xl_private *xl_priv = (struct xl_private *)dev->priv ;
|
1473 |
|
|
|
1474 |
|
|
if (netif_running(dev)) {
|
1475 |
|
|
printk(KERN_WARNING "%s: Cannot set mac/laa address while card is open\n", dev->name) ;
|
1476 |
|
|
return -EIO ;
|
1477 |
|
|
}
|
1478 |
|
|
|
1479 |
|
|
memcpy(xl_priv->xl_laa, saddr->sa_data,dev->addr_len) ;
|
1480 |
|
|
|
1481 |
|
|
if (xl_priv->xl_message_level) {
|
1482 |
|
|
printk(KERN_INFO "%s: MAC/LAA Set to = %x.%x.%x.%x.%x.%x\n",dev->name, xl_priv->xl_laa[0],
|
1483 |
|
|
xl_priv->xl_laa[1], xl_priv->xl_laa[2],
|
1484 |
|
|
xl_priv->xl_laa[3], xl_priv->xl_laa[4],
|
1485 |
|
|
xl_priv->xl_laa[5]);
|
1486 |
|
|
}
|
1487 |
|
|
|
1488 |
|
|
return 0 ;
|
1489 |
|
|
}
|
1490 |
|
|
|
1491 |
|
|
static void xl_arb_cmd(struct net_device *dev)
|
1492 |
|
|
{
|
1493 |
|
|
struct xl_private *xl_priv = (struct xl_private *) dev->priv;
|
1494 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
1495 |
|
|
u8 arb_cmd ;
|
1496 |
|
|
u16 lan_status, lan_status_diff ;
|
1497 |
|
|
|
1498 |
|
|
writel( ( MEM_BYTE_READ | 0xD0000 | xl_priv->arb), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1499 |
|
|
arb_cmd = readb(xl_mmio + MMIO_MACDATA) ;
|
1500 |
|
|
|
1501 |
|
|
if (arb_cmd == RING_STATUS_CHANGE) { /* Ring.Status.Change */
|
1502 |
|
|
writel( ( (MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1503 |
|
|
|
1504 |
|
|
printk(KERN_INFO "%s: Ring Status Change: New Status = %04x\n", dev->name, ntohs(readw(xl_mmio + MMIO_MACDATA) )) ;
|
1505 |
|
|
|
1506 |
|
|
lan_status = ntohs(readw(xl_mmio + MMIO_MACDATA));
|
1507 |
|
|
|
1508 |
|
|
/* Acknowledge interrupt, this tells nic we are done with the arb */
|
1509 |
|
|
writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
|
1510 |
|
|
|
1511 |
|
|
lan_status_diff = xl_priv->xl_lan_status ^ lan_status ;
|
1512 |
|
|
|
1513 |
|
|
if (lan_status_diff & (LSC_LWF | LSC_ARW | LSC_FPE | LSC_RR) ) {
|
1514 |
|
|
if (lan_status_diff & LSC_LWF)
|
1515 |
|
|
printk(KERN_WARNING "%s: Short circuit detected on the lobe\n",dev->name);
|
1516 |
|
|
if (lan_status_diff & LSC_ARW)
|
1517 |
|
|
printk(KERN_WARNING "%s: Auto removal error\n",dev->name);
|
1518 |
|
|
if (lan_status_diff & LSC_FPE)
|
1519 |
|
|
printk(KERN_WARNING "%s: FDX Protocol Error\n",dev->name);
|
1520 |
|
|
if (lan_status_diff & LSC_RR)
|
1521 |
|
|
printk(KERN_WARNING "%s: Force remove MAC frame received\n",dev->name);
|
1522 |
|
|
|
1523 |
|
|
/* Adapter has been closed by the hardware */
|
1524 |
|
|
|
1525 |
|
|
netif_stop_queue(dev);
|
1526 |
|
|
xl_freemem(dev) ;
|
1527 |
|
|
free_irq(dev->irq,dev);
|
1528 |
|
|
|
1529 |
|
|
printk(KERN_WARNING "%s: Adapter has been closed \n", dev->name) ;
|
1530 |
|
|
} /* If serious error */
|
1531 |
|
|
|
1532 |
|
|
if (xl_priv->xl_message_level) {
|
1533 |
|
|
if (lan_status_diff & LSC_SIG_LOSS)
|
1534 |
|
|
printk(KERN_WARNING "%s: No receive signal detected \n", dev->name) ;
|
1535 |
|
|
if (lan_status_diff & LSC_HARD_ERR)
|
1536 |
|
|
printk(KERN_INFO "%s: Beaconing \n",dev->name);
|
1537 |
|
|
if (lan_status_diff & LSC_SOFT_ERR)
|
1538 |
|
|
printk(KERN_WARNING "%s: Adapter transmitted Soft Error Report Mac Frame \n",dev->name);
|
1539 |
|
|
if (lan_status_diff & LSC_TRAN_BCN)
|
1540 |
|
|
printk(KERN_INFO "%s: We are tranmitting the beacon, aaah\n",dev->name);
|
1541 |
|
|
if (lan_status_diff & LSC_SS)
|
1542 |
|
|
printk(KERN_INFO "%s: Single Station on the ring \n", dev->name);
|
1543 |
|
|
if (lan_status_diff & LSC_RING_REC)
|
1544 |
|
|
printk(KERN_INFO "%s: Ring recovery ongoing\n",dev->name);
|
1545 |
|
|
if (lan_status_diff & LSC_FDX_MODE)
|
1546 |
|
|
printk(KERN_INFO "%s: Operating in FDX mode\n",dev->name);
|
1547 |
|
|
}
|
1548 |
|
|
|
1549 |
|
|
if (lan_status_diff & LSC_CO) {
|
1550 |
|
|
if (xl_priv->xl_message_level)
|
1551 |
|
|
printk(KERN_INFO "%s: Counter Overflow \n", dev->name);
|
1552 |
|
|
/* Issue READ.LOG command */
|
1553 |
|
|
xl_srb_cmd(dev, READ_LOG) ;
|
1554 |
|
|
}
|
1555 |
|
|
|
1556 |
|
|
/* There is no command in the tech docs to issue the read_sr_counters */
|
1557 |
|
|
if (lan_status_diff & LSC_SR_CO) {
|
1558 |
|
|
if (xl_priv->xl_message_level)
|
1559 |
|
|
printk(KERN_INFO "%s: Source routing counters overflow\n", dev->name);
|
1560 |
|
|
}
|
1561 |
|
|
|
1562 |
|
|
xl_priv->xl_lan_status = lan_status ;
|
1563 |
|
|
|
1564 |
|
|
} /* Lan.change.status */
|
1565 |
|
|
else if ( arb_cmd == RECEIVE_DATA) { /* Received.Data */
|
1566 |
|
|
#if XL_DEBUG
|
1567 |
|
|
printk(KERN_INFO "Received.Data \n") ;
|
1568 |
|
|
#endif
|
1569 |
|
|
writel( ((MEM_WORD_READ | 0xD0000 | xl_priv->arb) + 6), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1570 |
|
|
xl_priv->mac_buffer = ntohs(readw(xl_mmio + MMIO_MACDATA)) ;
|
1571 |
|
|
|
1572 |
|
|
/* Now we are going to be really basic here and not do anything
|
1573 |
|
|
* with the data at all. The tech docs do not give me enough
|
1574 |
|
|
* information to calculate the buffers properly so we're
|
1575 |
|
|
* just going to tell the nic that we've dealt with the frame
|
1576 |
|
|
* anyway.
|
1577 |
|
|
*/
|
1578 |
|
|
|
1579 |
|
|
dev->last_rx = jiffies ;
|
1580 |
|
|
/* Acknowledge interrupt, this tells nic we are done with the arb */
|
1581 |
|
|
writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK, xl_mmio + MMIO_COMMAND) ;
|
1582 |
|
|
|
1583 |
|
|
/* Is the ASB free ? */
|
1584 |
|
|
|
1585 |
|
|
xl_priv->asb_queued = 0 ;
|
1586 |
|
|
writel( ((MEM_BYTE_READ | 0xD0000 | xl_priv->asb) + 2), xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1587 |
|
|
if (readb(xl_mmio + MMIO_MACDATA) != 0xff) {
|
1588 |
|
|
xl_priv->asb_queued = 1 ;
|
1589 |
|
|
|
1590 |
|
|
xl_wait_misr_flags(dev) ;
|
1591 |
|
|
|
1592 |
|
|
writel(MEM_BYTE_WRITE | MF_ASBFR, xl_mmio + MMIO_MAC_ACCESS_CMD);
|
1593 |
|
|
writeb(0xff, xl_mmio + MMIO_MACDATA) ;
|
1594 |
|
|
writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1595 |
|
|
writeb(MISR_ASBFR, xl_mmio + MMIO_MACDATA) ;
|
1596 |
|
|
return ;
|
1597 |
|
|
/* Drop out and wait for the bottom half to be run */
|
1598 |
|
|
}
|
1599 |
|
|
|
1600 |
|
|
xl_asb_cmd(dev) ;
|
1601 |
|
|
|
1602 |
|
|
} else {
|
1603 |
|
|
printk(KERN_WARNING "%s: Received unknown arb (xl_priv) command: %02x \n",dev->name,arb_cmd) ;
|
1604 |
|
|
}
|
1605 |
|
|
|
1606 |
|
|
/* Acknowledge the arb interrupt */
|
1607 |
|
|
|
1608 |
|
|
writel(ACK_INTERRUPT | ARBCACK | LATCH_ACK , xl_mmio + MMIO_COMMAND) ;
|
1609 |
|
|
|
1610 |
|
|
return ;
|
1611 |
|
|
}
|
1612 |
|
|
|
1613 |
|
|
|
1614 |
|
|
/*
|
1615 |
|
|
* There is only one asb command, but we can get called from different
|
1616 |
|
|
* places.
|
1617 |
|
|
*/
|
1618 |
|
|
|
1619 |
|
|
static void xl_asb_cmd(struct net_device *dev)
|
1620 |
|
|
{
|
1621 |
|
|
struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
|
1622 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
1623 |
|
|
|
1624 |
|
|
if (xl_priv->asb_queued == 1)
|
1625 |
|
|
writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
|
1626 |
|
|
|
1627 |
|
|
writel(MEM_BYTE_WRITE | 0xd0000 | xl_priv->asb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1628 |
|
|
writeb(0x81, xl_mmio + MMIO_MACDATA) ;
|
1629 |
|
|
|
1630 |
|
|
writel(MEM_WORD_WRITE | 0xd0000 | xl_priv->asb | 6, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1631 |
|
|
writew(ntohs(xl_priv->mac_buffer), xl_mmio + MMIO_MACDATA) ;
|
1632 |
|
|
|
1633 |
|
|
xl_wait_misr_flags(dev) ;
|
1634 |
|
|
|
1635 |
|
|
writel(MEM_BYTE_WRITE | MF_RASB, xl_mmio + MMIO_MAC_ACCESS_CMD);
|
1636 |
|
|
writeb(0xff, xl_mmio + MMIO_MACDATA) ;
|
1637 |
|
|
|
1638 |
|
|
writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1639 |
|
|
writeb(MISR_RASB, xl_mmio + MMIO_MACDATA) ;
|
1640 |
|
|
|
1641 |
|
|
xl_priv->asb_queued = 2 ;
|
1642 |
|
|
|
1643 |
|
|
return ;
|
1644 |
|
|
}
|
1645 |
|
|
|
1646 |
|
|
/*
|
1647 |
|
|
* This will only get called if there was an error
|
1648 |
|
|
* from the asb cmd.
|
1649 |
|
|
*/
|
1650 |
|
|
static void xl_asb_bh(struct net_device *dev)
|
1651 |
|
|
{
|
1652 |
|
|
struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
|
1653 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
1654 |
|
|
u8 ret_code ;
|
1655 |
|
|
|
1656 |
|
|
writel(MMIO_BYTE_READ | 0xd0000 | xl_priv->asb | 2, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1657 |
|
|
ret_code = readb(xl_mmio + MMIO_MACDATA) ;
|
1658 |
|
|
switch (ret_code) {
|
1659 |
|
|
case 0x01:
|
1660 |
|
|
printk(KERN_INFO "%s: ASB Command, unrecognized command code \n",dev->name) ;
|
1661 |
|
|
break ;
|
1662 |
|
|
case 0x26:
|
1663 |
|
|
printk(KERN_INFO "%s: ASB Command, unexpected receive buffer \n", dev->name) ;
|
1664 |
|
|
break ;
|
1665 |
|
|
case 0x40:
|
1666 |
|
|
printk(KERN_INFO "%s: ASB Command, Invalid Station ID \n", dev->name) ;
|
1667 |
|
|
break ;
|
1668 |
|
|
}
|
1669 |
|
|
xl_priv->asb_queued = 0 ;
|
1670 |
|
|
writel(ACK_INTERRUPT | LATCH_ACK | ASBFACK, xl_mmio + MMIO_COMMAND) ;
|
1671 |
|
|
return ;
|
1672 |
|
|
}
|
1673 |
|
|
|
1674 |
|
|
/*
|
1675 |
|
|
* Issue srb commands to the nic
|
1676 |
|
|
*/
|
1677 |
|
|
|
1678 |
|
|
static void xl_srb_cmd(struct net_device *dev, int srb_cmd)
|
1679 |
|
|
{
|
1680 |
|
|
struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
|
1681 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
1682 |
|
|
|
1683 |
|
|
switch (srb_cmd) {
|
1684 |
|
|
case READ_LOG:
|
1685 |
|
|
writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1686 |
|
|
writeb(READ_LOG, xl_mmio + MMIO_MACDATA) ;
|
1687 |
|
|
break;
|
1688 |
|
|
|
1689 |
|
|
case CLOSE_NIC:
|
1690 |
|
|
writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1691 |
|
|
writeb(CLOSE_NIC, xl_mmio + MMIO_MACDATA) ;
|
1692 |
|
|
break ;
|
1693 |
|
|
|
1694 |
|
|
case SET_RECEIVE_MODE:
|
1695 |
|
|
writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1696 |
|
|
writeb(SET_RECEIVE_MODE, xl_mmio + MMIO_MACDATA) ;
|
1697 |
|
|
writel(MEM_WORD_WRITE | 0xD0000 | xl_priv->srb | 4, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1698 |
|
|
writew(xl_priv->xl_copy_all_options, xl_mmio + MMIO_MACDATA) ;
|
1699 |
|
|
break ;
|
1700 |
|
|
|
1701 |
|
|
case SET_FUNC_ADDRESS:
|
1702 |
|
|
writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1703 |
|
|
writeb(SET_FUNC_ADDRESS, xl_mmio + MMIO_MACDATA) ;
|
1704 |
|
|
writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 6 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1705 |
|
|
writeb(xl_priv->xl_functional_addr[0], xl_mmio + MMIO_MACDATA) ;
|
1706 |
|
|
writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 7 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1707 |
|
|
writeb(xl_priv->xl_functional_addr[1], xl_mmio + MMIO_MACDATA) ;
|
1708 |
|
|
writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 8 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1709 |
|
|
writeb(xl_priv->xl_functional_addr[2], xl_mmio + MMIO_MACDATA) ;
|
1710 |
|
|
writel(MEM_BYTE_WRITE | 0xD0000 | xl_priv->srb | 9 , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1711 |
|
|
writeb(xl_priv->xl_functional_addr[3], xl_mmio + MMIO_MACDATA) ;
|
1712 |
|
|
break ;
|
1713 |
|
|
} /* switch */
|
1714 |
|
|
|
1715 |
|
|
|
1716 |
|
|
xl_wait_misr_flags(dev) ;
|
1717 |
|
|
|
1718 |
|
|
/* Write 0xff to the CSRB flag */
|
1719 |
|
|
writel(MEM_BYTE_WRITE | MF_CSRB , xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1720 |
|
|
writeb(0xFF, xl_mmio + MMIO_MACDATA) ;
|
1721 |
|
|
/* Set csrb bit in MISR register to process command */
|
1722 |
|
|
writel(MMIO_BYTE_WRITE | MISR_SET, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1723 |
|
|
writeb(MISR_CSRB, xl_mmio + MMIO_MACDATA) ;
|
1724 |
|
|
xl_priv->srb_queued = 1 ;
|
1725 |
|
|
|
1726 |
|
|
return ;
|
1727 |
|
|
}
|
1728 |
|
|
|
1729 |
|
|
/*
|
1730 |
|
|
* This is nasty, to use the MISR command you have to wait for 6 memory locations
|
1731 |
|
|
* to be zero. This is the way the driver does on other OS'es so we should be ok with
|
1732 |
|
|
* the empty loop.
|
1733 |
|
|
*/
|
1734 |
|
|
|
1735 |
|
|
static void xl_wait_misr_flags(struct net_device *dev)
|
1736 |
|
|
{
|
1737 |
|
|
struct xl_private *xl_priv = (struct xl_private *) dev->priv ;
|
1738 |
|
|
u8 * xl_mmio = xl_priv->xl_mmio ;
|
1739 |
|
|
|
1740 |
|
|
int i ;
|
1741 |
|
|
|
1742 |
|
|
writel(MMIO_BYTE_READ | MISR_RW, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1743 |
|
|
if (readb(xl_mmio + MMIO_MACDATA) != 0) { /* Misr not clear */
|
1744 |
|
|
for (i=0; i<6; i++) {
|
1745 |
|
|
writel(MEM_BYTE_READ | 0xDFFE0 | i, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1746 |
|
|
while (readb(xl_mmio + MMIO_MACDATA) != 0 ) {} ; /* Empty Loop */
|
1747 |
|
|
}
|
1748 |
|
|
}
|
1749 |
|
|
|
1750 |
|
|
writel(MMIO_BYTE_WRITE | MISR_AND, xl_mmio + MMIO_MAC_ACCESS_CMD) ;
|
1751 |
|
|
writeb(0x80, xl_mmio + MMIO_MACDATA) ;
|
1752 |
|
|
|
1753 |
|
|
return ;
|
1754 |
|
|
}
|
1755 |
|
|
|
1756 |
|
|
/*
|
1757 |
|
|
* Change mtu size, this should work the same as olympic
|
1758 |
|
|
*/
|
1759 |
|
|
|
1760 |
|
|
static int xl_change_mtu(struct net_device *dev, int mtu)
|
1761 |
|
|
{
|
1762 |
|
|
struct xl_private *xl_priv = (struct xl_private *) dev->priv;
|
1763 |
|
|
u16 max_mtu ;
|
1764 |
|
|
|
1765 |
|
|
if (xl_priv->xl_ring_speed == 4)
|
1766 |
|
|
max_mtu = 4500 ;
|
1767 |
|
|
else
|
1768 |
|
|
max_mtu = 18000 ;
|
1769 |
|
|
|
1770 |
|
|
if (mtu > max_mtu)
|
1771 |
|
|
return -EINVAL ;
|
1772 |
|
|
if (mtu < 100)
|
1773 |
|
|
return -EINVAL ;
|
1774 |
|
|
|
1775 |
|
|
dev->mtu = mtu ;
|
1776 |
|
|
xl_priv->pkt_buf_sz = mtu + TR_HLEN ;
|
1777 |
|
|
|
1778 |
|
|
return 0 ;
|
1779 |
|
|
}
|
1780 |
|
|
|
1781 |
|
|
static void __devexit xl_remove_one (struct pci_dev *pdev)
|
1782 |
|
|
{
|
1783 |
|
|
struct net_device *dev = pci_get_drvdata(pdev);
|
1784 |
|
|
struct xl_private *xl_priv=(struct xl_private *)dev->priv;
|
1785 |
|
|
|
1786 |
|
|
unregister_trdev(dev);
|
1787 |
|
|
iounmap(xl_priv->xl_mmio) ;
|
1788 |
|
|
pci_release_regions(pdev) ;
|
1789 |
|
|
pci_set_drvdata(pdev,NULL) ;
|
1790 |
|
|
kfree(dev);
|
1791 |
|
|
return ;
|
1792 |
|
|
}
|
1793 |
|
|
|
1794 |
|
|
static struct pci_driver xl_3c359_driver = {
|
1795 |
|
|
name: "3c359",
|
1796 |
|
|
id_table: xl_pci_tbl,
|
1797 |
|
|
probe: xl_probe,
|
1798 |
|
|
remove: __devexit_p(xl_remove_one),
|
1799 |
|
|
};
|
1800 |
|
|
|
1801 |
|
|
static int __init xl_pci_init (void)
|
1802 |
|
|
{
|
1803 |
|
|
return pci_module_init (&xl_3c359_driver);
|
1804 |
|
|
}
|
1805 |
|
|
|
1806 |
|
|
|
1807 |
|
|
static void __exit xl_pci_cleanup (void)
|
1808 |
|
|
{
|
1809 |
|
|
pci_unregister_driver (&xl_3c359_driver);
|
1810 |
|
|
}
|
1811 |
|
|
|
1812 |
|
|
module_init(xl_pci_init);
|
1813 |
|
|
module_exit(xl_pci_cleanup);
|
1814 |
|
|
|
1815 |
|
|
MODULE_LICENSE("GPL") ;
|