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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [net/] [wan/] [hd64570.h] - Blame information for rev 1275

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#ifndef __HD64570_H
#define __HD64570_H
 
/* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)
   and 1 (64180 MPU). For modes 2 and 3, XOR the address with 0x01.
 
   Source: HD64570 SCA User's Manual
*/
 
 
 
/* SCA Control Registers */
#define LPR    0x00             /* Low Power */
 
/* Wait controller registers */
#define PABR0  0x02             /* Physical Address Boundary 0 */
#define PABR1  0x03             /* Physical Address Boundary 1 */
#define WCRL   0x04             /* Wait Control L */
#define WCRM   0x05             /* Wait Control M */
#define WCRH   0x06             /* Wait Control H */
 
#define PCR    0x08             /* DMA Priority Control */
#define DMER   0x09             /* DMA Master Enable */
 
 
/* Interrupt registers */
#define ISR0   0x10             /* Interrupt Status 0  */
#define ISR1   0x11             /* Interrupt Status 1  */
#define ISR2   0x12             /* Interrupt Status 2  */
 
#define IER0   0x14             /* Interrupt Enable 0  */
#define IER1   0x15             /* Interrupt Enable 1  */
#define IER2   0x16             /* Interrupt Enable 2  */
 
#define ITCR   0x18             /* Interrupt Control */
#define IVR    0x1A             /* Interrupt Vector */
#define IMVR   0x1C             /* Interrupt Modified Vector */
 
 
 
/* MSCI channel (port) 0 registers - offset 0x20
   MSCI channel (port) 1 registers - offset 0x40 */
 
#define MSCI0_OFFSET 0x20
#define MSCI1_OFFSET 0x40
 
#define TRBL   0x00             /* TX/RX buffer L */ 
#define TRBH   0x01             /* TX/RX buffer H */ 
#define ST0    0x02             /* Status 0 */
#define ST1    0x03             /* Status 1 */
#define ST2    0x04             /* Status 2 */
#define ST3    0x05             /* Status 3 */
#define FST    0x06             /* Frame Status  */
#define IE0    0x08             /* Interrupt Enable 0 */
#define IE1    0x09             /* Interrupt Enable 1 */
#define IE2    0x0A             /* Interrupt Enable 2 */
#define FIE    0x0B             /* Frame Interrupt Enable  */
#define CMD    0x0C             /* Command */
#define MD0    0x0E             /* Mode 0 */
#define MD1    0x0F             /* Mode 1 */
#define MD2    0x10             /* Mode 2 */
#define CTL    0x11             /* Control */
#define SA0    0x12             /* Sync/Address 0 */
#define SA1    0x13             /* Sync/Address 1 */
#define IDL    0x14             /* Idle Pattern */
#define TMC    0x15             /* Time Constant */
#define RXS    0x16             /* RX Clock Source */
#define TXS    0x17             /* TX Clock Source */
#define TRC0   0x18             /* TX Ready Control 0 */ 
#define TRC1   0x19             /* TX Ready Control 1 */ 
#define RRC    0x1A             /* RX Ready Control */ 
#define CST0   0x1C             /* Current Status 0 */
#define CST1   0x1D             /* Current Status 1 */
 
 
/* Timer channel 0 (port 0 RX) registers - offset 0x60
   Timer channel 1 (port 0 TX) registers - offset 0x68
   Timer channel 2 (port 1 RX) registers - offset 0x70
   Timer channel 3 (port 1 TX) registers - offset 0x78
*/
 
#define TIMER0RX_OFFSET 0x60
#define TIMER0TX_OFFSET 0x68
#define TIMER1RX_OFFSET 0x70
#define TIMER1TX_OFFSET 0x78
 
#define TCNTL  0x00             /* Up-counter L */
#define TCNTH  0x01             /* Up-counter H */
#define TCONRL 0x02             /* Constant L */
#define TCONRH 0x03             /* Constant H */
#define TCSR   0x04             /* Control/Status */
#define TEPR   0x05             /* Expand Prescale */
 
 
 
/* DMA channel 0 (port 0 RX) registers - offset 0x80
   DMA channel 1 (port 0 TX) registers - offset 0xA0
   DMA channel 2 (port 1 RX) registers - offset 0xC0
   DMA channel 3 (port 1 TX) registers - offset 0xE0
*/
 
#define DMAC0RX_OFFSET 0x80
#define DMAC0TX_OFFSET 0xA0
#define DMAC1RX_OFFSET 0xC0
#define DMAC1TX_OFFSET 0xE0
 
#define BARL   0x00             /* Buffer Address L (chained block) */
#define BARH   0x01             /* Buffer Address H (chained block) */
#define BARB   0x02             /* Buffer Address B (chained block) */
 
#define DARL   0x00             /* RX Destination Addr L (single block) */
#define DARH   0x01             /* RX Destination Addr H (single block) */
#define DARB   0x02             /* RX Destination Addr B (single block) */
 
#define SARL   0x04             /* TX Source Address L (single block) */
#define SARH   0x05             /* TX Source Address H (single block) */
#define SARB   0x06             /* TX Source Address B (single block) */
 
#define CPB    0x06             /* Chain Pointer Base (chained block) */
 
#define CDAL   0x08             /* Current Descriptor Addr L (chained block) */
#define CDAH   0x09             /* Current Descriptor Addr H (chained block) */
#define EDAL   0x0A             /* Error Descriptor Addr L (chained block) */
#define EDAH   0x0B             /* Error Descriptor Addr H (chained block) */
#define BFLL   0x0C             /* RX Receive Buffer Length L (chained block)*/
#define BFLH   0x0D             /* RX Receive Buffer Length H (chained block)*/
#define BCRL   0x0E             /* Byte Count L */
#define BCRH   0x0F             /* Byte Count H */
#define DSR    0x10             /* DMA Status */
#define DSR_RX(node) (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
#define DSR_TX(node) (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
#define DMR    0x11             /* DMA Mode */
#define DMR_RX(node) (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
#define DMR_TX(node) (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
#define FCT    0x13             /* Frame End Interrupt Counter */
#define FCT_RX(node) (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
#define FCT_TX(node) (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
#define DIR    0x14             /* DMA Interrupt Enable */
#define DIR_RX(node) (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
#define DIR_TX(node) (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
#define DCR    0x15             /* DMA Command  */
#define DCR_RX(node) (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))
#define DCR_TX(node) (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))
 
 
 
 
/* Descriptor Structure */
 
typedef struct {
        u16 cp;                 /* Chain Pointer */
        u32 bp;                 /* Buffer Pointer (24 bits) */
        u16 len;                /* Data Length */
        u8 stat;                /* Status */
        u8 unused;              /* pads to 2-byte boundary */
}__attribute__ ((packed)) pkt_desc;
 
 
/* Packet Descriptor Status bits */
 
#define ST_TX_EOM     0x80      /* End of frame */
#define ST_TX_EOT     0x01      /* End of transmition */
 
#define ST_RX_EOM     0x80      /* End of frame */
#define ST_RX_SHORT   0x40      /* Short frame */
#define ST_RX_ABORT   0x20      /* Abort */
#define ST_RX_RESBIT  0x10      /* Residual bit */
#define ST_RX_OVERRUN 0x08      /* Overrun */
#define ST_RX_CRC     0x04      /* CRC */
 
#define ST_ERROR_MASK 0x7C
 
#define DIR_EOTE      0x80      /* Transfer completed */
#define DIR_EOME      0x40      /* Frame Transfer Completed (chained-block) */
#define DIR_BOFE      0x20      /* Buffer Overflow/Underflow (chained-block)*/
#define DIR_COFE      0x10      /* Counter Overflow (chained-block) */
 
 
#define DSR_EOT       0x80      /* Transfer completed */
#define DSR_EOM       0x40      /* Frame Transfer Completed (chained-block) */
#define DSR_BOF       0x20      /* Buffer Overflow/Underflow (chained-block)*/
#define DSR_COF       0x10      /* Counter Overflow (chained-block) */
#define DSR_DE        0x02      /* DMA Enable */
#define DSR_DWE       0x01      /* DMA Write Disable */
 
/* DMA Master Enable Register (DMER) bits */
#define DMER_DME      0x80      /* DMA Master Enable */
 
 
#define CMD_RESET     0x21      /* Reset Channel */
#define CMD_TX_ENABLE 0x02      /* Start transmitter */
#define CMD_RX_ENABLE 0x12      /* Start receiver */
 
#define MD0_HDLC      0x80      /* Bit-sync HDLC mode */
#define MD0_CRC_ENA   0x04      /* Enable CRC code calculation */
#define MD0_CRC_CCITT 0x02      /* CCITT CRC instead of CRC-16 */
#define MD0_CRC_PR1   0x01      /* Initial all-ones instead of all-zeros */
 
#define MD0_CRC_NONE  0x00
#define MD0_CRC_16_0  0x04
#define MD0_CRC_16    0x05
#define MD0_CRC_ITU_0 0x06
#define MD0_CRC_ITU   0x07
 
#define MD2_NRZ       0x00
#define MD2_NRZI      0x20
#define MD2_MANCHESTER 0x80
#define MD2_FM_MARK   0xA0
#define MD2_FM_SPACE  0xC0
#define MD2_LOOPBACK  0x03      /* Local data Loopback */
 
#define CTL_NORTS     0x01
#define CTL_IDLE      0x10      /* Transmit an idle pattern */
#define CTL_UDRNC     0x20      /* Idle after CRC or FCS+flag transmition */
 
#define ST0_TXRDY     0x02      /* TX ready */
#define ST0_RXRDY     0x01      /* RX ready */
 
#define ST1_UDRN      0x80      /* MSCI TX underrun */
 
#define ST3_CTS       0x08      /* modem input - /CTS */
#define ST3_DCD       0x04      /* modem input - /DCD */
 
#define IE0_TXINT     0x80      /* TX INT MSCI interrupt enable */
#define IE1_UDRN      0x80      /* TX underrun MSCI interrupt enable */
 
#define DCR_ABORT     0x01      /* Software abort command */
#define DCR_CLEAR_EOF 0x02      /* Clear EOF interrupt */
 
/* TX and RX Clock Source - RXS and TXS */
#define CLK_BRG_MASK  0x0F
#define CLK_LINE_RX   0x00      /* TX/RX clock line input */
#define CLK_LINE_TX   0x00      /* TX/RX line input */
#define CLK_BRG_RX    0x40      /* internal baud rate generator */
#define CLK_BRG_TX    0x40      /* internal baud rate generator */
#define CLK_RXCLK_TX  0x60      /* TX clock from RX clock */
 
#endif

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[/] [or1k/] [trunk/] [linux/] [linux-2.4/] [drivers/] [net/] [wan/] [hd64570.h] - Blame information for rev 1275

Line No.	Rev	Author	Line
1	1275	phoenix	`#ifndef __HD64570_H`
2			`#define __HD64570_H`
3
4			`/* SCA HD64570 register definitions - all addresses for mode 0 (8086 MPU)`
5			`and 1 (64180 MPU). For modes 2 and 3, XOR the address with 0x01.`
6
7			`Source: HD64570 SCA User's Manual`
8			`*/`
9
10
11
12			`/* SCA Control Registers */`
13			`#define LPR 0x00 /* Low Power */`
14
15			`/* Wait controller registers */`
16			`#define PABR0 0x02 /* Physical Address Boundary 0 */`
17			`#define PABR1 0x03 /* Physical Address Boundary 1 */`
18			`#define WCRL 0x04 /* Wait Control L */`
19			`#define WCRM 0x05 /* Wait Control M */`
20			`#define WCRH 0x06 /* Wait Control H */`
21
22			`#define PCR 0x08 /* DMA Priority Control */`
23			`#define DMER 0x09 /* DMA Master Enable */`
24
25
26			`/* Interrupt registers */`
27			`#define ISR0 0x10 /* Interrupt Status 0 */`
28			`#define ISR1 0x11 /* Interrupt Status 1 */`
29			`#define ISR2 0x12 /* Interrupt Status 2 */`
30
31			`#define IER0 0x14 /* Interrupt Enable 0 */`
32			`#define IER1 0x15 /* Interrupt Enable 1 */`
33			`#define IER2 0x16 /* Interrupt Enable 2 */`
34
35			`#define ITCR 0x18 /* Interrupt Control */`
36			`#define IVR 0x1A /* Interrupt Vector */`
37			`#define IMVR 0x1C /* Interrupt Modified Vector */`
38
39
40
41			`/* MSCI channel (port) 0 registers - offset 0x20`
42			`MSCI channel (port) 1 registers - offset 0x40 */`
43
44			`#define MSCI0_OFFSET 0x20`
45			`#define MSCI1_OFFSET 0x40`
46
47			`#define TRBL 0x00 /* TX/RX buffer L */`
48			`#define TRBH 0x01 /* TX/RX buffer H */`
49			`#define ST0 0x02 /* Status 0 */`
50			`#define ST1 0x03 /* Status 1 */`
51			`#define ST2 0x04 /* Status 2 */`
52			`#define ST3 0x05 /* Status 3 */`
53			`#define FST 0x06 /* Frame Status */`
54			`#define IE0 0x08 /* Interrupt Enable 0 */`
55			`#define IE1 0x09 /* Interrupt Enable 1 */`
56			`#define IE2 0x0A /* Interrupt Enable 2 */`
57			`#define FIE 0x0B /* Frame Interrupt Enable */`
58			`#define CMD 0x0C /* Command */`
59			`#define MD0 0x0E /* Mode 0 */`
60			`#define MD1 0x0F /* Mode 1 */`
61			`#define MD2 0x10 /* Mode 2 */`
62			`#define CTL 0x11 /* Control */`
63			`#define SA0 0x12 /* Sync/Address 0 */`
64			`#define SA1 0x13 /* Sync/Address 1 */`
65			`#define IDL 0x14 /* Idle Pattern */`
66			`#define TMC 0x15 /* Time Constant */`
67			`#define RXS 0x16 /* RX Clock Source */`
68			`#define TXS 0x17 /* TX Clock Source */`
69			`#define TRC0 0x18 /* TX Ready Control 0 */`
70			`#define TRC1 0x19 /* TX Ready Control 1 */`
71			`#define RRC 0x1A /* RX Ready Control */`
72			`#define CST0 0x1C /* Current Status 0 */`
73			`#define CST1 0x1D /* Current Status 1 */`
74
75
76			`/* Timer channel 0 (port 0 RX) registers - offset 0x60`
77			`Timer channel 1 (port 0 TX) registers - offset 0x68`
78			`Timer channel 2 (port 1 RX) registers - offset 0x70`
79			`Timer channel 3 (port 1 TX) registers - offset 0x78`
80			`*/`
81
82			`#define TIMER0RX_OFFSET 0x60`
83			`#define TIMER0TX_OFFSET 0x68`
84			`#define TIMER1RX_OFFSET 0x70`
85			`#define TIMER1TX_OFFSET 0x78`
86
87			`#define TCNTL 0x00 /* Up-counter L */`
88			`#define TCNTH 0x01 /* Up-counter H */`
89			`#define TCONRL 0x02 /* Constant L */`
90			`#define TCONRH 0x03 /* Constant H */`
91			`#define TCSR 0x04 /* Control/Status */`
92			`#define TEPR 0x05 /* Expand Prescale */`
93
94
95
96			`/* DMA channel 0 (port 0 RX) registers - offset 0x80`
97			`DMA channel 1 (port 0 TX) registers - offset 0xA0`
98			`DMA channel 2 (port 1 RX) registers - offset 0xC0`
99			`DMA channel 3 (port 1 TX) registers - offset 0xE0`
100			`*/`
101
102			`#define DMAC0RX_OFFSET 0x80`
103			`#define DMAC0TX_OFFSET 0xA0`
104			`#define DMAC1RX_OFFSET 0xC0`
105			`#define DMAC1TX_OFFSET 0xE0`
106
107			`#define BARL 0x00 /* Buffer Address L (chained block) */`
108			`#define BARH 0x01 /* Buffer Address H (chained block) */`
109			`#define BARB 0x02 /* Buffer Address B (chained block) */`
110
111			`#define DARL 0x00 /* RX Destination Addr L (single block) */`
112			`#define DARH 0x01 /* RX Destination Addr H (single block) */`
113			`#define DARB 0x02 /* RX Destination Addr B (single block) */`
114
115			`#define SARL 0x04 /* TX Source Address L (single block) */`
116			`#define SARH 0x05 /* TX Source Address H (single block) */`
117			`#define SARB 0x06 /* TX Source Address B (single block) */`
118
119			`#define CPB 0x06 /* Chain Pointer Base (chained block) */`
120
121			`#define CDAL 0x08 /* Current Descriptor Addr L (chained block) */`
122			`#define CDAH 0x09 /* Current Descriptor Addr H (chained block) */`
123			`#define EDAL 0x0A /* Error Descriptor Addr L (chained block) */`
124			`#define EDAH 0x0B /* Error Descriptor Addr H (chained block) */`
125			`#define BFLL 0x0C /* RX Receive Buffer Length L (chained block)*/`
126			`#define BFLH 0x0D /* RX Receive Buffer Length H (chained block)*/`
127			`#define BCRL 0x0E /* Byte Count L */`
128			`#define BCRH 0x0F /* Byte Count H */`
129			`#define DSR 0x10 /* DMA Status */`
130			`#define DSR_RX(node) (DSR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))`
131			`#define DSR_TX(node) (DSR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))`
132			`#define DMR 0x11 /* DMA Mode */`
133			`#define DMR_RX(node) (DMR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))`
134			`#define DMR_TX(node) (DMR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))`
135			`#define FCT 0x13 /* Frame End Interrupt Counter */`
136			`#define FCT_RX(node) (FCT + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))`
137			`#define FCT_TX(node) (FCT + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))`
138			`#define DIR 0x14 /* DMA Interrupt Enable */`
139			`#define DIR_RX(node) (DIR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))`
140			`#define DIR_TX(node) (DIR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))`
141			`#define DCR 0x15 /* DMA Command */`
142			`#define DCR_RX(node) (DCR + (node ? DMAC1RX_OFFSET : DMAC0RX_OFFSET))`
143			`#define DCR_TX(node) (DCR + (node ? DMAC1TX_OFFSET : DMAC0TX_OFFSET))`
144
145
146
147
148			`/* Descriptor Structure */`
149
150			`typedef struct {`
151			`u16 cp; /* Chain Pointer */`
152			`u32 bp; /* Buffer Pointer (24 bits) */`
153			`u16 len; /* Data Length */`
154			`u8 stat; /* Status */`
155			`u8 unused; /* pads to 2-byte boundary */`
156			`}__attribute__ ((packed)) pkt_desc;`
157
158
159			`/* Packet Descriptor Status bits */`
160
161			`#define ST_TX_EOM 0x80 /* End of frame */`
162			`#define ST_TX_EOT 0x01 /* End of transmition */`
163
164			`#define ST_RX_EOM 0x80 /* End of frame */`
165			`#define ST_RX_SHORT 0x40 /* Short frame */`
166			`#define ST_RX_ABORT 0x20 /* Abort */`
167			`#define ST_RX_RESBIT 0x10 /* Residual bit */`
168			`#define ST_RX_OVERRUN 0x08 /* Overrun */`
169			`#define ST_RX_CRC 0x04 /* CRC */`
170
171			`#define ST_ERROR_MASK 0x7C`
172
173			`#define DIR_EOTE 0x80 /* Transfer completed */`
174			`#define DIR_EOME 0x40 /* Frame Transfer Completed (chained-block) */`
175			`#define DIR_BOFE 0x20 /* Buffer Overflow/Underflow (chained-block)*/`
176			`#define DIR_COFE 0x10 /* Counter Overflow (chained-block) */`
177
178
179			`#define DSR_EOT 0x80 /* Transfer completed */`
180			`#define DSR_EOM 0x40 /* Frame Transfer Completed (chained-block) */`
181			`#define DSR_BOF 0x20 /* Buffer Overflow/Underflow (chained-block)*/`
182			`#define DSR_COF 0x10 /* Counter Overflow (chained-block) */`
183			`#define DSR_DE 0x02 /* DMA Enable */`
184			`#define DSR_DWE 0x01 /* DMA Write Disable */`
185
186			`/* DMA Master Enable Register (DMER) bits */`
187			`#define DMER_DME 0x80 /* DMA Master Enable */`
188
189
190			`#define CMD_RESET 0x21 /* Reset Channel */`
191			`#define CMD_TX_ENABLE 0x02 /* Start transmitter */`
192			`#define CMD_RX_ENABLE 0x12 /* Start receiver */`
193
194			`#define MD0_HDLC 0x80 /* Bit-sync HDLC mode */`
195			`#define MD0_CRC_ENA 0x04 /* Enable CRC code calculation */`
196			`#define MD0_CRC_CCITT 0x02 /* CCITT CRC instead of CRC-16 */`
197			`#define MD0_CRC_PR1 0x01 /* Initial all-ones instead of all-zeros */`
198
199			`#define MD0_CRC_NONE 0x00`
200			`#define MD0_CRC_16_0 0x04`
201			`#define MD0_CRC_16 0x05`
202			`#define MD0_CRC_ITU_0 0x06`
203			`#define MD0_CRC_ITU 0x07`
204
205			`#define MD2_NRZ 0x00`
206			`#define MD2_NRZI 0x20`
207			`#define MD2_MANCHESTER 0x80`
208			`#define MD2_FM_MARK 0xA0`
209			`#define MD2_FM_SPACE 0xC0`
210			`#define MD2_LOOPBACK 0x03 /* Local data Loopback */`
211
212			`#define CTL_NORTS 0x01`
213			`#define CTL_IDLE 0x10 /* Transmit an idle pattern */`
214			`#define CTL_UDRNC 0x20 /* Idle after CRC or FCS+flag transmition */`
215
216			`#define ST0_TXRDY 0x02 /* TX ready */`
217			`#define ST0_RXRDY 0x01 /* RX ready */`
218
219			`#define ST1_UDRN 0x80 /* MSCI TX underrun */`
220
221			`#define ST3_CTS 0x08 /* modem input - /CTS */`
222			`#define ST3_DCD 0x04 /* modem input - /DCD */`
223
224			`#define IE0_TXINT 0x80 /* TX INT MSCI interrupt enable */`
225			`#define IE1_UDRN 0x80 /* TX underrun MSCI interrupt enable */`
226
227			`#define DCR_ABORT 0x01 /* Software abort command */`
228			`#define DCR_CLEAR_EOF 0x02 /* Clear EOF interrupt */`
229
230			`/* TX and RX Clock Source - RXS and TXS */`
231			`#define CLK_BRG_MASK 0x0F`
232			`#define CLK_LINE_RX 0x00 /* TX/RX clock line input */`
233			`#define CLK_LINE_TX 0x00 /* TX/RX line input */`
234			`#define CLK_BRG_RX 0x40 /* internal baud rate generator */`
235			`#define CLK_BRG_TX 0x40 /* internal baud rate generator */`
236			`#define CLK_RXCLK_TX 0x60 /* TX clock from RX clock */`
237
238			`#endif`