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phoenix |
/* $Id: cs4231.h,v 1.1.1.1 2004-04-15 02:07:23 phoenix Exp $
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* drivers/sbus/audio/cs4231.h
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*
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* Copyright (C) 1996 Thomas K. Dyas (tdyas@noc.rutgers.edu)
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* Copyright (C) 1997 Derrick J. Brashear (shadow@dementia.org)
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* Copyright (C) 1999 David S. Miller (davem@redhat.com)
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*/
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#ifndef _CS4231_H_
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#define _CS4231_H_
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#include <linux/types.h>
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/* According to the CS4231A data provided on CS web site and sun's includes */
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#define IAR 0x00UL /* Index Address Register */
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#define IDR 0x04UL /* Index Data Register */
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#define STAT 0x08UL /* Status Register */
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#define PIOD 0x0cUL /* PIO Data Register */
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#define APCCSR 0x10UL /* APC DMA CSR */
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#define APCCVA 0x20UL /* APC Capture DMA Address */
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#define APCCC 0x24UL /* APC Capture Count */
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#define APCCNVA 0x28UL /* APC Capture DMA Next Address */
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#define APCCNC 0x2cUL /* APC Capture Next Count */
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#define APCPVA 0x30UL /* APC Play DMA Address */
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#define APCPC 0x34UL /* APC Play Count */
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#define APCPNVA 0x38UL /* APC Play DMA Next Address */
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#define APCPNC 0x3cUL /* APC Play Next Count */
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| 29 |
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/* EBUS DMA Registers */
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#define EBDMA_CSR 0x00UL /* Control/Status */
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#define EBDMA_ADDR 0x04UL /* DMA Address */
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#define EBDMA_COUNT 0x08UL /* DMA Count */
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/* Our structure for each chip */
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struct cs4231_chip {
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unsigned long regs;
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unsigned long eb2c;
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unsigned long eb2p;
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struct audio_info perchip_info;
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unsigned int playlen, reclen;
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int irq, irq2, nirqs;
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unsigned long regs_size;
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/* Keep track of various info */
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volatile unsigned int status;
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/* Current buffer that the driver is playing. */
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volatile __u8 * output_ptr;
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volatile __u32 output_size;
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volatile __u32 output_dma_handle, output_next_dma_handle;
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volatile __u32 output_dma_size, output_next_dma_size;
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/* Current record buffer. */
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volatile __u8 * input_ptr;
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volatile __u32 input_size;
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volatile __u32 input_dma_handle, input_next_dma_handle;
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volatile __u32 input_dma_size, input_next_dma_size;
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/* Number of buffers in the pipe. */
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volatile __u32 playing_count;
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volatile __u32 recording_count;
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};
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#ifdef EB4231_SUPPORT
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#define CS4231_READ32(__C, __REG) \
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(((__C)->status & CS_STATUS_IS_EBUS) ? \
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readl((__REG)) : \
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sbus_readl((__REG)))
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#define CS4231_READ8(__C, __REG) \
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(((__C)->status & CS_STATUS_IS_EBUS) ? \
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readb((__REG)) : \
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sbus_readb((__REG)))
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#define CS4231_WRITE32(__C, __REG, __VAL) \
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(((__C)->status & CS_STATUS_IS_EBUS) ? \
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writel((__VAL), (__REG)) : \
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sbus_writel((__VAL), (__REG)))
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#define CS4231_WRITE8(__C, __REG, __VAL) \
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(((__C)->status & CS_STATUS_IS_EBUS) ? \
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writeb((__VAL), (__REG)) : \
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sbus_writeb((__VAL), (__REG)))
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#else
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/* We can assume all is SBUS in this case. */
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#define CS4231_READ32(__C, __REG) sbus_readl((__REG))
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#define CS4231_READ8(__C, __REG) sbus_readb((__REG))
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#define CS4231_WRITE32(__C, __REG, __VAL) sbus_writel((__VAL), (__REG))
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#define CS4231_WRITE8(__C, __REG, __VAL) sbus_writeb((__VAL), (__REG))
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#endif
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/* Local status bits */
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#define CS_STATUS_NEED_INIT 0x01
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#define CS_STATUS_INIT_ON_CLOSE 0x02
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#define CS_STATUS_REV_A 0x04
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#define CS_STATUS_INTS_ON 0x08
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#define CS_STATUS_IS_ULTRA 0x10
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#define CS_STATUS_IS_EBUS 0x20
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#define CS_TIMEOUT 9000000
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#define GAIN_SET(var, gain) ((var & ~(0x3f)) | gain)
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#define RECGAIN_SET(var, gain) ((var & ~(0x1f)) | gain)
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| 102 |
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/* bits 0-3 set address of register accessed by idr register */
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/* bit 4 allows access to idr registers 16-31 in mode 2 only */
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/* bit 5 if set causes dma transfers to cease if the int bit of status set */
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#define IAR_AUTOCAL_BEGIN 0x40 /* MCE */
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#define IAR_NOT_READY 0x80 /* INIT */
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#define IAR_AUTOCAL_END ~(IAR_AUTOCAL_BEGIN) /* MCD */
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| 110 |
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/* Registers 1-15 modes 1 and 2. Registers 16-31 mode 2 only */
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/* Registers assumed to be same in both modes unless noted */
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| 112 |
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| 113 |
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/* 0 - Left Input Control */
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/* 1 - Right Input Control */
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#define MIC_ENABLE(var) ((var & 0x2f) | 0x80)
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#define LINE_ENABLE(var) (var & 0x2f)
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#define CDROM_ENABLE(var) ((var & 0x2f) | 0x40)
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#define OUTPUTLOOP_ENABLE(var) ((var & 0x2f) | 0xC0)
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#define INPUTCR_AUX1 0x40
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/* 2 - Left Aux 1 Input Control */
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/* 3 - Right Aux 1 Input Control */
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/* 4 - Left Aux 2 Input Control */
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/* 5 - Right Aux 2 Input Control */
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| 126 |
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/* 6 - Left Output Control */
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| 127 |
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/* 7 - Right Output Control */
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| 128 |
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#define OUTCR_MUTE 0x80
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#define OUTCR_UNMUTE ~0x80
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| 131 |
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/* 8 - Playback Data Format (Mode 2) */
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#define CHANGE_DFR(var, val) ((var & ~(0xF)) | val)
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#define CHANGE_ENCODING(var, val) ((var & ~(0xe0)) | val)
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#define DEFAULT_DATA_FMAT CS4231_DFR_ULAW
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#define CS4231_DFR_5512 0x01
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#define CS4231_DFR_6615 0x0f
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#define CS4231_DFR_8000 0x00
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#define CS4231_DFR_9600 0x0e
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#define CS4231_DFR_11025 0x03
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#define CS4231_DFR_16000 0x02
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#define CS4231_DFR_18900 0x05
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#define CS4231_DFR_22050 0x07
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#define CS4231_DFR_27429 0x04
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#define CS4231_DFR_32000 0x06
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#define CS4231_DFR_33075 0x0d
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#define CS4231_DFR_37800 0x09
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#define CS4231_DFR_44100 0x0b
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#define CS4231_DFR_48000 0x0c
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#define CS4231_DFR_LINEAR8 0x00
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#define CS4231_DFR_ULAW 0x20
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#define CS4231_DFR_LINEARLE 0x40
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#define CS4231_DFR_ALAW 0x60
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#define CS4231_DFR_ADPCM 0xa0 /* N/A in mode 1 */
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#define CS4231_DFR_LINEARBE 0xc0 /* N/A in mode 1 */
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#define CS4231_STEREO_ON(val) (val | 0x10)
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#define CS4231_MONO_ON(val) (val & ~0x10)
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| 158 |
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/* 9 - Interface Config. Register */
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#define PEN_ENABLE (0x01) /* Playback Enable */
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#define PEN_DISABLE (~0x01)
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#define CEN_ENABLE (0x02) /* Capture Enable */
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#define CEN_DISABLE (~0x02)
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#define SDC_ENABLE (0x04) /* Turn on single DMA Channel mode */
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#define ACAL_CONV 0x08 /* Turn on converter autocal */
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#define ACAL_DISABLE (~0x08)
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#define ACAL_DAC 0x10 /* Turn on DAC autocal */
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#define ACAL_FULL (ACAL_DAC|ACAL_CONV) /* Turn on full autocal */
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#define PPIO 0x20 /* do playback via PIO rather than DMA */
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#define CPIO 0x40 /* do capture via PIO rather than DMA */
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#define ICR_AUTOCAL_INIT 0x01
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/* 10 - Pin Control Register */
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#define INTR_ON 0x82
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#define INTR_OFF 0x80
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#define PINCR_LINE_MUTE 0x40
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#define PINCR_HDPH_MUTE 0x80
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/* 11 - Test/Initialization */
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#define DRQ_STAT 0x10
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#define AUTOCAL_IN_PROGRESS 0x20
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| 182 |
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/* 12 - Misc Information */
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#define MISC_IR_MODE2 0x40
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/* 13 - Loopback Control */
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#define LOOPB_ON 0x01
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#define LOOPB_OFF 0x00
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| 189 |
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/* 14 - shared play/capture upper (mode 1) */
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/* 15 - shared play/capture lower (mode 1) */
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| 192 |
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/* 14 - Playback Upper (mode 2) */
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/* 15 - Playback Lower (mode 2) */
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/* The rest are mode 2 only */
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| 197 |
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/* 16 - Alternate Feature 1 Enable */
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#define DAC_ZERO 0x01
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#define PLAY_MCE 0x10
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#define CAPTURE_MCE 0x20
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#define TIMER_ENABLE 0x40
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#define OLB_ENABLE 0x80 /* go to 2.88 vpp analog output */
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| 204 |
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/* 17 - Alternate Feature 2 Enable */
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#define HPF_ON 0x01 /* High Pass Filter */
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#define XTALE_ON 0x02 /* Enable both crystals */
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#define APAR_OFF 0x04 /* ADPCM playback accum reset */
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| 208 |
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| 209 |
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/* 18 - Left Line Input Gain */
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| 210 |
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/* 19 - Right Line Input Gain */
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| 212 |
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/* 20 - Timer High */
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/* 21 - Timer Low */
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/* 22 - unused */
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/* 23 - Alt. Fea. Ena 3 */
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#define ACF 0x01
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| 220 |
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/* 24 - Alternate Feature Status */
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#define CS_PU 0x01 /* Underrun */
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#define CS_PO 0x02 /* Overrun */
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#define CS_CU 0x04 /* Underrun */
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#define CS_CO 0x08 /* Overrun */
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#define CS_PI 0x10
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#define CS_CI 0x20
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#define CS_TI 0x40
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| 229 |
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/* 25 - Version */
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#define CS4231A 0x20
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#define CS4231CDE 0x80
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| 233 |
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/* 26 - Mono I/O Control */
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#define CHANGE_MONO_GAIN(val) ((val & ~(0xFF)) | val)
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#define MONO_IOCR_BYPASS 0x20
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#define MONO_IOCR_MUTE 0x40
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#define MONO_IOCR_INMUTE 0x80
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| 239 |
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/* 27 - Unused */
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| 240 |
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| 241 |
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/* 28 - Capture Data Format */
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| 242 |
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/* see register 8 */
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| 244 |
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/* 29 - Unused */
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| 245 |
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| 246 |
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/* 30 - Capture Upper */
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/* 31 - Capture Lower */
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| 248 |
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| 249 |
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/* Following are APC CSR register definitions for the Sparc */
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| 251 |
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#define APC_INT_PENDING 0x800000 /* Interrupt Pending */
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#define APC_PLAY_INT 0x400000 /* Playback interrupt */
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| 253 |
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#define APC_CAPT_INT 0x200000 /* Capture interrupt */
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| 254 |
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#define APC_GENL_INT 0x100000 /* General interrupt */
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| 255 |
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#define APC_XINT_ENA 0x80000 /* General ext int. enable */
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| 256 |
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#define APC_XINT_PLAY 0x40000 /* Playback ext intr */
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| 257 |
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#define APC_XINT_CAPT 0x20000 /* Capture ext intr */
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| 258 |
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#define APC_XINT_GENL 0x10000 /* Error ext intr */
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| 259 |
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#define APC_XINT_EMPT 0x8000 /* Pipe empty interrupt (0 write to pva) */
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| 260 |
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#define APC_XINT_PEMP 0x4000 /* Play pipe empty (pva and pnva not set) */
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| 261 |
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#define APC_XINT_PNVA 0x2000 /* Playback NVA dirty */
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| 262 |
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#define APC_XINT_PENA 0x1000 /* play pipe empty Int enable */
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| 263 |
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#define APC_XINT_COVF 0x800 /* Cap data dropped on floor */
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| 264 |
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#define APC_XINT_CNVA 0x400 /* Capture NVA dirty */
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| 265 |
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#define APC_XINT_CEMP 0x200 /* Capture pipe empty (cva and cnva not set) */
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| 266 |
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#define APC_XINT_CENA 0x100 /* Cap. pipe empty int enable */
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| 267 |
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#define APC_PPAUSE 0x80 /* Pause the play DMA */
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| 268 |
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#define APC_CPAUSE 0x40 /* Pause the capture DMA */
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| 269 |
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#define APC_CDC_RESET 0x20 /* CODEC RESET */
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| 270 |
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#define APC_PDMA_READY 0x08 /* Play DMA Go */
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| 271 |
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#define APC_CDMA_READY 0x04 /* Capture DMA Go */
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| 272 |
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#define APC_CHIP_RESET 0x01 /* Reset the chip */
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| 273 |
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| 274 |
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#define APC_INIT_SETUP (APC_CDMA_READY | APC_PDMA_READY | APC_XINT_ENA | \
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| 275 |
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APC_XINT_PLAY | APC_XINT_GENL | APC_INT_PENDING | \
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| 276 |
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APC_PLAY_INT | APC_CAPT_INT | APC_GENL_INT)
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| 277 |
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| 278 |
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#define APC_PLAY_SETUP (APC_GENL_INT | APC_PLAY_INT | APC_XINT_ENA | \
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| 279 |
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APC_XINT_PLAY | APC_XINT_EMPT | APC_XINT_GENL | \
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| 280 |
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APC_XINT_PENA | APC_PDMA_READY)
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| 281 |
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| 282 |
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#define APC_CAPT_SETUP (APC_GENL_INT | APC_CAPT_INT | APC_XINT_ENA | \
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| 283 |
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APC_XINT_CAPT | APC_XINT_CEMP | APC_XINT_GENL | \
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| 284 |
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APC_CDMA_READY)
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| 285 |
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| 286 |
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/* Following are EB2 CSR register definitions for the Sparc */
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| 287 |
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| 288 |
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/* asm/ebus.h has the base settings */
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| 289 |
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| 290 |
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#define EB2_PLAY_SETUP (EBUS_DCSR_BURST_SZ_8 | EBUS_DCSR_INT_EN | EBUS_DCSR_EN_DMA | \
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| 291 |
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EBUS_DCSR_EN_CNT | EBUS_DCSR_TC)
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| 292 |
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#define EB2_CAPT_SETUP (EBUS_DCSR_BURST_SZ_8 | EBUS_DCSR_INT_EN | EBUS_DCSR_EN_DMA| \
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| 293 |
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EBUS_DCSR_EN_CNT | EBUS_DCSR_TC | EBUS_DCSR_WRITE)
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| 294 |
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| 295 |
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#define CS4231_MIN_ATEN (0)
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| 296 |
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#define CS4231_MAX_ATEN (31)
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| 297 |
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#define CS4231_MAX_DEV_ATEN (63)
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| 298 |
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| 299 |
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#define CS4231_MON_MIN_ATEN (0)
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| 300 |
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#define CS4231_MON_MAX_ATEN (63)
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| 301 |
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| 302 |
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#define CS4231_DEFAULT_PLAYGAIN (132)
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| 303 |
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#define CS4231_DEFAULT_RECGAIN (126)
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| 304 |
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| 305 |
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#define CS4231_MIN_GAIN (0)
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| 306 |
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#define CS4231_MAX_GAIN (15)
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| 307 |
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| 308 |
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#define CS4231_PRECISION (8) /* # of bits/sample */
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| 309 |
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#define CS4231_CHANNELS (1) /* channels/sample */
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| 310 |
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| 311 |
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#define CS4231_RATE (8000) /* default sample rate */
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| 312 |
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| 313 |
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#endif /* _CS4231_H_ */
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